OpenCores
URL https://opencores.org/ocsvn/line_codes/line_codes/trunk

Subversion Repositories line_codes

[/] [line_codes/] [trunk/] [bench/] [vhdl/] [smlt_ami_dec.vhd] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ribamar
-- smlttion for AMI decoder. 
2
 
3
entity smlt_ami_dec is
4
end smlt_ami_dec;
5
 
6
architecture behaviour of smlt_ami_dec is
7
        --data type: 
8
        component ami_dec
9
        port (
10
                clr_bar,
11
                e0, e1: in  bit;
12
                s     : out bit);
13
        end component;
14
        --binding: 
15
        for a: ami_dec use entity work.ami_dec;
16
 
17
        --declaring the signals present in this architecture: 
18
        signal CLK, S, E0, E1, clrb: bit;
19
        signal input0, input1: bit_vector(0 to 26);
20
 
21
        begin --architecture. 
22
                a: ami_dec port map
23
                ( clr_bar => clrb, e0 => E0, e1 => E1, s => S );
24
 
25
                input0 <= "000100010000100100001000010";
26
                input1 <= "000001001000001000100000101";
27
 
28
        process begin
29
                clrb <= '1';
30
                for i in 0 to 26 loop
31
                        E0 <= input0(i);
32
                        E1 <= input1(i);
33
                        CLK <= '0';
34
                        wait for 9 ns;
35
                        CLK <= '1';
36
                        wait for 1 ns;
37
                end loop;
38
                wait;
39
        end process;
40
 
41
 
42
end behaviour;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.