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[/] [loadbalancer/] [trunk/] [Balance/] [balance.vhd] - Blame information for rev 2

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--------------------------------------------------------
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use ieee.numeric_std.all;
        use IEEE.STD_LOGIC_ARITH.ALL;
        use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------
        ENTITY  balance IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
                        SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                        SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                        SIGNAL in_wr :IN STD_LOGIC;
                        SIGNAL in_rdy : OUT STD_LOGIC;
 
                        SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
                        SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
                        SIGNAL out_wr : OUT STD_LOGIC;
                        SIGNAL out_rdy : IN STD_LOGIC;
 
                        SIGNAL in_next_mac :IN   STD_LOGIC_VECTOR(47 DOWNTO 0);
                        SIGNAL in_exit_port :IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                        SIGNAL in_next_mac_rdy : IN STD_LOGIC;
                        SIGNAL out_rd_next_mac : OUT STD_LOGIC;
                        SIGNAL key :OUT   STD_LOGIC_VECTOR(11 DOWNTO 0);
 
                   SIGNAL reset :IN STD_LOGIC;
                   SIGNAL clk   :IN STD_LOGIC
 
        );
        END ENTITY;
        -----------------------------------------------------
        ARCHITECTURE behavior OF balance IS
-------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
                                GENERIC(WIDTH :INTEGER := 72;
                                                MAX_DEPTH_BITS :INTEGER := 3);
                                PORT(
                                         SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         SIGNAL wr_en : IN STD_LOGIC;
                                         SIGNAL rd_en : IN STD_LOGIC;
                                         SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         SIGNAL full : OUT STD_LOGIC;
                                         SIGNAL nearly_full : OUT STD_LOGIC;
                                         SIGNAL empty : OUT STD_LOGIC;
                                         SIGNAL reset :IN STD_LOGIC;
                                         SIGNAL clk   :IN STD_LOGIC
                                );
                END COMPONENT;
-------COMPONENET SMALL FIFO
------COMPONENT vlan2ext
        COMPONENT        n_mac IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
    SIGNAL              in_wr                           :       IN              STD_LOGIC       ;
 
        SIGNAL rd_next_mac : OUT STD_LOGIC;
        SIGNAL key :OUT   STD_LOGIC_VECTOR(11 DOWNTO 0);
 
    --- Misc
 
    SIGNAL              reset                           :       IN              STD_LOGIC       ;
    SIGNAL              clk                             :       IN              STD_LOGIC
        );
        END COMPONENT n_mac;
------COMPONENT vlan2ext
------------ one hot encoding state definition
 
        TYPE state_type IS (IDLE, IN_MODULE_HDRS, WORD_1, IN_PACKET);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_NEXT : state_type;
 
------------end state machine definition
 
----------------------FIFO        
          SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
          SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_rd_en : STD_LOGIC;
          SIGNAL in_fifo_go : STD_LOGIC;
          SIGNAL in_fifo_rd_en_p : STD_LOGIC;
      SIGNAL in_fifo_dout  : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_full : STD_LOGIC;
      SIGNAL in_fifo_nearly_full : STD_LOGIC;
      SIGNAL in_fifo_empty : STD_LOGIC;
------------------------------
          SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(55 DOWNTO 0);
      SIGNAL ctrl_fifo_rd : STD_LOGIC;
      SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(55 DOWNTO 0);
      SIGNAL ctrl_fifo_full : STD_LOGIC;
      SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;
      SIGNAL ctrl_fifo_empty : STD_LOGIC;
--        SIGNAL cnt : INTEGER; 
 
          SIGNAL                out_data_i                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                out_ctrl_i                      :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                out_wr_i                        :               STD_LOGIC       ;
 
 
---------------------------------------------------
        BEGIN
 
 
        ------PORT MAP open_header
        n_mac_Inst : n_mac
        GENERIC MAP (DATA_WIDTH  => 64,
                        CTRL_WIDTH => 8)
        PORT MAP(
                        in_data                         =>      in_data,
                        in_ctrl                         =>      in_ctrl ,
                in_wr                           =>      in_wr,
                        rd_next_mac             =>  out_rd_next_mac,
                        key                             =>  key,
                reset                           =>      reset,
                clk                             =>      clk
        );
 
        ------PORT MAP open_header
 
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst1 :  small_fifo
                GENERIC MAP(WIDTH  => 72,
                                MAX_DEPTH_BITS  => 5)
                        PORT MAP(
                                  din =>in_fifo_in,
                                  wr_en =>in_wr,
                                  rd_en => in_fifo_rd_en,
                                  dout =>in_fifo_dout,
                                  full =>in_fifo_full,
                                  nearly_full =>in_fifo_nearly_full,
                                  empty => in_fifo_empty,
                                  reset => reset ,
                                  clk  => clk
                        );
 
 
 
-------PORT MAP SMALL FIFO
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst_ctrl :  small_fifo
        GENERIC MAP(WIDTH  => 56,
                        MAX_DEPTH_BITS  => 5)
                                PORT MAP(
                                  din =>ctrl_fifo_in,
                                  wr_en =>in_next_mac_rdy,
                                  rd_en => ctrl_fifo_rd,
                                  dout =>ctrl_fifo_dout,
                                  full =>ctrl_fifo_full,
                                  nearly_full =>ctrl_fifo_nearly_full,
                                  empty => ctrl_fifo_empty,
                                  reset => reset ,
                                  clk  => clk
                                );
 
 
-----------------------
        in_fifo_in      <=      in_data & in_ctrl ;
                fifo_data       <=         in_fifo_dout(71 DOWNTO 8)    ;
                fifo_ctrl       <=      in_fifo_dout(7 DOWNTO 0) ;
                ctrl_fifo_in <= in_next_mac & in_exit_port;
                in_fifo_rd_en <=out_rdy AND (NOT in_fifo_empty) AND in_fifo_go;
                 in_rdy         <=      (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full)       ;
--      in_rdy  <=      (NOT in_fifo_nearly_full)       ;       
                PROCESS(clk,reset)
                BEGIN
                        IF (reset ='1') THEN
                                state <=IDLE;
                                ELSIF clk'EVENT AND clk ='1' THEN
                                state<=state_next;
                        END IF;
                END PROCESS;
                PROCESS(clk,reset)
                        BEGIN
                                IF (reset ='1') THEN
                                        in_fifo_rd_en_p <='0';
                                ELSIF clk'EVENT AND clk ='1' THEN
                                        in_fifo_rd_en_p <=in_fifo_rd_en;
                                END IF;
                END PROCESS;
 
PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)
        BEGIN
                                                        state_next                              <=      state;
                                                        out_data_i                              <=  fifo_data ;
                                                        out_ctrl_i                              <=  fifo_ctrl ;
                                                        out_wr_i                                   <=  in_fifo_rd_en_p ;
                                                        ctrl_fifo_rd                    <=      '0'      ;
                                                        in_fifo_go                              <=      '0'      ;
 
                CASE state IS
                        WHEN IDLE =>
                                   IF(ctrl_fifo_empty = '0') THEN
                                                                   ctrl_fifo_rd                         <=      '1'     ;
                                                                   in_fifo_go                           <=      '1'     ;
                                                                   state_next                           <=  IN_MODULE_HDRS;
                                        END IF;
                        WHEN IN_MODULE_HDRS =>
                                                        in_fifo_go                              <=      '1'     ;
                                                        IF ( in_fifo_rd_en_p ='1'  )THEN
                                                                out_data_i(55 downto 48)<=       X"01";--ctrl_fifo_dout(7 DOWNTO 0) ;                                                           
                                                                state_next              <=  WORD_1;
                                                        END IF;
                        WHEN WORD_1     =>
                                                                in_fifo_go                              <=      '1'     ;
                                                        IF ( in_fifo_rd_en_p ='1'  ) THEN
                                                                out_data_i(63 downto 16)<=       ctrl_fifo_dout (55 DOWNTO 8);
                                                                state_next              <=   IN_PACKET;
                                                                END IF;
                        WHEN IN_PACKET  =>
                                                                in_fifo_go                              <=      '1'     ;
                                                        IF ( fifo_ctrl /=X"00" ) THEN
                                                                in_fifo_go                              <=      '0'      ;
                                                        state_next              <=   IDLE;
                                                END IF;
 
                        END CASE;
        END PROCESS;
---------------Register output
 
 
                PROCESS(clk,reset)
                BEGIN
 
                        IF clk'EVENT AND clk ='1' THEN
                                                                        out_data                                <=      out_data_i;
                                                                        out_ctrl                                <=      out_ctrl_i;
                                                                        out_wr                                  <=      out_wr_i;
                        END IF;
                END PROCESS;
END behavior;
 

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Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [Balance/] [balance.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2			`LIBRARY IEEE;`
3			`USE IEEE.STD_LOGIC_1164.ALL;`
4			`use ieee.numeric_std.all;`
5			`use IEEE.STD_LOGIC_ARITH.ALL;`
6			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
7
8			`-------------------------------`
9			`ENTITY balance IS`
10			`GENERIC(DATA_WIDTH :INTEGER := 64;`
11			`CTRL_WIDTH :INTEGER := 8);`
12			`PORT(`
13
14			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
15			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
16			`SIGNAL in_wr :IN STD_LOGIC;`
17			`SIGNAL in_rdy : OUT STD_LOGIC;`
18
19			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
20			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
21			`SIGNAL out_wr : OUT STD_LOGIC;`
22			`SIGNAL out_rdy : IN STD_LOGIC;`
23
24			`SIGNAL in_next_mac :IN STD_LOGIC_VECTOR(47 DOWNTO 0);`
25			`SIGNAL in_exit_port :IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
26			`SIGNAL in_next_mac_rdy : IN STD_LOGIC;`
27			`SIGNAL out_rd_next_mac : OUT STD_LOGIC;`
28			`SIGNAL key :OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
29
30			`SIGNAL reset :IN STD_LOGIC;`
31			`SIGNAL clk :IN STD_LOGIC`
32
33			`);`
34			`END ENTITY;`
35			`-----------------------------------------------------`
36			`ARCHITECTURE behavior OF balance IS`
37			`-------COMPONENET SMALL FIFO`
38			`COMPONENT small_fifo IS`
39			`GENERIC(WIDTH :INTEGER := 72;`
40			`MAX_DEPTH_BITS :INTEGER := 3);`
41			`PORT(`
42			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);`
43			`SIGNAL wr_en : IN STD_LOGIC;`
44			`SIGNAL rd_en : IN STD_LOGIC;`
45			`SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);`
46			`SIGNAL full : OUT STD_LOGIC;`
47			`SIGNAL nearly_full : OUT STD_LOGIC;`
48			`SIGNAL empty : OUT STD_LOGIC;`
49			`SIGNAL reset :IN STD_LOGIC;`
50			`SIGNAL clk :IN STD_LOGIC`
51			`);`
52			`END COMPONENT;`
53			`-------COMPONENET SMALL FIFO`
54			`------COMPONENT vlan2ext`
55			`COMPONENT n_mac IS`
56			`GENERIC(DATA_WIDTH :INTEGER := 64;`
57			`CTRL_WIDTH :INTEGER := 8);`
58			`PORT(`
59			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
60			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
61			`SIGNAL in_wr : IN STD_LOGIC ;`
62
63			`SIGNAL rd_next_mac : OUT STD_LOGIC;`
64			`SIGNAL key :OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
65
66			`--- Misc`
67
68			`SIGNAL reset : IN STD_LOGIC ;`
69			`SIGNAL clk : IN STD_LOGIC`
70			`);`
71			`END COMPONENT n_mac;`
72			`------COMPONENT vlan2ext`
73			`------------ one hot encoding state definition`
74
75			`TYPE state_type IS (IDLE, IN_MODULE_HDRS, WORD_1, IN_PACKET);`
76			`ATTRIBUTE enum_encoding: STRING;`
77			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
78
79			`SIGNAL state, state_NEXT : state_type;`
80
81			`------------end state machine definition`
82
83			`----------------------FIFO`
84			`SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);`
85			`SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);`
86			`SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
87			`SIGNAL in_fifo_rd_en : STD_LOGIC;`
88			`SIGNAL in_fifo_go : STD_LOGIC;`
89			`SIGNAL in_fifo_rd_en_p : STD_LOGIC;`
90			`SIGNAL in_fifo_dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
91			`SIGNAL in_fifo_full : STD_LOGIC;`
92			`SIGNAL in_fifo_nearly_full : STD_LOGIC;`
93			`SIGNAL in_fifo_empty : STD_LOGIC;`
94			`------------------------------`
95			`SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(55 DOWNTO 0);`
96			`SIGNAL ctrl_fifo_rd : STD_LOGIC;`
97			`SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(55 DOWNTO 0);`
98			`SIGNAL ctrl_fifo_full : STD_LOGIC;`
99			`SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;`
100			`SIGNAL ctrl_fifo_empty : STD_LOGIC;`
101			`-- SIGNAL cnt : INTEGER;`
102
103			`SIGNAL out_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
104			`SIGNAL out_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
105			`SIGNAL out_wr_i : STD_LOGIC ;`
106
107
108			`---------------------------------------------------`
109			`BEGIN`
110
111
112			`------PORT MAP open_header`
113			`n_mac_Inst : n_mac`
114			`GENERIC MAP (DATA_WIDTH => 64,`
115			`CTRL_WIDTH => 8)`
116			`PORT MAP(`
117			`in_data => in_data,`
118			`in_ctrl => in_ctrl ,`
119			`in_wr => in_wr,`
120			`rd_next_mac => out_rd_next_mac,`
121			`key => key,`
122			`reset => reset,`
123			`clk => clk`
124			`);`
125
126			`------PORT MAP open_header`
127
128			`-------PORT MAP SMALL FIFO DATA`
129			`small_fifo_Inst1 : small_fifo`
130			`GENERIC MAP(WIDTH => 72,`
131			`MAX_DEPTH_BITS => 5)`
132			`PORT MAP(`
133			`din =>in_fifo_in,`
134			`wr_en =>in_wr,`
135			`rd_en => in_fifo_rd_en,`
136			`dout =>in_fifo_dout,`
137			`full =>in_fifo_full,`
138			`nearly_full =>in_fifo_nearly_full,`
139			`empty => in_fifo_empty,`
140			`reset => reset ,`
141			`clk => clk`
142			`);`
143
144
145
146			`-------PORT MAP SMALL FIFO`
147			`-------PORT MAP SMALL FIFO DATA`
148			`small_fifo_Inst_ctrl : small_fifo`
149			`GENERIC MAP(WIDTH => 56,`
150			`MAX_DEPTH_BITS => 5)`
151			`PORT MAP(`
152			`din =>ctrl_fifo_in,`
153			`wr_en =>in_next_mac_rdy,`
154			`rd_en => ctrl_fifo_rd,`
155			`dout =>ctrl_fifo_dout,`
156			`full =>ctrl_fifo_full,`
157			`nearly_full =>ctrl_fifo_nearly_full,`
158			`empty => ctrl_fifo_empty,`
159			`reset => reset ,`
160			`clk => clk`
161			`);`
162
163
164			`-----------------------`
165			`in_fifo_in <= in_data & in_ctrl ;`
166			`fifo_data <= in_fifo_dout(71 DOWNTO 8) ;`
167			`fifo_ctrl <= in_fifo_dout(7 DOWNTO 0) ;`
168			`ctrl_fifo_in <= in_next_mac & in_exit_port;`
169			`in_fifo_rd_en <=out_rdy AND (NOT in_fifo_empty) AND in_fifo_go;`
170			`in_rdy <= (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full) ;`
171			`-- in_rdy <= (NOT in_fifo_nearly_full) ;`
172			`PROCESS(clk,reset)`
173			`BEGIN`
174			`IF (reset ='1') THEN`
175			`state <=IDLE;`
176			`ELSIF clk'EVENT AND clk ='1' THEN`
177			`state<=state_next;`
178			`END IF;`
179			`END PROCESS;`
180			`PROCESS(clk,reset)`
181			`BEGIN`
182			`IF (reset ='1') THEN`
183			`in_fifo_rd_en_p <='0';`
184			`ELSIF clk'EVENT AND clk ='1' THEN`
185			`in_fifo_rd_en_p <=in_fifo_rd_en;`
186			`END IF;`
187			`END PROCESS;`
188
189			`PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)`
190			`BEGIN`
191			`state_next <= state;`
192			`out_data_i <= fifo_data ;`
193			`out_ctrl_i <= fifo_ctrl ;`
194			`out_wr_i <= in_fifo_rd_en_p ;`
195			`ctrl_fifo_rd <= '0' ;`
196			`in_fifo_go <= '0' ;`
197
198			`CASE state IS`
199			`WHEN IDLE =>`
200			`IF(ctrl_fifo_empty = '0') THEN`
201			`ctrl_fifo_rd <= '1' ;`
202			`in_fifo_go <= '1' ;`
203			`state_next <= IN_MODULE_HDRS;`
204			`END IF;`
205			`WHEN IN_MODULE_HDRS =>`
206			`in_fifo_go <= '1' ;`
207			`IF ( in_fifo_rd_en_p ='1' )THEN`
208			`out_data_i(55 downto 48)<= X"01";--ctrl_fifo_dout(7 DOWNTO 0) ;`
209			`state_next <= WORD_1;`
210			`END IF;`
211			`WHEN WORD_1 =>`
212			`in_fifo_go <= '1' ;`
213			`IF ( in_fifo_rd_en_p ='1' ) THEN`
214			`out_data_i(63 downto 16)<= ctrl_fifo_dout (55 DOWNTO 8);`
215			`state_next <= IN_PACKET;`
216			`END IF;`
217			`WHEN IN_PACKET =>`
218			`in_fifo_go <= '1' ;`
219			`IF ( fifo_ctrl /=X"00" ) THEN`
220			`in_fifo_go <= '0' ;`
221			`state_next <= IDLE;`
222			`END IF;`
223
224			`END CASE;`
225			`END PROCESS;`
226			`---------------Register output`
227
228
229			`PROCESS(clk,reset)`
230			`BEGIN`
231
232			`IF clk'EVENT AND clk ='1' THEN`
233			`out_data <= out_data_i;`
234			`out_ctrl <= out_ctrl_i;`
235			`out_wr <= out_wr_i;`
236			`END IF;`
237			`END PROCESS;`
238			`END behavior;`
239