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[/] [loadbalancer/] [trunk/] [Balance/] [n_mac.vhd] - Blame information for rev 2

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--------------------------------------------------------
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use ieee.numeric_std.all;
        use IEEE.STD_LOGIC_ARITH.ALL;
        use IEEE.STD_LOGIC_UNSIGNED.ALL;
        USE WORK.CONFIG.ALL;
-------------------------------
        ENTITY n_mac IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
    SIGNAL              in_wr                           :       IN              STD_LOGIC       ;
 
        SIGNAL rd_next_mac : OUT STD_LOGIC;
        SIGNAL key :OUT   STD_LOGIC_VECTOR(11 DOWNTO 0);
 
    --- Misc
 
    SIGNAL              reset                           :       IN              STD_LOGIC       ;
    SIGNAL              clk                             :       IN              STD_LOGIC
        );
        END ENTITY n_mac;
 
 ------------------------------------------------------
        ARCHITECTURE behavior OF n_mac IS
        ----------------
        COMPONENT hash IS
                GENERIC(
                        KEY_WIDTH       :       NATURAL := 48;--Hash key width
                        ADD_WIDTH       :       NATURAL := 12; --address width
                        HASH_NO         :       NATURAL := 4 --Hash number
                );
                PORT (
                        key             :       STD_LOGIC_VECTOR(47 DOWNTO 0);   --Hash key 
                        address         :       OUT STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0)               --address 
                );
        END COMPONENT hash;
---------------------------------
------------ one hot encoding state definition
        TYPE state_type is (READ_HEADER, READ_WORD_1, READ_WORD_2);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_NEXT : state_type;
 
        SIGNAL          src_mac_p1                      :       STD_LOGIC;
        SIGNAL          src_mac_p2                      :       STD_LOGIC;
        SIGNAL          rd_next_mac_i           :       STD_LOGIC;
        SIGNAL          src_mac                         :       STD_LOGIC_VECTOR(47 DOWNTO 0);
 
 
        BEGIN
---------------------------------------------
--      hash_Inst :  hash 
--              GENERIC MAP(
--                      KEY_WIDTH       => 48,  ADD_WIDTH       => 12,  HASH_NO         => 1 --Hash number
--              )
--              PORT MAP(
--                      key             =>src_mac,      --Hash key 
--                      address         =>key           --address 
--              );
 
        PROCESS(reset,clk)
                BEGIN
                        IF (reset ='1') THEN
                                state <=READ_HEADER;
                        ELSIF clk'EVENT AND clk ='1' THEN
                                state<=state_next;
                        END IF;
                END PROCESS;
 
                PROCESS(state , in_ctrl , in_wr)
                BEGIN
                                                                                                        state_next                                 <=  state;
                                                                                                        src_mac_p1                                 <= '0' ;
                                                                                                        src_mac_p2                                 <= '0' ;
                        CASE state IS
                                WHEN READ_HEADER =>
                                        IF( in_wr = '1' AND in_ctrl=X"FF"  ) THEN
                                                                                                        src_mac_p1                                 <= '1' ;
                                                                                                        src_mac_p2                                 <= '1' ;
                                                                                                        state_next                 <=  READ_WORD_1;
                                        END IF;
                                WHEN READ_WORD_1 =>
                                        IF( in_wr = '1') THEN
--                                                                                                      src_mac_p1                                 <= '1' ;
                                                                                                        state_next                <=  READ_WORD_2;
                                                END IF;
                                WHEN READ_WORD_2 =>
 
                                        IF(in_wr = '1' ) THEN
--                                                                                                      src_mac_p2                                <= '1' ;
                                                                                                        state_next                <= READ_HEADER;
                                        END IF;
                                WHEN OTHERS =>
                                                                                                        state_next                <= READ_HEADER;
                        END CASE;
                END PROCESS;
 
                PROCESS(clk)
                BEGIN
                        IF clk'EVENT AND clk ='1'  THEN
 
--                                      IF  src_mac_p1 = '1' THEN
--                                                      src_mac(47 downto 32)<= in_data(15 downto 0);
--                                      END IF;
--                                      IF  src_mac_p2 = '1' THEN
--                                                      src_mac(31 downto 0)<= in_data(63 downto 32);
--                                                      
--                                      END IF;
                                        rd_next_mac <= src_mac_p2;
--                                      rd_next_mac_i <= src_mac_p2;
                        END IF;
                END PROCESS;
 
 
END behavior;
 

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2			`LIBRARY IEEE;`
3			`USE IEEE.STD_LOGIC_1164.ALL;`
4			`use ieee.numeric_std.all;`
5			`use IEEE.STD_LOGIC_ARITH.ALL;`
6			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
7			`USE WORK.CONFIG.ALL;`
8			`-------------------------------`
9			`ENTITY n_mac IS`
10			`GENERIC(DATA_WIDTH :INTEGER := 64;`
11			`CTRL_WIDTH :INTEGER := 8);`
12			`PORT(`
13			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
14			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
15			`SIGNAL in_wr : IN STD_LOGIC ;`
16
17			`SIGNAL rd_next_mac : OUT STD_LOGIC;`
18			`SIGNAL key :OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
19
20			`--- Misc`
21
22			`SIGNAL reset : IN STD_LOGIC ;`
23			`SIGNAL clk : IN STD_LOGIC`
24			`);`
25			`END ENTITY n_mac;`
26
27			`------------------------------------------------------`
28			`ARCHITECTURE behavior OF n_mac IS`
29			`----------------`
30			`COMPONENT hash IS`
31			`GENERIC(`
32			`KEY_WIDTH : NATURAL := 48;--Hash key width`
33			`ADD_WIDTH : NATURAL := 12; --address width`
34			`HASH_NO : NATURAL := 4 --Hash number`
35			`);`
36			`PORT (`
37			`key : STD_LOGIC_VECTOR(47 DOWNTO 0); --Hash key`
38			`address : OUT STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0) --address`
39			`);`
40			`END COMPONENT hash;`
41			`---------------------------------`
42			`------------ one hot encoding state definition`
43			`TYPE state_type is (READ_HEADER, READ_WORD_1, READ_WORD_2);`
44			`ATTRIBUTE enum_encoding: STRING;`
45			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
46
47			`SIGNAL state, state_NEXT : state_type;`
48
49			`SIGNAL src_mac_p1 : STD_LOGIC;`
50			`SIGNAL src_mac_p2 : STD_LOGIC;`
51			`SIGNAL rd_next_mac_i : STD_LOGIC;`
52			`SIGNAL src_mac : STD_LOGIC_VECTOR(47 DOWNTO 0);`
53
54
55			`BEGIN`
56			`---------------------------------------------`
57			`-- hash_Inst : hash`
58			`-- GENERIC MAP(`
59			`-- KEY_WIDTH => 48, ADD_WIDTH => 12, HASH_NO => 1 --Hash number`
60			`-- )`
61			`-- PORT MAP(`
62			`-- key =>src_mac, --Hash key`
63			`-- address =>key --address`
64			`-- );`
65
66			`PROCESS(reset,clk)`
67			`BEGIN`
68			`IF (reset ='1') THEN`
69			`state <=READ_HEADER;`
70			`ELSIF clk'EVENT AND clk ='1' THEN`
71			`state<=state_next;`
72			`END IF;`
73			`END PROCESS;`
74
75			`PROCESS(state , in_ctrl , in_wr)`
76			`BEGIN`
77			`state_next <= state;`
78			`src_mac_p1 <= '0' ;`
79			`src_mac_p2 <= '0' ;`
80			`CASE state IS`
81			`WHEN READ_HEADER =>`
82			`IF( in_wr = '1' AND in_ctrl=X"FF" ) THEN`
83			`src_mac_p1 <= '1' ;`
84			`src_mac_p2 <= '1' ;`
85			`state_next <= READ_WORD_1;`
86			`END IF;`
87			`WHEN READ_WORD_1 =>`
88			`IF( in_wr = '1') THEN`
89			`-- src_mac_p1 <= '1' ;`
90			`state_next <= READ_WORD_2;`
91			`END IF;`
92			`WHEN READ_WORD_2 =>`
93
94			`IF(in_wr = '1' ) THEN`
95			`-- src_mac_p2 <= '1' ;`
96			`state_next <= READ_HEADER;`
97			`END IF;`
98			`WHEN OTHERS =>`
99			`state_next <= READ_HEADER;`
100			`END CASE;`
101			`END PROCESS;`
102
103			`PROCESS(clk)`
104			`BEGIN`
105			`IF clk'EVENT AND clk ='1' THEN`
106
107			`-- IF src_mac_p1 = '1' THEN`
108			`-- src_mac(47 downto 32)<= in_data(15 downto 0);`
109			`-- END IF;`
110			`-- IF src_mac_p2 = '1' THEN`
111			`-- src_mac(31 downto 0)<= in_data(63 downto 32);`
112			`--`
113			`-- END IF;`
114			`rd_next_mac <= src_mac_p2;`
115			`-- rd_next_mac_i <= src_mac_p2;`
116			`END IF;`
117			`END PROCESS;`
118
119
120			`END behavior;`
121

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Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [Balance/] [n_mac.vhd] - Blame information for rev 2