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[/] [loadbalancer/] [trunk/] [Classfier/] [classifier.vhd] - Blame information for rev 2

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--------------------------------------------------------
 
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use IEEE.std_logic_arith.all;
-------------------------------
        ENTITY classifier IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
    SIGNAL              in_wr                           :       IN              STD_LOGIC       ;
        SIGNAL          in_rdy                          :       OUT     STD_LOGIC       ;
 
        SIGNAL          out_data                        :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          out_ctrl                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
        SIGNAL          out_wr                          :       OUT     STD_LOGIC       ;
        SIGNAL          out_rdy                         :       IN              STD_LOGIC       ;
 
    --- Misc
    SIGNAL              dest                    :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
    SIGNAL              reset                           :       IN              STD_LOGIC       ;
    SIGNAL              clk                             :       IN              STD_LOGIC
        );
        END ENTITY;
 
 ------------------------------------------------------
        ARCHITECTURE behavior OF classifier IS
-------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
        GENERIC(WIDTH :INTEGER := 72;
                        MAX_DEPTH_BITS :INTEGER := 3);
        PORT(
 
 
     SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
     SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
 
     SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word 
 
     SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
     SIGNAL full : OUT STD_LOGIC;--output         full,
     SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
     SIGNAL empty : OUT STD_LOGIC;--output         empty,
 
 
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT;
-------COMPONENET SMALL FIFO
------COMPONENT open_header
        COMPONENT open_header IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
    SIGNAL              in_wr                           :       IN              STD_LOGIC       ;
 
        SIGNAL          pkt_type                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
        SIGNAL          pkt_type_rdy            :       OUT     STD_LOGIC       ;
    SIGNAL              pkt_type_rdy_ack                :       IN      STD_LOGIC       ;
         --- Misc
 
    SIGNAL              reset                           :       IN              STD_LOGIC       ;
    SIGNAL              clk                             :       IN              STD_LOGIC
        );
        END COMPONENT;
------COMPONENT open_header
------------ one hot encoding state definition
 
        TYPE state_type IS (IDLE, IN_MODULE_HDRS,SKIP_HDRS, IN_PACKET, DUMP_1 ,DUMP_2 ,DUMP_3, DUMP_4, DUMP_5);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_NEXT : state_type;
 
------------end state machine definition
 
----------------------FIFO        
          SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
          SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_rd_en : STD_LOGIC;
          SIGNAL in_fifo_rd_en_p : STD_LOGIC;
          SIGNAL in_fifo_go : STD_LOGIC;
          SIGNAL in_fifo_go_i : STD_LOGIC;
      SIGNAL in_fifo_dout  : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_full : STD_LOGIC;
      SIGNAL in_fifo_nearly_full : STD_LOGIC;
      SIGNAL in_fifo_empty : STD_LOGIC;
------------------------------
          SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(7 DOWNTO 0);
      SIGNAL ctrl_fifo_rd : STD_LOGIC;
      SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
      SIGNAL ctrl_fifo_full : STD_LOGIC;
      SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;
      SIGNAL ctrl_fifo_empty : STD_LOGIC;
      SIGNAL pkt_type_rdy : STD_LOGIC;
                SIGNAL pkt_type_rdy_ack_p : STD_LOGIC;
                SIGNAL pkt_type_rdy_ack : STD_LOGIC;
          SIGNAL pkt_type : STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL cnt : INTEGER;
          SIGNAL                out_data_i                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                out_ctrl_i                      :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                out_wr_i                        :               STD_LOGIC       ;
---------------------------------------------------
        BEGIN
        ------PORT MAP open_header
        open_header_Inst : open_header
        GENERIC MAP (DATA_WIDTH  => 64,
                        CTRL_WIDTH => 8)
        PORT MAP(
                        in_data                         =>      in_data,
                        in_ctrl                         =>      in_ctrl ,
                in_wr                           =>      in_wr,
 
                        pkt_type                        =>      pkt_type        ,
                        pkt_type_rdy            =>      pkt_type_rdy,
    --- Misc
         pkt_type_rdy_ack =>pkt_type_rdy_ack_p,
                reset                           =>      reset,
                clk                             =>      clk
        );
 
        ------PORT MAP open_header
 
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst :  small_fifo
        GENERIC MAP(WIDTH  => 72,
                        MAX_DEPTH_BITS  => 5)
        PORT MAP(
 
 
      din =>(in_fifo_in),
      wr_en =>in_wr,
 
      rd_en => in_fifo_rd_en,
 
      dout =>in_fifo_dout,
      full =>in_fifo_full,
      nearly_full =>in_fifo_nearly_full,
      empty => in_fifo_empty,
 
 
     reset => reset ,
     clk  => clk
 
        );
 
 
-------PORT MAP SMALL FIFO
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst_ctrl :  small_fifo
        GENERIC MAP(WIDTH  => 8,
                        MAX_DEPTH_BITS  => 5)
        PORT MAP(
 
 
      din =>pkt_type,
      wr_en =>pkt_type_rdy,
 
      rd_en => ctrl_fifo_rd,
 
      dout =>ctrl_fifo_dout,
      full =>ctrl_fifo_full,
      nearly_full =>ctrl_fifo_nearly_full,
      empty => ctrl_fifo_empty,
 
 
     reset => reset ,
     clk  => clk
 
        );
 
 
-----------------------
      in_fifo_in        <=      in_data & in_ctrl ;
                fifo_data       <=         in_fifo_dout(71 DOWNTO 8)    ;
                fifo_ctrl       <=      in_fifo_dout(7 DOWNTO 0) ;
                in_fifo_rd_en <=  in_fifo_go and out_rdy and (not in_fifo_empty);
 
 
 
                 in_rdy         <=      (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full)       ;
 
 
 
        dest <=  ctrl_fifo_dout(7 DOWNTO 0);
 
PROCESS(clk,reset)
BEGIN
        IF (reset ='1') THEN
                state <=IDLE;
                ELSIF clk'EVENT AND clk ='1' THEN
                state<=state_next;
                in_fifo_rd_en_p <= in_fifo_rd_en;
        END IF;
END PROCESS;
 
PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)
        BEGIN
                                                                        state_next                         <= state;
                                                                        out_data_i                              <=      fifo_data;
                                                                        out_ctrl_i                              <=      fifo_ctrl;
                                                                        out_wr_i                                   <=   in_fifo_rd_en_p ;
                                                                        ctrl_fifo_rd                    <=      '0'      ;
                                                                        in_fifo_go                              <=      '0'      ;
                                                                        pkt_type_rdy_ack_p      <= '0';
 
                CASE state IS
                        WHEN IDLE =>-- wait till the ctrl queue is not empty classification done
                           IF(ctrl_fifo_empty = '0') THEN
                                                                   ctrl_fifo_rd                 <=      '1'     ;
                                                                   in_fifo_go                           <=      '1'     ;
                                                                        pkt_type_rdy_ack_p      <= '1';
                                                                   state_next                           <=  IN_MODULE_HDRS;
                        END IF;
                        WHEN IN_MODULE_HDRS =>
                                                                                in_fifo_go                                 <=   '1'     ;
                                IF ( in_fifo_rd_en_p = '1' ) THEN
--                                                                      out_data_i(55 downto 48)<=       
--                                                                      out_wr_i                                   <=   '1' ;
 
                                                                        state_next                 <= IN_PACKET;
                                        END IF;
 
                        WHEN SKIP_HDRS =>
 
                                IF (  fifo_ctrl = X"00" ) THEN
                                                                 state_next                 <= IN_PACKET;
                            ELSE
                                                         in_fifo_go                             <=      '1'     ;
 
                                        END IF;
 
                        WHEN IN_PACKET          =>
--                                                                       out_wr_i                                   <=  '1' ; 
                                                                        in_fifo_go                                  <=  '1'     ;
 
                                IF (  fifo_ctrl /= X"00") THEN
--                                                              IF  out_rdy='1' THEN
                                                                   in_fifo_go                              <=   '0'      ;
--                                                                      out_wr_i                                    <=  '1' ;   
                                                                        state_next                 <= DUMP_1;
                                                                END IF;
--                              ELSIF out_rdy='1' AND in_fifo_empty ='0'  THEN 
 
--                              END IF;
                                WHEN DUMP_1             => state_next                 <= DUMP_2;
                                WHEN DUMP_2             => state_next                 <= DUMP_3;
                                WHEN DUMP_3             => state_next                 <= DUMP_4;
                                WHEN DUMP_4             => state_next                 <= DUMP_5;
                                WHEN DUMP_5             => state_next                 <= IDLE;
                                WHEN OTHERS=> state_next                          <= IDLE;
 
                END CASE;
        END PROCESS;
---------------Register output
                PROCESS(clk,reset)
                BEGIN
 
                        IF clk'EVENT AND clk ='1' THEN
                                                                        out_data                                <=      out_data_i;
                                                                        out_ctrl                                <=      out_ctrl_i;
                                                                        out_wr                                  <=      out_wr_i;
 
                        END IF;
                END PROCESS;
END behavior;
 

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Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [Classfier/] [classifier.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2
3			`LIBRARY IEEE;`
4			`USE IEEE.STD_LOGIC_1164.ALL;`
5			`use IEEE.std_logic_arith.all;`
6			`-------------------------------`
7			`ENTITY classifier IS`
8			`GENERIC(DATA_WIDTH :INTEGER := 64;`
9			`CTRL_WIDTH :INTEGER := 8);`
10			`PORT(`
11			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
12			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
13			`SIGNAL in_wr : IN STD_LOGIC ;`
14			`SIGNAL in_rdy : OUT STD_LOGIC ;`
15
16			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
17			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
18			`SIGNAL out_wr : OUT STD_LOGIC ;`
19			`SIGNAL out_rdy : IN STD_LOGIC ;`
20
21			`--- Misc`
22			`SIGNAL dest : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
23			`SIGNAL reset : IN STD_LOGIC ;`
24			`SIGNAL clk : IN STD_LOGIC`
25			`);`
26			`END ENTITY;`
27
28			`------------------------------------------------------`
29			`ARCHITECTURE behavior OF classifier IS`
30			`-------COMPONENET SMALL FIFO`
31			`COMPONENT small_fifo IS`
32			`GENERIC(WIDTH :INTEGER := 72;`
33			`MAX_DEPTH_BITS :INTEGER := 3);`
34			`PORT(`
35
36
37			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din, // Data in`
38			`SIGNAL wr_en : IN STD_LOGIC;--input wr_en, // Write enable`
39
40			`SIGNAL rd_en : IN STD_LOGIC;--input rd_en, // Read the next word`
41
42			`SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out`
43			`SIGNAL full : OUT STD_LOGIC;--output full,`
44			`SIGNAL nearly_full : OUT STD_LOGIC;--output nearly_full,`
45			`SIGNAL empty : OUT STD_LOGIC;--output empty,`
46
47
48			`SIGNAL reset :IN STD_LOGIC;`
49			`SIGNAL clk :IN STD_LOGIC`
50
51			`);`
52			`END COMPONENT;`
53			`-------COMPONENET SMALL FIFO`
54			`------COMPONENT open_header`
55			`COMPONENT open_header IS`
56			`GENERIC(DATA_WIDTH :INTEGER := 64;`
57			`CTRL_WIDTH :INTEGER := 8);`
58			`PORT(`
59			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
60			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
61			`SIGNAL in_wr : IN STD_LOGIC ;`
62
63			`SIGNAL pkt_type : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
64			`SIGNAL pkt_type_rdy : OUT STD_LOGIC ;`
65			`SIGNAL pkt_type_rdy_ack : IN STD_LOGIC ;`
66			`--- Misc`
67
68			`SIGNAL reset : IN STD_LOGIC ;`
69			`SIGNAL clk : IN STD_LOGIC`
70			`);`
71			`END COMPONENT;`
72			`------COMPONENT open_header`
73			`------------ one hot encoding state definition`
74
75			`TYPE state_type IS (IDLE, IN_MODULE_HDRS,SKIP_HDRS, IN_PACKET, DUMP_1 ,DUMP_2 ,DUMP_3, DUMP_4, DUMP_5);`
76			`ATTRIBUTE enum_encoding: STRING;`
77			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
78
79			`SIGNAL state, state_NEXT : state_type;`
80
81			`------------end state machine definition`
82
83			`----------------------FIFO`
84			`SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);`
85			`SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);`
86			`SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
87			`SIGNAL in_fifo_rd_en : STD_LOGIC;`
88			`SIGNAL in_fifo_rd_en_p : STD_LOGIC;`
89			`SIGNAL in_fifo_go : STD_LOGIC;`
90			`SIGNAL in_fifo_go_i : STD_LOGIC;`
91			`SIGNAL in_fifo_dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
92			`SIGNAL in_fifo_full : STD_LOGIC;`
93			`SIGNAL in_fifo_nearly_full : STD_LOGIC;`
94			`SIGNAL in_fifo_empty : STD_LOGIC;`
95			`------------------------------`
96			`SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(7 DOWNTO 0);`
97			`SIGNAL ctrl_fifo_rd : STD_LOGIC;`
98			`SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);`
99			`SIGNAL ctrl_fifo_full : STD_LOGIC;`
100			`SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;`
101			`SIGNAL ctrl_fifo_empty : STD_LOGIC;`
102			`SIGNAL pkt_type_rdy : STD_LOGIC;`
103			`SIGNAL pkt_type_rdy_ack_p : STD_LOGIC;`
104			`SIGNAL pkt_type_rdy_ack : STD_LOGIC;`
105			`SIGNAL pkt_type : STD_LOGIC_VECTOR(7 DOWNTO 0);`
106			`SIGNAL cnt : INTEGER;`
107			`SIGNAL out_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
108			`SIGNAL out_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
109			`SIGNAL out_wr_i : STD_LOGIC ;`
110			`---------------------------------------------------`
111			`BEGIN`
112			`------PORT MAP open_header`
113			`open_header_Inst : open_header`
114			`GENERIC MAP (DATA_WIDTH => 64,`
115			`CTRL_WIDTH => 8)`
116			`PORT MAP(`
117			`in_data => in_data,`
118			`in_ctrl => in_ctrl ,`
119			`in_wr => in_wr,`
120
121			`pkt_type => pkt_type ,`
122			`pkt_type_rdy => pkt_type_rdy,`
123			`--- Misc`
124			`pkt_type_rdy_ack =>pkt_type_rdy_ack_p,`
125			`reset => reset,`
126			`clk => clk`
127			`);`
128
129			`------PORT MAP open_header`
130
131			`-------PORT MAP SMALL FIFO DATA`
132			`small_fifo_Inst : small_fifo`
133			`GENERIC MAP(WIDTH => 72,`
134			`MAX_DEPTH_BITS => 5)`
135			`PORT MAP(`
136
137
138			`din =>(in_fifo_in),`
139			`wr_en =>in_wr,`
140
141			`rd_en => in_fifo_rd_en,`
142
143			`dout =>in_fifo_dout,`
144			`full =>in_fifo_full,`
145			`nearly_full =>in_fifo_nearly_full,`
146			`empty => in_fifo_empty,`
147
148
149			`reset => reset ,`
150			`clk => clk`
151
152			`);`
153
154
155			`-------PORT MAP SMALL FIFO`
156			`-------PORT MAP SMALL FIFO DATA`
157			`small_fifo_Inst_ctrl : small_fifo`
158			`GENERIC MAP(WIDTH => 8,`
159			`MAX_DEPTH_BITS => 5)`
160			`PORT MAP(`
161
162
163			`din =>pkt_type,`
164			`wr_en =>pkt_type_rdy,`
165
166			`rd_en => ctrl_fifo_rd,`
167
168			`dout =>ctrl_fifo_dout,`
169			`full =>ctrl_fifo_full,`
170			`nearly_full =>ctrl_fifo_nearly_full,`
171			`empty => ctrl_fifo_empty,`
172
173
174			`reset => reset ,`
175			`clk => clk`
176
177			`);`
178
179
180			`-----------------------`
181			`in_fifo_in <= in_data & in_ctrl ;`
182			`fifo_data <= in_fifo_dout(71 DOWNTO 8) ;`
183			`fifo_ctrl <= in_fifo_dout(7 DOWNTO 0) ;`
184			`in_fifo_rd_en <= in_fifo_go and out_rdy and (not in_fifo_empty);`
185
186
187
188			`in_rdy <= (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full) ;`
189
190
191
192			`dest <= ctrl_fifo_dout(7 DOWNTO 0);`
193
194			`PROCESS(clk,reset)`
195			`BEGIN`
196			`IF (reset ='1') THEN`
197			`state <=IDLE;`
198			`ELSIF clk'EVENT AND clk ='1' THEN`
199			`state<=state_next;`
200			`in_fifo_rd_en_p <= in_fifo_rd_en;`
201			`END IF;`
202			`END PROCESS;`
203
204			`PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)`
205			`BEGIN`
206			`state_next <= state;`
207			`out_data_i <= fifo_data;`
208			`out_ctrl_i <= fifo_ctrl;`
209			`out_wr_i <= in_fifo_rd_en_p ;`
210			`ctrl_fifo_rd <= '0' ;`
211			`in_fifo_go <= '0' ;`
212			`pkt_type_rdy_ack_p <= '0';`
213
214			`CASE state IS`
215			`WHEN IDLE =>-- wait till the ctrl queue is not empty classification done`
216			`IF(ctrl_fifo_empty = '0') THEN`
217			`ctrl_fifo_rd <= '1' ;`
218			`in_fifo_go <= '1' ;`
219			`pkt_type_rdy_ack_p <= '1';`
220			`state_next <= IN_MODULE_HDRS;`
221			`END IF;`
222			`WHEN IN_MODULE_HDRS =>`
223			`in_fifo_go <= '1' ;`
224			`IF ( in_fifo_rd_en_p = '1' ) THEN`
225			`-- out_data_i(55 downto 48)<=`
226			`-- out_wr_i <= '1' ;`
227
228			`state_next <= IN_PACKET;`
229			`END IF;`
230
231			`WHEN SKIP_HDRS =>`
232
233			`IF ( fifo_ctrl = X"00" ) THEN`
234			`state_next <= IN_PACKET;`
235			`ELSE`
236			`in_fifo_go <= '1' ;`
237
238			`END IF;`
239
240			`WHEN IN_PACKET =>`
241			`-- out_wr_i <= '1' ;`
242			`in_fifo_go <= '1' ;`
243
244			`IF ( fifo_ctrl /= X"00") THEN`
245			`-- IF out_rdy='1' THEN`
246			`in_fifo_go <= '0' ;`
247			`-- out_wr_i <= '1' ;`
248			`state_next <= DUMP_1;`
249			`END IF;`
250			`-- ELSIF out_rdy='1' AND in_fifo_empty ='0' THEN`
251
252			`-- END IF;`
253			`WHEN DUMP_1 => state_next <= DUMP_2;`
254			`WHEN DUMP_2 => state_next <= DUMP_3;`
255			`WHEN DUMP_3 => state_next <= DUMP_4;`
256			`WHEN DUMP_4 => state_next <= DUMP_5;`
257			`WHEN DUMP_5 => state_next <= IDLE;`
258			`WHEN OTHERS=> state_next <= IDLE;`
259
260			`END CASE;`
261			`END PROCESS;`
262			`---------------Register output`
263			`PROCESS(clk,reset)`
264			`BEGIN`
265
266			`IF clk'EVENT AND clk ='1' THEN`
267			`out_data <= out_data_i;`
268			`out_ctrl <= out_ctrl_i;`
269			`out_wr <= out_wr_i;`
270
271			`END IF;`
272			`END PROCESS;`
273			`END behavior;`
274