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[/] [loadbalancer/] [trunk/] [Router/] [router.vhd] - Blame information for rev 2

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--------------------------------------------------------
 
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        USE WORK.CONFIG.ALL;
-------------------------------
 
        ENTITY  router  IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
         SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
         SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL in_wr :IN STD_LOGIC;
         SIGNAL in_rdy : OUT STD_LOGIC;
 
        ----------------
 
        -------------------
         SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
         SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr : OUT STD_LOGIC;
         SIGNAL out_rdy : IN STD_LOGIC;
 
         SIGNAL     en : IN STD_LOGIC;
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
 
        );
        END ENTITY router ;
 ------------------------------------------------------
        ARCHITECTURE behavior OF router  IS
        -------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
        GENERIC(WIDTH :INTEGER := 72;
                        MAX_DEPTH_BITS :INTEGER := 3);
        PORT(
 
 
     SIGNAL din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
     SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
 
     SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word 
 
     SIGNAL dout :OUT STD_LOGIC_VECTOR(71 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
     SIGNAL full : OUT STD_LOGIC;--output         full,
     SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
     SIGNAL empty : OUT STD_LOGIC;--output         empty,
 
 
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT;
 
------------ one hot encoding state definition
        TYPE state_type IS (IDLE , IN_MODULE_HDRS, READ_WORD1, IN_PACKET);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_next : state_type;
--------------------------------------------------------------
 
-------------------------------------------
     SIGNAL data_in :STD_LOGIC_VECTOR(71 DOWNTO 0);
          SIGNAL rd_en : STD_LOGIC;
     SIGNAL dout : STD_LOGIC_VECTOR(71 DOWNTO 0);
     SIGNAL fifo_data :STD_LOGIC_VECTOR(63 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
          SIGNAL fifo_ctrl :STD_LOGIC_VECTOR(7 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
     SIGNAL full : STD_LOGIC;--output         full,
     SIGNAL nearly_full : STD_LOGIC;--output         nearly_full,
     SIGNAL empty : STD_LOGIC;--output         empty,
        -----------------------------------------
         SIGNAL                 in_data_int                     :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
         SIGNAL                 in_ctrl_int             :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
         SIGNAL                 in_wr_int                       :                       STD_LOGIC       ;
         SIGNAL                 in_rdy_int                      :                       STD_LOGIC       ;
                 SIGNAL                 wr_en                   :                       STD_LOGIC       ;
        BEGIN
 
        -------PORT MAP SMALL FIFO
                small_fifo_Inst :  small_fifo
        GENERIC MAP(WIDTH  => 72,
                        MAX_DEPTH_BITS  => 3)
        PORT MAP(
 
 
      din =>(data_in),
      wr_en =>wr_en,
 
      rd_en => rd_en,
 
      dout =>dout,
      full =>full,
      nearly_full =>nearly_full,
      empty => empty,
 
 
     reset => reset ,
     clk  => clk
 
        );
 
-------PORT MAP SMALL FIFO
                wr_en <= en and in_wr;
                in_rdy <=  NOT nearly_full;
--              rd_en <= out_rdy AND (NOT empty) AND fifo_go;
                fifo_data <=dout(71 DOWNTO 8);
                fifo_ctrl <=DOUT(7 DOWNTO 0);
                data_in<=in_data & in_ctrl;
 
                PROCESS(reset,clk)
                BEGIN
                        IF (reset ='1') THEN
                                state <=IDLE;
                        ELSIF clk'EVENT AND clk ='1' THEN
                                state<=state_next;
                        END IF;
                END PROCESS;
                PROCESS(state, fifo_data, fifo_ctrl )
                        BEGIN
                            in_data_int <= fifo_data;
                                 in_ctrl_int <= fifo_ctrl;
                                 in_wr_int   <= '0';
                                 rd_en           <= '0';
                                state_next <= state;
                                CASE state IS
                                        WHEN IDLE =>
                                                   IF(empty = '0') THEN
                                                                                           rd_en                                        <= '1';
                                                                                           state_next                           <= IN_MODULE_HDRS;
                                                END IF;
                                        WHEN IN_MODULE_HDRS =>
                                                IF (out_rdy='1'  ) THEN
--                                                      IF (out_rdy='1'  ) THEN
                                                                        in_data_int(63 DOWNTO 48)<= DEFAULT_INT_PORT;
                                                                        in_wr_int   <= '1';
                                                                    rd_en               <= '1';
                                                                    state_next  <= READ_WORD1;
 
                                                END IF;
 
                                        WHEN READ_WORD1 =>
                                                                        in_data_int(63 DOWNTO 16)<= VC_MAC;
                                                        IF (out_rdy='1'  ) THEN
 
                                                                         in_wr_int   <= '1';
                                                                    rd_en               <= '1';
                                                                    state_next  <= IN_PACKET;
 
                                                END IF;
 
                                        WHEN IN_PACKET          =>
 
 
                                                IF ( fifo_ctrl /= X"00" ) THEN
                                                                        IF ( out_rdy ='1' ) THEN
                                                                        state_next               <= IDLE;
                                                                        in_wr_int                               <=      '1' ;
                                                                        END IF;
                                                ELSIF(empty = '0' AND out_rdy ='1')THEN
                                                                        rd_en                                   <=      '1'     ;
                                                                        in_wr_int                       <=      '1' ;
                                                END IF;
 
 
                                END CASE;
                        END PROCESS;
 PROCESS(clk,reset)
                BEGIN
 
                        IF clk'EVENT AND clk ='1' THEN
                                 out_data  <=   in_data_int ;
                                 out_ctrl  <=   in_ctrl_int ;
                                 out_wr   <=    in_wr_int ;
 
                        END IF;
                END PROCESS;
 
END behavior;
 

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2
3			`LIBRARY IEEE;`
4			`USE IEEE.STD_LOGIC_1164.ALL;`
5			`USE WORK.CONFIG.ALL;`
6			`-------------------------------`
7
8			`ENTITY router IS`
9			`GENERIC(DATA_WIDTH :INTEGER := 64;`
10			`CTRL_WIDTH :INTEGER := 8);`
11			`PORT(`
12
13			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
14			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
15			`SIGNAL in_wr :IN STD_LOGIC;`
16			`SIGNAL in_rdy : OUT STD_LOGIC;`
17
18			`----------------`
19
20			`-------------------`
21			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
22			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
23			`SIGNAL out_wr : OUT STD_LOGIC;`
24			`SIGNAL out_rdy : IN STD_LOGIC;`
25
26			`SIGNAL en : IN STD_LOGIC;`
27			`SIGNAL reset :IN STD_LOGIC;`
28			`SIGNAL clk :IN STD_LOGIC`
29
30			`);`
31			`END ENTITY router ;`
32			`------------------------------------------------------`
33			`ARCHITECTURE behavior OF router IS`
34			`-------COMPONENET SMALL FIFO`
35			`COMPONENT small_fifo IS`
36			`GENERIC(WIDTH :INTEGER := 72;`
37			`MAX_DEPTH_BITS :INTEGER := 3);`
38			`PORT(`
39
40
41			`SIGNAL din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);--input [WIDTH-1:0] din, // Data in`
42			`SIGNAL wr_en : IN STD_LOGIC;--input wr_en, // Write enable`
43
44			`SIGNAL rd_en : IN STD_LOGIC;--input rd_en, // Read the next word`
45
46			`SIGNAL dout :OUT STD_LOGIC_VECTOR(71 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out`
47			`SIGNAL full : OUT STD_LOGIC;--output full,`
48			`SIGNAL nearly_full : OUT STD_LOGIC;--output nearly_full,`
49			`SIGNAL empty : OUT STD_LOGIC;--output empty,`
50
51
52			`SIGNAL reset :IN STD_LOGIC;`
53			`SIGNAL clk :IN STD_LOGIC`
54
55			`);`
56			`END COMPONENT;`
57
58			`------------ one hot encoding state definition`
59			`TYPE state_type IS (IDLE , IN_MODULE_HDRS, READ_WORD1, IN_PACKET);`
60			`ATTRIBUTE enum_encoding: STRING;`
61			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
62
63			`SIGNAL state, state_next : state_type;`
64			`--------------------------------------------------------------`
65
66			`-------------------------------------------`
67			`SIGNAL data_in :STD_LOGIC_VECTOR(71 DOWNTO 0);`
68			`SIGNAL rd_en : STD_LOGIC;`
69			`SIGNAL dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
70			`SIGNAL fifo_data :STD_LOGIC_VECTOR(63 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out`
71			`SIGNAL fifo_ctrl :STD_LOGIC_VECTOR(7 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out`
72			`SIGNAL full : STD_LOGIC;--output full,`
73			`SIGNAL nearly_full : STD_LOGIC;--output nearly_full,`
74			`SIGNAL empty : STD_LOGIC;--output empty,`
75			`-----------------------------------------`
76			`SIGNAL in_data_int : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
77			`SIGNAL in_ctrl_int : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
78			`SIGNAL in_wr_int : STD_LOGIC ;`
79			`SIGNAL in_rdy_int : STD_LOGIC ;`
80			`SIGNAL wr_en : STD_LOGIC ;`
81			`BEGIN`
82
83			`-------PORT MAP SMALL FIFO`
84			`small_fifo_Inst : small_fifo`
85			`GENERIC MAP(WIDTH => 72,`
86			`MAX_DEPTH_BITS => 3)`
87			`PORT MAP(`
88
89
90			`din =>(data_in),`
91			`wr_en =>wr_en,`
92
93			`rd_en => rd_en,`
94
95			`dout =>dout,`
96			`full =>full,`
97			`nearly_full =>nearly_full,`
98			`empty => empty,`
99
100
101			`reset => reset ,`
102			`clk => clk`
103
104			`);`
105
106			`-------PORT MAP SMALL FIFO`
107			`wr_en <= en and in_wr;`
108			`in_rdy <= NOT nearly_full;`
109			`-- rd_en <= out_rdy AND (NOT empty) AND fifo_go;`
110			`fifo_data <=dout(71 DOWNTO 8);`
111			`fifo_ctrl <=DOUT(7 DOWNTO 0);`
112			`data_in<=in_data & in_ctrl;`
113
114			`PROCESS(reset,clk)`
115			`BEGIN`
116			`IF (reset ='1') THEN`
117			`state <=IDLE;`
118			`ELSIF clk'EVENT AND clk ='1' THEN`
119			`state<=state_next;`
120			`END IF;`
121			`END PROCESS;`
122			`PROCESS(state, fifo_data, fifo_ctrl )`
123			`BEGIN`
124			`in_data_int <= fifo_data;`
125			`in_ctrl_int <= fifo_ctrl;`
126			`in_wr_int <= '0';`
127			`rd_en <= '0';`
128			`state_next <= state;`
129			`CASE state IS`
130			`WHEN IDLE =>`
131			`IF(empty = '0') THEN`
132			`rd_en <= '1';`
133			`state_next <= IN_MODULE_HDRS;`
134			`END IF;`
135			`WHEN IN_MODULE_HDRS =>`
136			`IF (out_rdy='1' ) THEN`
137			`-- IF (out_rdy='1' ) THEN`
138			`in_data_int(63 DOWNTO 48)<= DEFAULT_INT_PORT;`
139			`in_wr_int <= '1';`
140			`rd_en <= '1';`
141			`state_next <= READ_WORD1;`
142
143			`END IF;`
144
145			`WHEN READ_WORD1 =>`
146			`in_data_int(63 DOWNTO 16)<= VC_MAC;`
147			`IF (out_rdy='1' ) THEN`
148
149			`in_wr_int <= '1';`
150			`rd_en <= '1';`
151			`state_next <= IN_PACKET;`
152
153			`END IF;`
154
155			`WHEN IN_PACKET =>`
156
157
158			`IF ( fifo_ctrl /= X"00" ) THEN`
159			`IF ( out_rdy ='1' ) THEN`
160			`state_next <= IDLE;`
161			`in_wr_int <= '1' ;`
162			`END IF;`
163			`ELSIF(empty = '0' AND out_rdy ='1')THEN`
164			`rd_en <= '1' ;`
165			`in_wr_int <= '1' ;`
166			`END IF;`
167
168
169			`END CASE;`
170			`END PROCESS;`
171			`PROCESS(clk,reset)`
172			`BEGIN`
173
174			`IF clk'EVENT AND clk ='1' THEN`
175			`out_data <= in_data_int ;`
176			`out_ctrl <= in_ctrl_int ;`
177			`out_wr <= in_wr_int ;`
178
179			`END IF;`
180			`END PROCESS;`
181
182			`END behavior;`
183

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[/] [loadbalancer/] [trunk/] [Router/] [router.vhd] - Blame information for rev 2