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[/] [loadbalancer/] [trunk/] [TABLE/] [hello_pkt.vhd.bak] - Blame information for rev 2

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---this file could be used to build ARP RESPONSE
 
--------------------------------------------------------
 
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use ieee.numeric_std.all;
        use IEEE.STD_LOGIC_ARITH.ALL;
        use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
        USE WORK.CONFIG.ALL;
-------------------------------
 
        ENTITY  hello_pkt IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
        SIGNAL tx_in_data : IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL tx_in_ctrl : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL tx_in_wr :  IN STD_LOGIC;
        SIGNAL rx_in_data : IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL rx_in_ctrl : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL rx_in_wr :  IN STD_LOGIC;
 
        SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr :  OUT STD_LOGIC;
--      SIGNAL out_cnt : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
--      SIGNAL cnt_enable :OUT STD_LOGIC;
    SIGNAL out_rdy :IN STD_LOGIC;
        SIGNAL in_rdy :OUT STD_LOGIC;
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
        );
        END ENTITY hello_pkt;
 ------------------------------------------------------
        ARCHITECTURE behavior OF hello_pkt IS
        ------------------------
        COMPONENT Aging_Timer is
           generic(
                  N: integer := 32;  -- 32 bits couter
                  M: integer := TIMER_PERIOD  -- 125000  = 1 miliscond
           );
           port(
                  clk, reset: in std_logic;
                  timeout: out std_logic;
                  timer_aging_bit: out std_logic;
                  count_out: out std_logic_vector(31 downto 0)--N-1
           );
        end COMPONENT Aging_Timer;
 
 
----------------------------------------------------------------------------
------------ one hot encoding state definition
        TYPE state_type is (IDLE,TIMEOUT, WRITE_HEADER);
--      ATTRIBUTE enum_encoding: STRING;
--      ATTRIBUTE enum_encoding OF state_type: TYPE IS "onehot";
        SIGNAL state, state_next: state_type;
        TYPE state_ch_type is (IDLE,IN_PACKET);
        SIGNAL state_ch, state_ch_next: state_ch_type;
------------end state machine definition
    TYPE counters_type IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
    SIGNAL tx_array : counters_type;
    SIGNAL rx_array : counters_type;
        TYPE status_type IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
        CONSTANT status : status_type:=(X"00", X"00", X"00", X"00");
--      SIGNAL FCS : STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL MSGSeqnum : STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL MSGSeqnum_up : STD_LOGIC;
---------------internal signals
    SIGNAL              out_data_p                      :   STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
        SIGNAL          out_ctrl_p                      :   STD_LOGIC_VECTOR(CTRL_WIDTH-1 DOWNTO 0);
    SIGNAL              out_wr_p                        :       STD_LOGIC;
--      SIGNAL          source_port                     :       STD_LOGIC_VECTOR(1 DOWNTO 0);--just four ports
--      SIGNAL          dest_port                       :       STD_LOGIC_VECTOR(15 DOWNTO 0);--just four ports
        SIGNAL          word_cnt                        :       INTEGER;
        SIGNAL          word_cnt_up                     :       STD_LOGIC;
        SIGNAL          word_cnt_rst            :       STD_LOGIC;
        SIGNAL          time_out                        :       STD_LOGIC;
        SIGNAL          clear_to_send           :       STD_LOGIC;
                ------IP HEADER CHECK SUM CALCULATIONS
 
        CONSTANT TEMP  : INTEGER :=17664 +      0 + 0 + 16401 + CONV_INTEGER(DIST_UNICAST_LB(31 DOWNTO 16)) +
                         CONV_INTEGER(DIST_UNICAST_LB(15 DOWNTO 0)) + CONV_INTEGER(DIST_MULTICAST_ALL(31 DOWNTO 16))+
                         CONV_INTEGER(DIST_MULTICAST_ALL(15 DOWNTO 0));
        CONSTANT TEMP1 : STD_LOGIC_VECTOR(19 DOWNTO 0 ):= std_logic_vector(to_unsigned(TEMP, 20));
        CONSTANT TEMP2 : STD_LOGIC_VECTOR(3 DOWNTO 0 ) := TEMP1(19 DOWNTO 16);
        CONSTANT TEMP3 :  STD_LOGIC_VECTOR(15 DOWNTO 0 ) := TEMP1(15 DOWNTO 0)+ TEMP2;
        CONSTANT FCS :  STD_LOGIC_VECTOR(15 DOWNTO 0 ) := NOT TEMP3;
 
--              +       X"0000" +       X"0000" +       X"4011"  +      DIST_UNICAST_LB(31 DOWNTO 16)+
--                              DIST_UNICAST_LB(15 DOWNTO 0) +  DIST_MULTICAST_ALL(31 DOWNTO 16)
--                              + DIST_MULTICAST_ALL(15 DOWNTO 0);
        -------------------------------------
-------------------------------------------
        BEGIN
 
 
 
---------------------------------------------------------------------------------
 
 
---------------------------------------------------------------------------------
 
 
        -------PORT MAP SMALL FIFO DATA
                ------------------------
                        Aging_Timer_Inst :  Aging_Timer
                           GENERIC MAP (
                                                                N => 32 ,
                                                                M =>TIMER_PERIOD-- 125000  = 1 miliscond
                                                        )
                                   port MAP(
                                          clk => clk,
                                          reset => reset,
                                          timeout =>open ,
                                          timer_aging_bit =>open,
                                          count_out => open
                                   );
 
                                        time_out<= '0';
                process (clk)
                        variable   cnt             : STD_LOGIC_VECTOR(15 DOWNTO 0);
                begin
                        if (rising_edge(clk)) then
 
                                if reset = '1' then
                                        -- Reset the counter to 0
                                        cnt := (OTHERS=>'0');
 
                                elsif MSGSeqnum_up = '1' then
                                        -- Increment the counter if counting is enabled
                                        cnt := cnt + '1';
 
                                end if;
                        end if;
 
                        -- Output the current count
                                MSGSeqnum <=  cnt;
        --              cnt_enable <= word_cnt_up;
        end process;
 
--------------------------------------------------
 
                PROCESS(reset,clk)
                BEGIN
                        IF (reset ='1') THEN
                                        state                                                           <=        IDLE;
                        ELSIF clk'EVENT AND clk ='1' THEN
                                        state                                                           <=        state_next;
                        END IF;
                END PROCESS;
                PROCESS(state, clear_to_send, time_out, word_cnt, out_rdy)
                BEGIN
                                        state_next                                                      <=        state;
                                        word_cnt_up                                                     <=        '0';
                                        word_cnt_rst                                            <=        '0';
                                        in_rdy                                                          <=        '1';
                                        MSGSeqnum_up                                            <=        '0';
                        CASE state IS
                        WHEN IDLE =>
                                in_rdy                                                                  <=        '1';
                                IF time_out ='1' THEN
                                        word_cnt_rst                                            <=        '1';
                                        state_next                                      <=        TIMEOUT;
                                END IF;
                        WHEN TIMEOUT =>
                                        in_rdy                                                          <=        '0';
--                               IF clear_to_send ='1' THEN
                                        word_cnt_rst                                            <=        '1';
                                        MSGSeqnum_up                                            <=        '1';
                                        state_next                                      <=        WRITE_HEADER;
--                                END IF;
                        WHEN WRITE_HEADER =>
                                        in_rdy                                                          <=        '0';
                                        IF word_cnt > 21   THEN
                                        state_next                                      <=        IDLE;
                                        ELSIF ( word_cnt <= 21 ) AND out_rdy = '1' THEN
                                        word_cnt_up                                                     <=        '1';
 
                                        state_next                                      <=        WRITE_HEADER;
                                END IF;
                        WHEN OTHERS =>
                                        state_next                                                      <=        IDLE;
                        END CASE;
                END PROCESS;
                --------------------------------------------------------------------
                process (clk)
                variable   cnt             : INTEGER;
        begin
                if (rising_edge(clk)) then
 
                        if word_cnt_rst = '1' then
                                -- Reset the counter to 0
                                cnt := 0;
 
                        elsif word_cnt_up = '1' then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + 1;
 
                        end if;
                end if;
 
                -- Output the current count
                word_cnt <= cnt;
--              cnt_enable <= word_cnt_up;
        end process;
--      out_cnt <= std_logic_vector(to_unsigned(word_cnt, 8));
                        -------------------OUTPUT ASSIGNMENT
 
 
                with word_cnt select
                out_data_p <= DEFAULT_INT_PORT & X"0014" & X"0040" &X"00A0" WHEN 1,
                                   X"FFFFFFFFFFFF" & mac_array(0)(47 DOWNTO 32) when 2,
                                   mac_array(0)(31 DOWNTO 0) & X"0800" & X"4500"when 3,
                                   X"0000000000004011" when 4,
                                   FCS & DIST_UNICAST_LB & DIST_MULTICAST_ALL(31 DOWNTO 16) WHEN 5,
                                   DIST_MULTICAST_ALL(15 DOWNTO 0) & DIST_PORT & DIST_PORT&X"0000" WHEN 6,
                                   X"0000"& DIST_VER & DIST_MSGTYPE & NODE_ID&X"00"& NODE_TYPE(23 downto 16)WHEN 7,
                                   NODE_TYPE(15 DOWNTO 0) & MSGSeqnum & X"00000000" WHEN 8,
 
                                   X"00" & status(0) & mac_array(0) WHEN  9,--port 0
                                   vlan_array(0) & ip_array(0) & subnet_array(0)(31 DOWNTO 16) WHEN  10,--port 0
                                   subnet_array(0)(15 DOWNTO 0) & tx_array(0) & rx_array(0)(31 DOWNTO 16) WHEN  11,
 
                                   rx_array(0)(15 DOWNTO 0) & X"01" & status(1) & mac_array(1)(47 DOWNTO 16)  WHEN  12,
                                   mac_array(1)(15 DOWNTO 0)& vlan_array(1) & ip_array(1) WHEN  13,
                                   subnet_array(1)& tx_array(1) WHEN  14,
 
                                   rx_array(1) &  X"02" & status(2) & mac_array(2)(47 DOWNTO 32) WHEN  15,--port 0
                                   mac_array(2)(31 DOWNTO 0)& vlan_array(2) & ip_array(2)(31 DOWNTO 16) WHEN  16,
                                   ip_array(2)(15 DOWNTO 0)&subnet_array(2)& tx_array(2)(31 DOWNTO 16) WHEN  17,
 
                                   tx_array(2)(15 DOWNTO 0)& rx_array(2) &  X"03" & status(3)WHEN  18,
                                   mac_array(3) &  vlan_array(3)&X"0" WHEN  19,
                                   ip_array(3) & subnet_array(3) WHEN  20,
                                   tx_array(3) &  rx_array(3) WHEN  21,
                                  ( OTHERS=>'0') when others;
 
 
                                out_wr_p        <=     word_cnt_up when word_cnt >= 1  AND word_cnt <= 21 else
                                                                 '0';
                                 out_ctrl_p <= X"FF" when word_cnt = 1 else
                                                                X"01"  when word_cnt = 21 else
                                                           X"00" ;
 
                        PROCESS(reset,clk)
                                BEGIN
 
                                        IF clk'EVENT AND clk ='1' THEN
                                                        out_data                        <=                out_data_p;
                                                        out_ctrl                        <=                out_ctrl_p;
                                                        out_wr                          <=                out_wr_p;
--                                                      out_wr_p                        <=                word_cnt_up;
                                        END IF;
                                END PROCESS;
 
 
------------------------------counters array-----------------------------------------
                process (clk)
                variable   cnt             : STD_LOGIC_VECTOR(31 DOWNTO 0);
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := (others=>'0');
 
                        elsif tx_in_wr='1' AND tx_in_ctrl = X"FF" AND tx_in_data(63 DOWNTO 48) =X"0001" then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + '1';
 
                        end if;
                end if;
 
                -- Output the current count
                tx_array(0) <= cnt;
        end process;
                process (clk)
                variable   cnt             : STD_LOGIC_VECTOR(31 DOWNTO 0);
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := (others=>'0');
 
                        elsif tx_in_wr='1' AND tx_in_ctrl = X"FF" AND tx_in_data(63 DOWNTO 48) =X"0004" then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + '1';
 
                        end if;
                end if;
 
                -- Output the current count
                tx_array(1) <= cnt;
        end process;
                process (clk)
                variable   cnt             : STD_LOGIC_VECTOR(31 DOWNTO 0);
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := (others=>'0');
 
                        elsif tx_in_wr='1' AND tx_in_ctrl = X"FF" AND tx_in_data(63 DOWNTO 48) =X"0010" then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + '1';
 
                        end if;
                end if;
 
                -- Output the current count
                tx_array(2) <= cnt;
        end process;
                process (clk)
                variable   cnt             : STD_LOGIC_VECTOR(31 DOWNTO 0);
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := (others=>'0');
 
                        elsif tx_in_wr='1' AND tx_in_ctrl = X"FF" AND tx_in_data(63 DOWNTO 48) =X"0040" then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + '1';
 
                        end if;
                end if;
 
                -- Output the current count
                tx_array(3) <= cnt;
        end process;
 
                process (clk)
                variable   cnt             : STD_LOGIC_VECTOR(31 DOWNTO 0);
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := (others=>'0');
 
                        elsif rx_in_wr='1' AND rx_in_ctrl = X"FF" AND rx_in_data(31 DOWNTO 16) =X"0000" then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + '1';
 
                        end if;
                end if;
 
                -- Output the current count
                rx_array(0) <= cnt;
        end process;
                process (clk)
                variable   cnt             : STD_LOGIC_VECTOR(31 DOWNTO 0);
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := (others=>'0');
 
                        elsif rx_in_wr='1' AND rx_in_ctrl = X"FF" AND rx_in_data(31 DOWNTO 16) =X"0002" then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + '1';
 
                        end if;
                end if;
 
                -- Output the current count
                rx_array(1) <= cnt;
        end process;
                process (clk)
                variable   cnt             : STD_LOGIC_VECTOR(31 DOWNTO 0);
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := (others=>'0');
 
                        elsif rx_in_wr='1' AND rx_in_ctrl = X"FF" AND rx_in_data(31 DOWNTO 16) =X"0004" then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + '1';
 
                        end if;
                end if;
 
                -- Output the current count
                rx_array(2) <= cnt;
        end process;
                process (clk)
                variable   cnt             : STD_LOGIC_VECTOR(31 DOWNTO 0);
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := (others=>'0');
 
                        elsif rx_in_wr='1' AND rx_in_ctrl = X"FF" AND rx_in_data(31 DOWNTO 16) =X"0006" then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + '1';
 
                        end if;
                end if;
 
                -- Output the current count
                rx_array(3) <= cnt;
        end process;
------------------------------counters array-----------------------------------------
END behavior;
 

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Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [TABLE/] [hello_pkt.vhd.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`---this file could be used to build ARP RESPONSE`
2
3			`--------------------------------------------------------`
4
5			`LIBRARY IEEE;`
6			`USE IEEE.STD_LOGIC_1164.ALL;`
7			`use ieee.numeric_std.all;`
8			`use IEEE.STD_LOGIC_ARITH.ALL;`
9			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
10
11			`USE WORK.CONFIG.ALL;`
12			`-------------------------------`
13
14			`ENTITY hello_pkt IS`
15			`GENERIC(DATA_WIDTH :INTEGER := 64;`
16			`CTRL_WIDTH :INTEGER := 8);`
17			`PORT(`
18
19			`SIGNAL tx_in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
20			`SIGNAL tx_in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
21			`SIGNAL tx_in_wr : IN STD_LOGIC;`
22			`SIGNAL rx_in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
23			`SIGNAL rx_in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
24			`SIGNAL rx_in_wr : IN STD_LOGIC;`
25
26			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
27			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
28			`SIGNAL out_wr : OUT STD_LOGIC;`
29			`-- SIGNAL out_cnt : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
30			`-- SIGNAL cnt_enable :OUT STD_LOGIC;`
31			`SIGNAL out_rdy :IN STD_LOGIC;`
32			`SIGNAL in_rdy :OUT STD_LOGIC;`
33			`SIGNAL reset :IN STD_LOGIC;`
34			`SIGNAL clk :IN STD_LOGIC`
35			`);`
36			`END ENTITY hello_pkt;`
37			`------------------------------------------------------`
38			`ARCHITECTURE behavior OF hello_pkt IS`
39			`------------------------`
40			`COMPONENT Aging_Timer is`
41			`generic(`
42			`N: integer := 32; -- 32 bits couter`
43			`M: integer := TIMER_PERIOD -- 125000 = 1 miliscond`
44			`);`
45			`port(`
46			`clk, reset: in std_logic;`
47			`timeout: out std_logic;`
48			`timer_aging_bit: out std_logic;`
49			`count_out: out std_logic_vector(31 downto 0)--N-1`
50			`);`
51			`end COMPONENT Aging_Timer;`
52
53
54			`----------------------------------------------------------------------------`
55			`------------ one hot encoding state definition`
56			`TYPE state_type is (IDLE,TIMEOUT, WRITE_HEADER);`
57			`-- ATTRIBUTE enum_encoding: STRING;`
58			`-- ATTRIBUTE enum_encoding OF state_type: TYPE IS "onehot";`
59			`SIGNAL state, state_next: state_type;`
60			`TYPE state_ch_type is (IDLE,IN_PACKET);`
61			`SIGNAL state_ch, state_ch_next: state_ch_type;`
62			`------------end state machine definition`
63			`TYPE counters_type IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0);`
64			`SIGNAL tx_array : counters_type;`
65			`SIGNAL rx_array : counters_type;`
66			`TYPE status_type IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);`
67			`CONSTANT status : status_type:=(X"00", X"00", X"00", X"00");`
68			`-- SIGNAL FCS : STD_LOGIC_VECTOR(15 DOWNTO 0);`
69			`SIGNAL MSGSeqnum : STD_LOGIC_VECTOR(15 DOWNTO 0);`
70			`SIGNAL MSGSeqnum_up : STD_LOGIC;`
71			`---------------internal signals`
72			`SIGNAL out_data_p : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);`
73			`SIGNAL out_ctrl_p : STD_LOGIC_VECTOR(CTRL_WIDTH-1 DOWNTO 0);`
74			`SIGNAL out_wr_p : STD_LOGIC;`
75			`-- SIGNAL source_port : STD_LOGIC_VECTOR(1 DOWNTO 0);--just four ports`
76			`-- SIGNAL dest_port : STD_LOGIC_VECTOR(15 DOWNTO 0);--just four ports`
77			`SIGNAL word_cnt : INTEGER;`
78			`SIGNAL word_cnt_up : STD_LOGIC;`
79			`SIGNAL word_cnt_rst : STD_LOGIC;`
80			`SIGNAL time_out : STD_LOGIC;`
81			`SIGNAL clear_to_send : STD_LOGIC;`
82			`------IP HEADER CHECK SUM CALCULATIONS`
83
84			`CONSTANT TEMP : INTEGER :=17664 + 0 + 0 + 16401 + CONV_INTEGER(DIST_UNICAST_LB(31 DOWNTO 16)) +`
85			`CONV_INTEGER(DIST_UNICAST_LB(15 DOWNTO 0)) + CONV_INTEGER(DIST_MULTICAST_ALL(31 DOWNTO 16))+`
86			`CONV_INTEGER(DIST_MULTICAST_ALL(15 DOWNTO 0));`
87			`CONSTANT TEMP1 : STD_LOGIC_VECTOR(19 DOWNTO 0 ):= std_logic_vector(to_unsigned(TEMP, 20));`
88			`CONSTANT TEMP2 : STD_LOGIC_VECTOR(3 DOWNTO 0 ) := TEMP1(19 DOWNTO 16);`
89			`CONSTANT TEMP3 : STD_LOGIC_VECTOR(15 DOWNTO 0 ) := TEMP1(15 DOWNTO 0)+ TEMP2;`
90			`CONSTANT FCS : STD_LOGIC_VECTOR(15 DOWNTO 0 ) := NOT TEMP3;`
91
92			`-- + X"0000" + X"0000" + X"4011" + DIST_UNICAST_LB(31 DOWNTO 16)+`
93			`-- DIST_UNICAST_LB(15 DOWNTO 0) + DIST_MULTICAST_ALL(31 DOWNTO 16)`
94			`-- + DIST_MULTICAST_ALL(15 DOWNTO 0);`
95			`-------------------------------------`
96			`-------------------------------------------`
97			`BEGIN`
98
99
100
101			`---------------------------------------------------------------------------------`
102
103
104			`---------------------------------------------------------------------------------`
105
106
107			`-------PORT MAP SMALL FIFO DATA`
108			`------------------------`
109			`Aging_Timer_Inst : Aging_Timer`
110			`GENERIC MAP (`
111			`N => 32 ,`
112			`M =>TIMER_PERIOD-- 125000 = 1 miliscond`
113			`)`
114			`port MAP(`
115			`clk => clk,`
116			`reset => reset,`
117			`timeout =>open ,`
118			`timer_aging_bit =>open,`
119			`count_out => open`
120			`);`
121
122			`time_out<= '0';`
123			`process (clk)`
124			`variable cnt : STD_LOGIC_VECTOR(15 DOWNTO 0);`
125			`begin`
126			`if (rising_edge(clk)) then`
127
128			`if reset = '1' then`
129			`-- Reset the counter to 0`
130			`cnt := (OTHERS=>'0');`
131
132			`elsif MSGSeqnum_up = '1' then`
133			`-- Increment the counter if counting is enabled`
134			`cnt := cnt + '1';`
135
136			`end if;`
137			`end if;`
138
139			`-- Output the current count`
140			`MSGSeqnum <= cnt;`
141			`-- cnt_enable <= word_cnt_up;`
142			`end process;`
143
144			`--------------------------------------------------`
145
146			`PROCESS(reset,clk)`
147			`BEGIN`
148			`IF (reset ='1') THEN`
149			`state <= IDLE;`
150			`ELSIF clk'EVENT AND clk ='1' THEN`
151			`state <= state_next;`
152			`END IF;`
153			`END PROCESS;`
154			`PROCESS(state, clear_to_send, time_out, word_cnt, out_rdy)`
155			`BEGIN`
156			`state_next <= state;`
157			`word_cnt_up <= '0';`
158			`word_cnt_rst <= '0';`
159			`in_rdy <= '1';`
160			`MSGSeqnum_up <= '0';`
161			`CASE state IS`
162			`WHEN IDLE =>`
163			`in_rdy <= '1';`
164			`IF time_out ='1' THEN`
165			`word_cnt_rst <= '1';`
166			`state_next <= TIMEOUT;`
167			`END IF;`
168			`WHEN TIMEOUT =>`
169			`in_rdy <= '0';`
170			`-- IF clear_to_send ='1' THEN`
171			`word_cnt_rst <= '1';`
172			`MSGSeqnum_up <= '1';`
173			`state_next <= WRITE_HEADER;`
174			`-- END IF;`
175			`WHEN WRITE_HEADER =>`
176			`in_rdy <= '0';`
177			`IF word_cnt > 21 THEN`
178			`state_next <= IDLE;`
179			`ELSIF ( word_cnt <= 21 ) AND out_rdy = '1' THEN`
180			`word_cnt_up <= '1';`
181
182			`state_next <= WRITE_HEADER;`
183			`END IF;`
184			`WHEN OTHERS =>`
185			`state_next <= IDLE;`
186			`END CASE;`
187			`END PROCESS;`
188			`--------------------------------------------------------------------`
189			`process (clk)`
190			`variable cnt : INTEGER;`
191			`begin`
192			`if (rising_edge(clk)) then`
193
194			`if word_cnt_rst = '1' then`
195			`-- Reset the counter to 0`
196			`cnt := 0;`
197
198			`elsif word_cnt_up = '1' then`
199			`-- Increment the counter if counting is enabled`
200			`cnt := cnt + 1;`
201
202			`end if;`
203			`end if;`
204
205			`-- Output the current count`
206			`word_cnt <= cnt;`
207			`-- cnt_enable <= word_cnt_up;`
208			`end process;`
209			`-- out_cnt <= std_logic_vector(to_unsigned(word_cnt, 8));`
210			`-------------------OUTPUT ASSIGNMENT`
211
212
213			`with word_cnt select`
214			`out_data_p <= DEFAULT_INT_PORT & X"0014" & X"0040" &X"00A0" WHEN 1,`
215			`X"FFFFFFFFFFFF" & mac_array(0)(47 DOWNTO 32) when 2,`
216			`mac_array(0)(31 DOWNTO 0) & X"0800" & X"4500"when 3,`
217			`X"0000000000004011" when 4,`
218			`FCS & DIST_UNICAST_LB & DIST_MULTICAST_ALL(31 DOWNTO 16) WHEN 5,`
219			`DIST_MULTICAST_ALL(15 DOWNTO 0) & DIST_PORT & DIST_PORT&X"0000" WHEN 6,`
220			`X"0000"& DIST_VER & DIST_MSGTYPE & NODE_ID&X"00"& NODE_TYPE(23 downto 16)WHEN 7,`
221			`NODE_TYPE(15 DOWNTO 0) & MSGSeqnum & X"00000000" WHEN 8,`
222
223			`X"00" & status(0) & mac_array(0) WHEN 9,--port 0`
224			`vlan_array(0) & ip_array(0) & subnet_array(0)(31 DOWNTO 16) WHEN 10,--port 0`
225			`subnet_array(0)(15 DOWNTO 0) & tx_array(0) & rx_array(0)(31 DOWNTO 16) WHEN 11,`
226
227			`rx_array(0)(15 DOWNTO 0) & X"01" & status(1) & mac_array(1)(47 DOWNTO 16) WHEN 12,`
228			`mac_array(1)(15 DOWNTO 0)& vlan_array(1) & ip_array(1) WHEN 13,`
229			`subnet_array(1)& tx_array(1) WHEN 14,`
230
231			`rx_array(1) & X"02" & status(2) & mac_array(2)(47 DOWNTO 32) WHEN 15,--port 0`
232			`mac_array(2)(31 DOWNTO 0)& vlan_array(2) & ip_array(2)(31 DOWNTO 16) WHEN 16,`
233			`ip_array(2)(15 DOWNTO 0)&subnet_array(2)& tx_array(2)(31 DOWNTO 16) WHEN 17,`
234
235			`tx_array(2)(15 DOWNTO 0)& rx_array(2) & X"03" & status(3)WHEN 18,`
236			`mac_array(3) & vlan_array(3)&X"0" WHEN 19,`
237			`ip_array(3) & subnet_array(3) WHEN 20,`
238			`tx_array(3) & rx_array(3) WHEN 21,`
239			`( OTHERS=>'0') when others;`
240
241
242			`out_wr_p <= word_cnt_up when word_cnt >= 1 AND word_cnt <= 21 else`
243			`'0';`
244			`out_ctrl_p <= X"FF" when word_cnt = 1 else`
245			`X"01" when word_cnt = 21 else`
246			`X"00" ;`
247
248			`PROCESS(reset,clk)`
249			`BEGIN`
250
251			`IF clk'EVENT AND clk ='1' THEN`
252			`out_data <= out_data_p;`
253			`out_ctrl <= out_ctrl_p;`
254			`out_wr <= out_wr_p;`
255			`-- out_wr_p <= word_cnt_up;`
256			`END IF;`
257			`END PROCESS;`
258
259
260			`------------------------------counters array-----------------------------------------`
261			`process (clk)`
262			`variable cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);`
263			`begin`
264			`if (rising_edge(clk)) then`
265
266			`if reset = '1' then`
267			`-- Reset the counter to 0`
268			`cnt := (others=>'0');`
269
270			`elsif tx_in_wr='1' AND tx_in_ctrl = X"FF" AND tx_in_data(63 DOWNTO 48) =X"0001" then`
271			`-- Increment the counter if counting is enabled`
272			`cnt := cnt + '1';`
273
274			`end if;`
275			`end if;`
276
277			`-- Output the current count`
278			`tx_array(0) <= cnt;`
279			`end process;`
280			`process (clk)`
281			`variable cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);`
282			`begin`
283			`if (rising_edge(clk)) then`
284
285			`if reset = '1' then`
286			`-- Reset the counter to 0`
287			`cnt := (others=>'0');`
288
289			`elsif tx_in_wr='1' AND tx_in_ctrl = X"FF" AND tx_in_data(63 DOWNTO 48) =X"0004" then`
290			`-- Increment the counter if counting is enabled`
291			`cnt := cnt + '1';`
292
293			`end if;`
294			`end if;`
295
296			`-- Output the current count`
297			`tx_array(1) <= cnt;`
298			`end process;`
299			`process (clk)`
300			`variable cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);`
301			`begin`
302			`if (rising_edge(clk)) then`
303
304			`if reset = '1' then`
305			`-- Reset the counter to 0`
306			`cnt := (others=>'0');`
307
308			`elsif tx_in_wr='1' AND tx_in_ctrl = X"FF" AND tx_in_data(63 DOWNTO 48) =X"0010" then`
309			`-- Increment the counter if counting is enabled`
310			`cnt := cnt + '1';`
311
312			`end if;`
313			`end if;`
314
315			`-- Output the current count`
316			`tx_array(2) <= cnt;`
317			`end process;`
318			`process (clk)`
319			`variable cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);`
320			`begin`
321			`if (rising_edge(clk)) then`
322
323			`if reset = '1' then`
324			`-- Reset the counter to 0`
325			`cnt := (others=>'0');`
326
327			`elsif tx_in_wr='1' AND tx_in_ctrl = X"FF" AND tx_in_data(63 DOWNTO 48) =X"0040" then`
328			`-- Increment the counter if counting is enabled`
329			`cnt := cnt + '1';`
330
331			`end if;`
332			`end if;`
333
334			`-- Output the current count`
335			`tx_array(3) <= cnt;`
336			`end process;`
337
338			`process (clk)`
339			`variable cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);`
340			`begin`
341			`if (rising_edge(clk)) then`
342
343			`if reset = '1' then`
344			`-- Reset the counter to 0`
345			`cnt := (others=>'0');`
346
347			`elsif rx_in_wr='1' AND rx_in_ctrl = X"FF" AND rx_in_data(31 DOWNTO 16) =X"0000" then`
348			`-- Increment the counter if counting is enabled`
349			`cnt := cnt + '1';`
350
351			`end if;`
352			`end if;`
353
354			`-- Output the current count`
355			`rx_array(0) <= cnt;`
356			`end process;`
357			`process (clk)`
358			`variable cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);`
359			`begin`
360			`if (rising_edge(clk)) then`
361
362			`if reset = '1' then`
363			`-- Reset the counter to 0`
364			`cnt := (others=>'0');`
365
366			`elsif rx_in_wr='1' AND rx_in_ctrl = X"FF" AND rx_in_data(31 DOWNTO 16) =X"0002" then`
367			`-- Increment the counter if counting is enabled`
368			`cnt := cnt + '1';`
369
370			`end if;`
371			`end if;`
372
373			`-- Output the current count`
374			`rx_array(1) <= cnt;`
375			`end process;`
376			`process (clk)`
377			`variable cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);`
378			`begin`
379			`if (rising_edge(clk)) then`
380
381			`if reset = '1' then`
382			`-- Reset the counter to 0`
383			`cnt := (others=>'0');`
384
385			`elsif rx_in_wr='1' AND rx_in_ctrl = X"FF" AND rx_in_data(31 DOWNTO 16) =X"0004" then`
386			`-- Increment the counter if counting is enabled`
387			`cnt := cnt + '1';`
388
389			`end if;`
390			`end if;`
391
392			`-- Output the current count`
393			`rx_array(2) <= cnt;`
394			`end process;`
395			`process (clk)`
396			`variable cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);`
397			`begin`
398			`if (rising_edge(clk)) then`
399
400			`if reset = '1' then`
401			`-- Reset the counter to 0`
402			`cnt := (others=>'0');`
403
404			`elsif rx_in_wr='1' AND rx_in_ctrl = X"FF" AND rx_in_data(31 DOWNTO 16) =X"0006" then`
405			`-- Increment the counter if counting is enabled`
406			`cnt := cnt + '1';`
407
408			`end if;`
409			`end if;`
410
411			`-- Output the current count`
412			`rx_array(3) <= cnt;`
413			`end process;`
414			`------------------------------counters array-----------------------------------------`
415			`END behavior;`
416