URL https://opencores.org/ocsvn/loadbalancer/loadbalancer/trunk

Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [TABLE/] [manager.vhd.bak] - Blame information for rev 2

Details | Compare with Previous | View Log


--------------------------------------------------------
        library IEEE;
        use IEEE.STD_LOGIC_1164.ALL;
        use IEEE.STD_LOGIC_ARITH.ALL;
        use IEEE.STD_LOGIC_UNSIGNED.ALL;
        use ieee.numeric_std.all;
---------------------------------------------
 
        ENTITY  manager IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
                                SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                                SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                                SIGNAL in_wr :IN STD_LOGIC;
                                SIGNAL in_rdy : OUT STD_LOGIC;
                                SIGNAL in_rd: IN std_logic;
                                SIGNAL in_key           : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                                SIGNAL out_mac: OUT std_logic_VECTOR(47 downto 0);
                                SIGNAL out_port: OUT std_logic_VECTOR(7 downto 0);
                                SIGNAL out_rd_rdy: OUT std_logic        ;
                                SIGNAL out_rdy : IN STD_LOGIC;
                                SIGNAL en :IN STD_LOGIC;
                                SIGNAL reset :IN STD_LOGIC;
                                SIGNAL clk   :IN STD_LOGIC
--                              SIGNAL mac_out:OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
--                              SIGNAL mac_weight_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--                              SIGNAL mac_exit_port_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--                              SIGNAL mac_cnt_out: OUT std_logic_VECTOR(7 downto 0);
--                              SIGNAL mac_wr_out : OUT STD_LOGIC;
--                              SIGNAL wrd_cnt: OUT std_logic_VECTOR(7 downto 0)
        );
        END ENTITY;
 
 
 
 ------------------------------------------------------
        ARCHITECTURE behavior OF manager IS
                COMPONENT table is
                                generic (
                                                ADDR_WIDTH :integer := 10);
                        port (
                                                                SIGNAL  clk                     :       IN std_logic;
                                                                SIGNAL  reset           :       IN STD_LOGIC;
                                                                SIGNAL  in_mac          :       IN std_logic_VECTOR(47 downto 0);
                                                                SIGNAL  in_weight       :       IN std_logic_VECTOR(7 downto 0);
                                                                SIGNAL  in_port         :       IN std_logic_VECTOR(7 downto 0);
                                                                SIGNAL  in_wr           :       IN std_logic;
                                                                SIGNAL  in_rd           :       IN std_logic;
                                                                SIGNAL  in_key          : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                                                                SIGNAL  out_mac         :       OUT std_logic_VECTOR(47 downto 0);
                                                                SIGNAL  out_port        :       OUT std_logic_VECTOR(7 downto 0);
                                                                SIGNAL  out_rd_rdy      :       OUT std_logic
                        );
                end COMPONENT table ;
        -------COMPONENET SMALL FIFO
                                COMPONENT  small_fifo IS
                        GENERIC(WIDTH :INTEGER := 72;
                                        MAX_DEPTH_BITS :INTEGER := 3);
                        PORT(
 
 
                         SIGNAL din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
                         SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
 
                         SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word
 
                         SIGNAL dout :OUT STD_LOGIC_VECTOR(71 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
                         SIGNAL full : OUT STD_LOGIC;--output         full,
                         SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
                         SIGNAL empty : OUT STD_LOGIC;--output         empty,
 
 
                        SIGNAL reset :IN STD_LOGIC;
                        SIGNAL clk   :IN STD_LOGIC
 
                        );
                        END COMPONENT;
-------COMPONENET SMALL FIFO
------------ one hot encoding state definition
        TYPE state_type IS (IN_MODULE_HDRS,START,ADD_ENTRY,WORD_1,WORD_2,WORD_3,WORD_4,WORD_5,WORD_6, IN_PACKET);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_next : state_type;
 
---------------------------------------------------------------------------------------------------------
                  SIGNAL wr_en                  :       STD_LOGIC;
                  SIGNAL data_in                :       STD_LOGIC_VECTOR(71 DOWNTO 0);
                  SIGNAL rd_en                  :       STD_LOGIC;
                  SIGNAL rd_en_p                :       STD_LOGIC;
                  SIGNAL dout                   :       STD_LOGIC_VECTOR(71 DOWNTO 0);
                  SIGNAL fifo_data              :       STD_LOGIC_VECTOR(63 DOWNTO 0);--output reg
                  SIGNAL fifo_ctrl              :       STD_LOGIC_VECTOR(7 DOWNTO 0);--output
                  SIGNAL full                   :       STD_LOGIC;--output
                  SIGNAL nearly_full    :       STD_LOGIC;--output
                  SIGNAL empty                  :       STD_LOGIC;--output
 
                  SIGNAL table_in_mac_i : STD_LOGIC_VECTOR(47 DOWNTO 0);
                  SIGNAL table_in_wr_i : STD_LOGIC;
                  SIGNAL table_in_mac_i_e1 : STD_LOGIC;
                  SIGNAL table_in_mac_i_e2 : STD_LOGIC;
                  SIGNAL table_in_mac: STD_LOGIC_VECTOR(47 DOWNTO 0);
                  SIGNAL table_in_wr: STD_LOGIC;
                  SIGNAL table_in_rd: STD_LOGIC;
                  SIGNAL table_out_mac: STD_LOGIC_VECTOR(47 DOWNTO 0);
                  SIGNAL table_out_rd_rdy: STD_LOGIC;
                  SIGNAL word_cnt  : NATURAL ;
                  SIGNAL word_cnt_rst : STD_LOGIC;
                  SIGNAL mac_cnt  : INTEGER ;
                  SIGNAL mac_cnt_rdy : STD_LOGIC;
                  SIGNAL done_macs  : INTEGER ;
                  SIGNAL done_macs_up : STD_LOGIC;
                  SIGNAL done_macs_rst : STD_LOGIC;
                  SIGNAL mac: STD_LOGIC_VECTOR(47 DOWNTO 0);
                  SIGNAL mac_weight: STD_LOGIC_VECTOR(7 DOWNTO 0);
                  SIGNAL mac_exit_port: STD_LOGIC_VECTOR(7 DOWNTO 0);
                  SIGNAL mac_wr                 :STD_LOGIC;
                  SIGNAL mac_wr_i                       :STD_LOGIC;
 
        BEGIN
 
        table_Inst : table
                                generic MAP (ADDR_WIDTH =>10)
                        port MAP(
                                                                        clk                     =>      clk     ,
                                                                        reset           =>      reset   ,
                                                                        in_mac          =>      mac     ,
                                                                        in_weight       =>      mac_weight,
                                                                        in_port         =>      mac_exit_port,
                                                                        in_wr           =>      mac_wr  ,
                                                                        in_rd           =>      in_rd   ,
                                                                        in_key          =>  in_key      ,
                                                                        out_mac         =>      out_mac ,
                                                                        out_port        =>      out_port,
                                                                        out_rd_rdy      =>      out_rd_rdy
                        );
 
        -------PORT MAP SMALL FIFO
--              small_fifo_Inst :  small_fifo
--      GENERIC MAP(WIDTH  => 72,
--                      MAX_DEPTH_BITS  => 3)
--      PORT MAP(
--    din =>(data_in),
--      wr_en =>in_wr,
--      rd_en => rd_en,
--      dout =>dout,
--      full =>full,
--      nearly_full =>nearly_full,
--      empty => empty,
--      reset => reset ,
--      clk  => clk
--
--      );
--
---------PORT MAP SMALL FIFO
--              in_rdy <=  NOT nearly_full;
--              rd_en <=  (NOT empty);
--              fifo_data <=dout(71 DOWNTO 8);
--              fifo_ctrl <=DOUT(7 DOWNTO 0);
--              data_in<=in_data & in_ctrl;
                wr_en <= in_wr and en;
--              wrd_cnt <=  std_logic_vector(to_unsigned(word_cnt, 8));
--              mac_cnt_out <=  std_logic_vector(to_unsigned(mac_cnt, 8));
--              mac_out <=mac  ;
--              mac_weight_out<=mac_weight;
--              mac_exit_port_out <=mac_exit_port;
--              mac_wr_out      <=mac_wr;
                ----------------------------------------
--          mac <= fifo_data(63 downto 16) ;
--          mac_weight<= fifo_data(15 downto 8);
--          mac_exit_port<= fifo_data(7 downto 0);
--              mac_exit_port<= std_logic_vector(to_unsigned(done_macs, 8));
                PROCESS(clk)
                BEGIN
                        IF clk'EVENT AND clk ='1' THEN
                        rd_en_p <=rd_en;
                        END IF;
                END PROCESS;
 
                PROCESS(reset,clk)
                BEGIN
                        IF (reset ='1') THEN
                                state <=IN_MODULE_HDRS;
                        ELSIF clk'EVENT AND clk ='1' THEN
                                state<=state_next;
                        END IF;
                END PROCESS;
                PROCESS(state, fifo_data, rd_en_p, in_ctrl )
                        BEGIN
                                                                          mac_cnt_rdy   <= '0';
                                                                          done_macs_up  <= '0';
                                                                          done_macs_rst <= '0';
                                                                          mac_wr_i <= '0';
                                                                          word_cnt_rst                  <= '0';
                                                                          state_next <= state;
                                CASE state IS
                                        WHEN IN_MODULE_HDRS =>
                                                                           word_cnt_rst                         <= '1';
                                                                           done_macs_rst                        <= '1';
                                                IF ( in_ctrl=X"FF" and wr_en ='1' ) THEN
 
                                                        state_next                                      <= WORD_1;
                                                END IF;
 
                                        WHEN WORD_1             =>
                                         IF wr_en ='1'  THEN
 
                                                                          state_next                 <= WORD_2;
                                        END IF;
                                        WHEN WORD_2             =>
                                         IF wr_en ='1'  THEN
 
                                                                          state_next                 <= WORD_3;
                                        END IF;
                                        WHEN WORD_3             =>
                                         IF wr_en ='1'  THEN
 
                                                                          state_next                 <= WORD_4;
                                        END IF;
 
                                        WHEN WORD_4             =>
                                         IF wr_en ='1'  THEN
 
                                                                          state_next                 <= WORD_5;
 
                                        END IF;
                                        WHEN WORD_5             =>
                                         IF wr_en ='1'  THEN
 
                                                                          state_next                 <= WORD_6;
                                        END IF;
 
                                        WHEN WORD_6             =>
                                         IF wr_en ='1'  THEN
                                                                          mac_cnt_rdy   <= '1';
                                                                          done_macs_rst                         <= '1';
                                                                          state_next                 <= ADD_ENTRY;
                                        END IF;
 
                                        WHEN ADD_ENTRY =>
 
                                                                         IF (wr_en ='1'  AND in_ctrl /= X"00") THEN
                                                                                state_next                 <= IN_MODULE_HDRS;
                                                                         ELSIF wr_en ='1'  AND done_macs < mac_cnt THEN
 
                                                                                          done_macs_up  <= '1';
                                                                                          mac_wr_i <= '1';
                                                                                      state_next                 <= ADD_ENTRY;
 
                                                                        END IF;
 
                                        WHEN OTHERS             =>
                                END CASE;
                        END PROCESS;
 
        PROCESS(reset,clk)
                BEGIN
                        IF (reset ='1') THEN
                        ELSIF clk'EVENT AND clk ='1' THEN
                                IF mac_cnt_rdy = '1' THEN
                                  mac_cnt <= CONV_integer(in_data(31 downto 24));
                                END IF;
                                 mac <= in_data(63 downto 16) ;
                                 mac_weight<= in_data(15 downto 8);
                                 mac_exit_port<= in_data(7 downto 0);
                                 mac_wr<=mac_wr_i;
                        END IF;
                END PROCESS;
 
-------register out put
 
-------------
process (clk)
                variable   cnt             : integer range 0 to 255;
        begin
                if (rising_edge(clk)) then
 
                        if word_cnt_rst   = '1' then
                                -- Reset the counter to 0
                                cnt := 0;
 
                        elsif rd_en_p = '1' then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + 1;
 
                        end if;
                end if;
 
                -- Output the current count
                word_cnt <= cnt;
        end process;
 
        process (clk)
                variable   cnt             : integer range 0 to 255;
        begin
                if (rising_edge(clk)) then
 
                        if done_macs_rst = '1' then
                                -- Reset the counter to 0
                                cnt := 0;
 
                        elsif done_macs_up = '1' then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + 1;
 
                        end if;
                end if;
 
                -- Output the current count
                done_macs <= cnt;
        end process;
----------------
END behavior;
 
 

Browse

Tools

Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [TABLE/] [manager.vhd.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2			`library IEEE;`
3			`use IEEE.STD_LOGIC_1164.ALL;`
4			`use IEEE.STD_LOGIC_ARITH.ALL;`
5			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
6			`use ieee.numeric_std.all;`
7			`---------------------------------------------`
8
9			`ENTITY manager IS`
10			`GENERIC(DATA_WIDTH :INTEGER := 64;`
11			`CTRL_WIDTH :INTEGER := 8);`
12			`PORT(`
13
14			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
15			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
16			`SIGNAL in_wr :IN STD_LOGIC;`
17			`SIGNAL in_rdy : OUT STD_LOGIC;`
18			`SIGNAL in_rd: IN std_logic;`
19			`SIGNAL in_key : IN STD_LOGIC_VECTOR(9 DOWNTO 0);`
20			`SIGNAL out_mac: OUT std_logic_VECTOR(47 downto 0);`
21			`SIGNAL out_port: OUT std_logic_VECTOR(7 downto 0);`
22			`SIGNAL out_rd_rdy: OUT std_logic ;`
23			`SIGNAL out_rdy : IN STD_LOGIC;`
24			`SIGNAL en :IN STD_LOGIC;`
25			`SIGNAL reset :IN STD_LOGIC;`
26			`SIGNAL clk :IN STD_LOGIC`
27			`-- SIGNAL mac_out:OUT STD_LOGIC_VECTOR(47 DOWNTO 0);`
28			`-- SIGNAL mac_weight_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
29			`-- SIGNAL mac_exit_port_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
30			`-- SIGNAL mac_cnt_out: OUT std_logic_VECTOR(7 downto 0);`
31			`-- SIGNAL mac_wr_out : OUT STD_LOGIC;`
32			`-- SIGNAL wrd_cnt: OUT std_logic_VECTOR(7 downto 0)`
33			`);`
34			`END ENTITY;`
35
36
37
38			`------------------------------------------------------`
39			`ARCHITECTURE behavior OF manager IS`
40			`COMPONENT table is`
41			`generic (`
42			`ADDR_WIDTH :integer := 10);`
43			`port (`
44			`SIGNAL clk : IN std_logic;`
45			`SIGNAL reset : IN STD_LOGIC;`
46			`SIGNAL in_mac : IN std_logic_VECTOR(47 downto 0);`
47			`SIGNAL in_weight : IN std_logic_VECTOR(7 downto 0);`
48			`SIGNAL in_port : IN std_logic_VECTOR(7 downto 0);`
49			`SIGNAL in_wr : IN std_logic;`
50			`SIGNAL in_rd : IN std_logic;`
51			`SIGNAL in_key : IN STD_LOGIC_VECTOR(9 DOWNTO 0);`
52			`SIGNAL out_mac : OUT std_logic_VECTOR(47 downto 0);`
53			`SIGNAL out_port : OUT std_logic_VECTOR(7 downto 0);`
54			`SIGNAL out_rd_rdy : OUT std_logic`
55			`);`
56			`end COMPONENT table ;`
57			`-------COMPONENET SMALL FIFO`
58			`COMPONENT small_fifo IS`
59			`GENERIC(WIDTH :INTEGER := 72;`
60			`MAX_DEPTH_BITS :INTEGER := 3);`
61			`PORT(`
62
63
64			`SIGNAL din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);--input [WIDTH-1:0] din, // Data in`
65			`SIGNAL wr_en : IN STD_LOGIC;--input wr_en, // Write enable`
66
67			`SIGNAL rd_en : IN STD_LOGIC;--input rd_en, // Read the next word`
68
69			`SIGNAL dout :OUT STD_LOGIC_VECTOR(71 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out`
70			`SIGNAL full : OUT STD_LOGIC;--output full,`
71			`SIGNAL nearly_full : OUT STD_LOGIC;--output nearly_full,`
72			`SIGNAL empty : OUT STD_LOGIC;--output empty,`
73
74
75			`SIGNAL reset :IN STD_LOGIC;`
76			`SIGNAL clk :IN STD_LOGIC`
77
78			`);`
79			`END COMPONENT;`
80			`-------COMPONENET SMALL FIFO`
81			`------------ one hot encoding state definition`
82			`TYPE state_type IS (IN_MODULE_HDRS,START,ADD_ENTRY,WORD_1,WORD_2,WORD_3,WORD_4,WORD_5,WORD_6, IN_PACKET);`
83			`ATTRIBUTE enum_encoding: STRING;`
84			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
85
86			`SIGNAL state, state_next : state_type;`
87
88			`---------------------------------------------------------------------------------------------------------`
89			`SIGNAL wr_en : STD_LOGIC;`
90			`SIGNAL data_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
91			`SIGNAL rd_en : STD_LOGIC;`
92			`SIGNAL rd_en_p : STD_LOGIC;`
93			`SIGNAL dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
94			`SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);--output reg`
95			`SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);--output`
96			`SIGNAL full : STD_LOGIC;--output`
97			`SIGNAL nearly_full : STD_LOGIC;--output`
98			`SIGNAL empty : STD_LOGIC;--output`
99
100			`SIGNAL table_in_mac_i : STD_LOGIC_VECTOR(47 DOWNTO 0);`
101			`SIGNAL table_in_wr_i : STD_LOGIC;`
102			`SIGNAL table_in_mac_i_e1 : STD_LOGIC;`
103			`SIGNAL table_in_mac_i_e2 : STD_LOGIC;`
104			`SIGNAL table_in_mac: STD_LOGIC_VECTOR(47 DOWNTO 0);`
105			`SIGNAL table_in_wr: STD_LOGIC;`
106			`SIGNAL table_in_rd: STD_LOGIC;`
107			`SIGNAL table_out_mac: STD_LOGIC_VECTOR(47 DOWNTO 0);`
108			`SIGNAL table_out_rd_rdy: STD_LOGIC;`
109			`SIGNAL word_cnt : NATURAL ;`
110			`SIGNAL word_cnt_rst : STD_LOGIC;`
111			`SIGNAL mac_cnt : INTEGER ;`
112			`SIGNAL mac_cnt_rdy : STD_LOGIC;`
113			`SIGNAL done_macs : INTEGER ;`
114			`SIGNAL done_macs_up : STD_LOGIC;`
115			`SIGNAL done_macs_rst : STD_LOGIC;`
116			`SIGNAL mac: STD_LOGIC_VECTOR(47 DOWNTO 0);`
117			`SIGNAL mac_weight: STD_LOGIC_VECTOR(7 DOWNTO 0);`
118			`SIGNAL mac_exit_port: STD_LOGIC_VECTOR(7 DOWNTO 0);`
119			`SIGNAL mac_wr :STD_LOGIC;`
120			`SIGNAL mac_wr_i :STD_LOGIC;`
121
122			`BEGIN`
123
124			`table_Inst : table`
125			`generic MAP (ADDR_WIDTH =>10)`
126			`port MAP(`
127			`clk => clk ,`
128			`reset => reset ,`
129			`in_mac => mac ,`
130			`in_weight => mac_weight,`
131			`in_port => mac_exit_port,`
132			`in_wr => mac_wr ,`
133			`in_rd => in_rd ,`
134			`in_key => in_key ,`
135			`out_mac => out_mac ,`
136			`out_port => out_port,`
137			`out_rd_rdy => out_rd_rdy`
138			`);`
139
140			`-------PORT MAP SMALL FIFO`
141			`-- small_fifo_Inst : small_fifo`
142			`-- GENERIC MAP(WIDTH => 72,`
143			`-- MAX_DEPTH_BITS => 3)`
144			`-- PORT MAP(`
145			`-- din =>(data_in),`
146			`-- wr_en =>in_wr,`
147			`-- rd_en => rd_en,`
148			`-- dout =>dout,`
149			`-- full =>full,`
150			`-- nearly_full =>nearly_full,`
151			`-- empty => empty,`
152			`-- reset => reset ,`
153			`-- clk => clk`
154			`--`
155			`-- );`
156			`--`
157			`---------PORT MAP SMALL FIFO`
158			`-- in_rdy <= NOT nearly_full;`
159			`-- rd_en <= (NOT empty);`
160			`-- fifo_data <=dout(71 DOWNTO 8);`
161			`-- fifo_ctrl <=DOUT(7 DOWNTO 0);`
162			`-- data_in<=in_data & in_ctrl;`
163			`wr_en <= in_wr and en;`
164			`-- wrd_cnt <= std_logic_vector(to_unsigned(word_cnt, 8));`
165			`-- mac_cnt_out <= std_logic_vector(to_unsigned(mac_cnt, 8));`
166			`-- mac_out <=mac ;`
167			`-- mac_weight_out<=mac_weight;`
168			`-- mac_exit_port_out <=mac_exit_port;`
169			`-- mac_wr_out <=mac_wr;`
170			`----------------------------------------`
171			`-- mac <= fifo_data(63 downto 16) ;`
172			`-- mac_weight<= fifo_data(15 downto 8);`
173			`-- mac_exit_port<= fifo_data(7 downto 0);`
174			`-- mac_exit_port<= std_logic_vector(to_unsigned(done_macs, 8));`
175			`PROCESS(clk)`
176			`BEGIN`
177			`IF clk'EVENT AND clk ='1' THEN`
178			`rd_en_p <=rd_en;`
179			`END IF;`
180			`END PROCESS;`
181
182			`PROCESS(reset,clk)`
183			`BEGIN`
184			`IF (reset ='1') THEN`
185			`state <=IN_MODULE_HDRS;`
186			`ELSIF clk'EVENT AND clk ='1' THEN`
187			`state<=state_next;`
188			`END IF;`
189			`END PROCESS;`
190			`PROCESS(state, fifo_data, rd_en_p, in_ctrl )`
191			`BEGIN`
192			`mac_cnt_rdy <= '0';`
193			`done_macs_up <= '0';`
194			`done_macs_rst <= '0';`
195			`mac_wr_i <= '0';`
196			`word_cnt_rst <= '0';`
197			`state_next <= state;`
198			`CASE state IS`
199			`WHEN IN_MODULE_HDRS =>`
200			`word_cnt_rst <= '1';`
201			`done_macs_rst <= '1';`
202			`IF ( in_ctrl=X"FF" and wr_en ='1' ) THEN`
203
204			`state_next <= WORD_1;`
205			`END IF;`
206
207			`WHEN WORD_1 =>`
208			`IF wr_en ='1' THEN`
209
210			`state_next <= WORD_2;`
211			`END IF;`
212			`WHEN WORD_2 =>`
213			`IF wr_en ='1' THEN`
214
215			`state_next <= WORD_3;`
216			`END IF;`
217			`WHEN WORD_3 =>`
218			`IF wr_en ='1' THEN`
219
220			`state_next <= WORD_4;`
221			`END IF;`
222
223			`WHEN WORD_4 =>`
224			`IF wr_en ='1' THEN`
225
226			`state_next <= WORD_5;`
227
228			`END IF;`
229			`WHEN WORD_5 =>`
230			`IF wr_en ='1' THEN`
231
232			`state_next <= WORD_6;`
233			`END IF;`
234
235			`WHEN WORD_6 =>`
236			`IF wr_en ='1' THEN`
237			`mac_cnt_rdy <= '1';`
238			`done_macs_rst <= '1';`
239			`state_next <= ADD_ENTRY;`
240			`END IF;`
241
242			`WHEN ADD_ENTRY =>`
243
244			`IF (wr_en ='1' AND in_ctrl /= X"00") THEN`
245			`state_next <= IN_MODULE_HDRS;`
246			`ELSIF wr_en ='1' AND done_macs < mac_cnt THEN`
247
248			`done_macs_up <= '1';`
249			`mac_wr_i <= '1';`
250			`state_next <= ADD_ENTRY;`
251
252			`END IF;`
253
254			`WHEN OTHERS =>`
255			`END CASE;`
256			`END PROCESS;`
257
258			`PROCESS(reset,clk)`
259			`BEGIN`
260			`IF (reset ='1') THEN`
261			`ELSIF clk'EVENT AND clk ='1' THEN`
262			`IF mac_cnt_rdy = '1' THEN`
263			`mac_cnt <= CONV_integer(in_data(31 downto 24));`
264			`END IF;`
265			`mac <= in_data(63 downto 16) ;`
266			`mac_weight<= in_data(15 downto 8);`
267			`mac_exit_port<= in_data(7 downto 0);`
268			`mac_wr<=mac_wr_i;`
269			`END IF;`
270			`END PROCESS;`
271
272			`-------register out put`
273
274			`-------------`
275			`process (clk)`
276			`variable cnt : integer range 0 to 255;`
277			`begin`
278			`if (rising_edge(clk)) then`
279
280			`if word_cnt_rst = '1' then`
281			`-- Reset the counter to 0`
282			`cnt := 0;`
283
284			`elsif rd_en_p = '1' then`
285			`-- Increment the counter if counting is enabled`
286			`cnt := cnt + 1;`
287
288			`end if;`
289			`end if;`
290
291			`-- Output the current count`
292			`word_cnt <= cnt;`
293			`end process;`
294
295			`process (clk)`
296			`variable cnt : integer range 0 to 255;`
297			`begin`
298			`if (rising_edge(clk)) then`
299
300			`if done_macs_rst = '1' then`
301			`-- Reset the counter to 0`
302			`cnt := 0;`
303
304			`elsif done_macs_up = '1' then`
305			`-- Increment the counter if counting is enabled`
306			`cnt := cnt + 1;`
307
308			`end if;`
309			`end if;`
310
311			`-- Output the current count`
312			`done_macs <= cnt;`
313			`end process;`
314			`----------------`
315			`END behavior;`
316
317