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[/] [loadbalancer/] [trunk/] [TABLE/] [table.vhd.bak] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
 
entity table is
                generic (
                                ADDR_WIDTH :integer := 10);
        port (
                                                SIGNAL  clk                     :       IN std_logic;
                                                SIGNAL  reset           :       IN STD_LOGIC;
                                                SIGNAL  in_mac          :       IN std_logic_VECTOR(47 downto 0);
                                                SIGNAL  in_weight       :       IN std_logic_VECTOR(7 downto 0);
                                                SIGNAL  in_port         :       IN std_logic_VECTOR(7 downto 0);
                                                SIGNAL  in_wr           :       IN std_logic;
                                                SIGNAL  in_rd           :       IN std_logic;
                                                SIGNAL  in_key : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
--                                              SIGNAL  add             :       out std_logic_vector(11 downto 0);
--                                              SIGNAL  entry           :       OUT std_logic_VECTOR( 63 downto 0);
--                                              SIGNAL  rdy             :       out std_logic;
--                                              SIGNAL  check           :       out std_logic;
                                                SIGNAL  out_mac         :       OUT std_logic_VECTOR(47 downto 0);
                                                SIGNAL  out_port        :       OUT std_logic_VECTOR(7 downto 0);
                                                SIGNAL  out_rd_rdy      :       OUT std_logic
        );
end table ;
 
architecture Behavioral of table is
        TYPE state_type IS(IDLE, START, LATCH_MAC_LOOKUP, CHECK_MAC_MATCH, UPDATE_ENTRY, ADD_ENTRY);
        SIGNAL state, state_next : state_type;
 
-------COMPONENET SMALL FIFO
        COMPONENT  small_fifo IS
                GENERIC(WIDTH                           :       INTEGER := 64;
                                MAX_DEPTH_BITS          :       INTEGER := 5);
                PORT(
                                         SIGNAL din             :       IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input
                                         SIGNAL wr_en           :       IN STD_LOGIC;--input
                                         SIGNAL rd_en           :       IN STD_LOGIC;--input
                                         SIGNAL dout            :       OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output
                                         SIGNAL full            :       OUT STD_LOGIC;--output
                                         SIGNAL nearly_full :   OUT STD_LOGIC;--output
                                         SIGNAL empty           :       OUT STD_LOGIC;--output
                                         SIGNAL reset           :       IN STD_LOGIC;
                                         SIGNAL clk             :       IN STD_LOGIC
 
                );
        END COMPONENT;
-------COMPONENET SMALL FIFO
                COMPONENT  mac_ram_table is
                generic (
                                ADDR_WIDTH :integer := ADDR_WIDTH
                                );
                        port (
                                        SIGNAL          clk: IN std_logic;
                                        SIGNAL          reset : IN STD_LOGIC;
                                        SIGNAL          in_mac_no_prt: IN std_logic_VECTOR(63 downto 0);--MAC NUMBER internal port
                                        SIGNAL          in_address   : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                                        SIGNAL          in_wr: IN std_logic;
                                        SIGNAL          in_check : IN STD_LOGIC;
                                        SIGNAL          match_address : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
                                        SIGNAL          match:  OUT STD_LOGIC;
                                        SIGNAL          unmatch:  OUT STD_LOGIC;
                                        SIGNAL          in_rd : IN STD_LOGIC;
                                        SIGNAL          in_key : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                                        SIGNAL          last_address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                                        SIGNAL          out_rd_rdy : OUT std_logic;
                                        SIGNAL          out_port : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
                                        SIGNAL          out_mac : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                        );
                end COMPONENT mac_ram_table;
------------------------------------
 
        SIGNAL          ram_in_mac                      :       std_logic_VECTOR(63 downto 0);
        SIGNAL          ram_in_address          :       STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL          ram_in_wr                       :       std_logic;
        SIGNAL          ram_out_mac             :       STD_LOGIC_VECTOR(47 DOWNTO 0);
        SIGNAL          ram_in_rd                       :       STD_LOGIC;
        SIGNAL          ram_in_check            :       STD_LOGIC;
        SIGNAL          ram_out_rd_rdy          :       STD_LOGIC;
        SIGNAL          ram_match_address       :       STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL          ram_match                       :       STD_LOGIC;
        SIGNAL          ram_unmatch                     :       STD_LOGIC;
 
        SIGNAL          ram_in_wr_i             :       std_logic;
        SIGNAL          ram_in_address_e1_i :   std_logic;
        SIGNAL          ram_in_address_e2_i :   std_logic;
        SIGNAL          ram_in_check_i          :       std_logic;
        SIGNAL          ram_in_address_i        :       STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL          ram_in_mac_i            :       STD_LOGIC_VECTOR(63 DOWNTO 0);
 
        SIGNAL          fifo_rd                         :       STD_LOGIC ;
    SIGNAL              fifo_in                         :       STD_LOGIC_VECTOR(63 DOWNTO 0) ;
    SIGNAL              fifo_out                        :       STD_LOGIC_VECTOR(63 DOWNTO 0) ;
    SIGNAL              fifo_full                       :       STD_LOGIC;
    SIGNAL              fifo_nearly_fulL        :       STD_LOGIC;
    SIGNAL              fifo_empty                      :       STD_LOGIC;
 
 
 
        SUBTYPE         last_type IS  INTEGER RANGE 0 TO 2**ADDR_WIDTH-1;
    SIGNAL              last                            : last_type;
        SIGNAL          last_std                        : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL          weight_i                        :       INTEGER RANGE 0 TO 255;
        SIGNAL          weight_up                       :       STD_LOGIC;
        SIGNAL          weight_restart          :       STD_LOGIC;
begin
                -------PORT MAP SMALL FIFO DATA
 
 
                fifo_in <=in_mac & in_weight & in_port ;
                small_fifo_Inst :  small_fifo
                        GENERIC MAP(WIDTH                       => 64,
                                                MAX_DEPTH_BITS  => 8)
                        PORT MAP(
                                                din                             =>      fifo_in,
                                                wr_en                   =>      in_wr,
                                                rd_en                   =>      fifo_rd,
                                                dout                    =>      fifo_out,
                                                full                    =>      fifo_full,
                                                nearly_full     =>      fifo_nearly_full,
                                                empty                   =>      fifo_empty,
                                                reset                   =>      reset ,
                                                clk                     =>      clk
                                        );
--
 
-------COMPONENET SMALL FIFO
 
                ram_Inst :  mac_ram_table
                        GENERIC MAP     (ADDR_WIDTH => ADDR_WIDTH)
                        port MAP (
                        clk     => clk,
                        reset => reset,
                        in_mac_no_prt=> ram_in_mac,
                        in_address => ram_in_address,
                        in_check=> ram_in_check,
                        match_address =>ram_match_address,
                        match=>ram_match,
                        unmatch=>ram_unmatch,
                        in_wr=> ram_in_wr,
                        in_rd => in_rd,
                        in_key=>in_key,
                        last_address=>last_std,
                        out_port        => out_port,
                        out_rd_rdy => out_rd_rdy,
                        out_mac => out_mac
                        );
                        ram_in_mac(63 DOWNTO 16)<=fifo_out(63 DOWNTO 16);
                        ram_in_mac(15 DOWNTO 8)<=std_logic_vector(to_unsigned(weight_i, 8));
                        ram_in_mac(7 DOWNTO 0)<=fifo_out(7 DOWNTO 0);
--                      add             <=ram_in_address;
--                      entry   <= ram_in_mac;
--                      rdy         <= ram_in_wr;
--                      check   <= ram_in_check;
------------------------------------
        last_std <= std_logic_vector(to_unsigned(last+1, ADDR_WIDTH));
        PROCESS(clk, reset)
                BEGIN
                        IF reset= '1' THEN
                                        last <= 0 ;
                        ELSIF clk'EVENT AND clk = '1' THEN
                                IF (state =ADD_ENTRY )THEN last <= last +1   ;END IF;
                        END IF;
                END PROCESS;
 
        PROCESS(clk, reset)
                BEGIN
                        IF reset= '1' THEN
                        state   <=        IDLE    ;
                        ELSIF clk'EVENT AND clk = '1' THEN
                                state   <=        state_next      ;
                        END IF;
                END PROCESS;
        PROCESS(state)
                BEGIN
                                                        fifo_rd                 <= '0';
                                                        ram_in_wr               <= '0';
                                                        ram_in_check    <= '0';
                                                        ram_in_address  <= (OTHERS=>'0');
                                                        weight_up               <= '0';
                                                        weight_restart  <= '0';
                                                        state_next              <=        state;
 
 
                        CASE state IS
 
                                WHEN    IDLE =>
                                                IF fifo_empty = '0' THEN
                                                        fifo_rd <= '1';
 
                                                        state_next <= START;
                                                END IF;
                                                        weight_restart  <= '1';
                                WHEN    START =>
 
                                                        IF weight_i      >      fifo_out(15 DOWNTO 8)   THEN
                                                                state_next      <=        IDLE    ;
                                                        ELSE
                                                                state_next  <= LATCH_MAC_LOOKUP;
                                                        END IF;
 
                                WHEN    LATCH_MAC_LOOKUP =>
 
                                                                ram_in_check<= '1';
                                                                state_next      <= CHECK_MAC_MATCH;
 
                                WHEN    CHECK_MAC_MATCH =>
                                                IF ram_match = '1' THEN
                                                        state_next <= UPDATE_ENTRY;
                                                ELSIF ram_unmatch = '1' THEN
                                                        state_next <= ADD_ENTRY;
                                                END IF;
 
                                WHEN    UPDATE_ENTRY =>
                                                        ram_in_wr <='1';
                                                        ram_in_address <= ram_match_address;
                                                        weight_up       <=  '1';
                                                        state_next <= START;
 
                                WHEN    ADD_ENTRY =>
                                                        ram_in_wr <='1';
                                                        ram_in_address <=std_logic_vector(to_unsigned(last+1, ADDR_WIDTH));
                                                        weight_up       <=  '1';
                                                        state_next <= START;
                                WHEN OTHERS =>
                                                        state_next<= IDLE;
                                END CASE;
                END PROCESS;
---------------------------------------------------------------------
 
        process (clk)
                variable   cnt             : integer range 0 to 255;
        begin
                if (rising_edge(clk)) then
 
                        if weight_restart = '1' then
                                -- Reset the counter to 0
                                cnt := 0;
 
                        elsif weight_up = '1' then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + 1;
 
                        end if;
                end if;
        weight_i        <= cnt+1;
end process;
--------------------------------------------------------------------------------------------------------
 
end Behavioral;
 

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[/] [loadbalancer/] [trunk/] [TABLE/] [table.vhd.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla
2			`library IEEE;`
3			`use IEEE.STD_LOGIC_1164.ALL;`
4			`use IEEE.STD_LOGIC_ARITH.ALL;`
5			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
6			`use ieee.numeric_std.all;`
7
8
9			`entity table is`
10			`generic (`
11			`ADDR_WIDTH :integer := 10);`
12			`port (`
13			`SIGNAL clk : IN std_logic;`
14			`SIGNAL reset : IN STD_LOGIC;`
15			`SIGNAL in_mac : IN std_logic_VECTOR(47 downto 0);`
16			`SIGNAL in_weight : IN std_logic_VECTOR(7 downto 0);`
17			`SIGNAL in_port : IN std_logic_VECTOR(7 downto 0);`
18			`SIGNAL in_wr : IN std_logic;`
19			`SIGNAL in_rd : IN std_logic;`
20			`SIGNAL in_key : IN STD_LOGIC_VECTOR(11 DOWNTO 0);`
21			`-- SIGNAL add : out std_logic_vector(11 downto 0);`
22			`-- SIGNAL entry : OUT std_logic_VECTOR( 63 downto 0);`
23			`-- SIGNAL rdy : out std_logic;`
24			`-- SIGNAL check : out std_logic;`
25			`SIGNAL out_mac : OUT std_logic_VECTOR(47 downto 0);`
26			`SIGNAL out_port : OUT std_logic_VECTOR(7 downto 0);`
27			`SIGNAL out_rd_rdy : OUT std_logic`
28			`);`
29			`end table ;`
30
31			`architecture Behavioral of table is`
32			`TYPE state_type IS(IDLE, START, LATCH_MAC_LOOKUP, CHECK_MAC_MATCH, UPDATE_ENTRY, ADD_ENTRY);`
33			`SIGNAL state, state_next : state_type;`
34
35			`-------COMPONENET SMALL FIFO`
36			`COMPONENT small_fifo IS`
37			`GENERIC(WIDTH : INTEGER := 64;`
38			`MAX_DEPTH_BITS : INTEGER := 5);`
39			`PORT(`
40			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input`
41			`SIGNAL wr_en : IN STD_LOGIC;--input`
42			`SIGNAL rd_en : IN STD_LOGIC;--input`
43			`SIGNAL dout : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output`
44			`SIGNAL full : OUT STD_LOGIC;--output`
45			`SIGNAL nearly_full : OUT STD_LOGIC;--output`
46			`SIGNAL empty : OUT STD_LOGIC;--output`
47			`SIGNAL reset : IN STD_LOGIC;`
48			`SIGNAL clk : IN STD_LOGIC`
49
50			`);`
51			`END COMPONENT;`
52			`-------COMPONENET SMALL FIFO`
53			`COMPONENT mac_ram_table is`
54			`generic (`
55			`ADDR_WIDTH :integer := ADDR_WIDTH`
56			`);`
57			`port (`
58			`SIGNAL clk: IN std_logic;`
59			`SIGNAL reset : IN STD_LOGIC;`
60			`SIGNAL in_mac_no_prt: IN std_logic_VECTOR(63 downto 0);--MAC NUMBER internal port`
61			`SIGNAL in_address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);`
62			`SIGNAL in_wr: IN std_logic;`
63			`SIGNAL in_check : IN STD_LOGIC;`
64			`SIGNAL match_address : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);`
65			`SIGNAL match: OUT STD_LOGIC;`
66			`SIGNAL unmatch: OUT STD_LOGIC;`
67			`SIGNAL in_rd : IN STD_LOGIC;`
68			`SIGNAL in_key : IN STD_LOGIC_VECTOR(9 DOWNTO 0);`
69			`SIGNAL last_address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);`
70			`SIGNAL out_rd_rdy : OUT std_logic;`
71			`SIGNAL out_port : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
72			`SIGNAL out_mac : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)`
73			`);`
74			`end COMPONENT mac_ram_table;`
75			`------------------------------------`
76
77			`SIGNAL ram_in_mac : std_logic_VECTOR(63 downto 0);`
78			`SIGNAL ram_in_address : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
79			`SIGNAL ram_in_wr : std_logic;`
80			`SIGNAL ram_out_mac : STD_LOGIC_VECTOR(47 DOWNTO 0);`
81			`SIGNAL ram_in_rd : STD_LOGIC;`
82			`SIGNAL ram_in_check : STD_LOGIC;`
83			`SIGNAL ram_out_rd_rdy : STD_LOGIC;`
84			`SIGNAL ram_match_address : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
85			`SIGNAL ram_match : STD_LOGIC;`
86			`SIGNAL ram_unmatch : STD_LOGIC;`
87
88			`SIGNAL ram_in_wr_i : std_logic;`
89			`SIGNAL ram_in_address_e1_i : std_logic;`
90			`SIGNAL ram_in_address_e2_i : std_logic;`
91			`SIGNAL ram_in_check_i : std_logic;`
92			`SIGNAL ram_in_address_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
93			`SIGNAL ram_in_mac_i : STD_LOGIC_VECTOR(63 DOWNTO 0);`
94
95			`SIGNAL fifo_rd : STD_LOGIC ;`
96			`SIGNAL fifo_in : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
97			`SIGNAL fifo_out : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
98			`SIGNAL fifo_full : STD_LOGIC;`
99			`SIGNAL fifo_nearly_fulL : STD_LOGIC;`
100			`SIGNAL fifo_empty : STD_LOGIC;`
101
102
103
104			`SUBTYPE last_type IS INTEGER RANGE 0 TO 2**ADDR_WIDTH-1;`
105			`SIGNAL last : last_type;`
106			`SIGNAL last_std : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
107			`SIGNAL weight_i : INTEGER RANGE 0 TO 255;`
108			`SIGNAL weight_up : STD_LOGIC;`
109			`SIGNAL weight_restart : STD_LOGIC;`
110			`begin`
111			`-------PORT MAP SMALL FIFO DATA`
112
113
114			`fifo_in <=in_mac & in_weight & in_port ;`
115			`small_fifo_Inst : small_fifo`
116			`GENERIC MAP(WIDTH => 64,`
117			`MAX_DEPTH_BITS => 8)`
118			`PORT MAP(`
119			`din => fifo_in,`
120			`wr_en => in_wr,`
121			`rd_en => fifo_rd,`
122			`dout => fifo_out,`
123			`full => fifo_full,`
124			`nearly_full => fifo_nearly_full,`
125			`empty => fifo_empty,`
126			`reset => reset ,`
127			`clk => clk`
128			`);`
129			`--`
130
131			`-------COMPONENET SMALL FIFO`
132
133			`ram_Inst : mac_ram_table`
134			`GENERIC MAP (ADDR_WIDTH => ADDR_WIDTH)`
135			`port MAP (`
136			`clk => clk,`
137			`reset => reset,`
138			`in_mac_no_prt=> ram_in_mac,`
139			`in_address => ram_in_address,`
140			`in_check=> ram_in_check,`
141			`match_address =>ram_match_address,`
142			`match=>ram_match,`
143			`unmatch=>ram_unmatch,`
144			`in_wr=> ram_in_wr,`
145			`in_rd => in_rd,`
146			`in_key=>in_key,`
147			`last_address=>last_std,`
148			`out_port => out_port,`
149			`out_rd_rdy => out_rd_rdy,`
150			`out_mac => out_mac`
151			`);`
152			`ram_in_mac(63 DOWNTO 16)<=fifo_out(63 DOWNTO 16);`
153			`ram_in_mac(15 DOWNTO 8)<=std_logic_vector(to_unsigned(weight_i, 8));`
154			`ram_in_mac(7 DOWNTO 0)<=fifo_out(7 DOWNTO 0);`
155			`-- add <=ram_in_address;`
156			`-- entry <= ram_in_mac;`
157			`-- rdy <= ram_in_wr;`
158			`-- check <= ram_in_check;`
159			`------------------------------------`
160			`last_std <= std_logic_vector(to_unsigned(last+1, ADDR_WIDTH));`
161			`PROCESS(clk, reset)`
162			`BEGIN`
163			`IF reset= '1' THEN`
164			`last <= 0 ;`
165			`ELSIF clk'EVENT AND clk = '1' THEN`
166			`IF (state =ADD_ENTRY )THEN last <= last +1 ;END IF;`
167			`END IF;`
168			`END PROCESS;`
169
170			`PROCESS(clk, reset)`
171			`BEGIN`
172			`IF reset= '1' THEN`
173			`state <= IDLE ;`
174			`ELSIF clk'EVENT AND clk = '1' THEN`
175			`state <= state_next ;`
176			`END IF;`
177			`END PROCESS;`
178			`PROCESS(state)`
179			`BEGIN`
180			`fifo_rd <= '0';`
181			`ram_in_wr <= '0';`
182			`ram_in_check <= '0';`
183			`ram_in_address <= (OTHERS=>'0');`
184			`weight_up <= '0';`
185			`weight_restart <= '0';`
186			`state_next <= state;`
187
188
189			`CASE state IS`
190
191			`WHEN IDLE =>`
192			`IF fifo_empty = '0' THEN`
193			`fifo_rd <= '1';`
194
195			`state_next <= START;`
196			`END IF;`
197			`weight_restart <= '1';`
198			`WHEN START =>`
199
200			`IF weight_i > fifo_out(15 DOWNTO 8) THEN`
201			`state_next <= IDLE ;`
202			`ELSE`
203			`state_next <= LATCH_MAC_LOOKUP;`
204			`END IF;`
205
206			`WHEN LATCH_MAC_LOOKUP =>`
207
208			`ram_in_check<= '1';`
209			`state_next <= CHECK_MAC_MATCH;`
210
211			`WHEN CHECK_MAC_MATCH =>`
212			`IF ram_match = '1' THEN`
213			`state_next <= UPDATE_ENTRY;`
214			`ELSIF ram_unmatch = '1' THEN`
215			`state_next <= ADD_ENTRY;`
216			`END IF;`
217
218			`WHEN UPDATE_ENTRY =>`
219			`ram_in_wr <='1';`
220			`ram_in_address <= ram_match_address;`
221			`weight_up <= '1';`
222			`state_next <= START;`
223
224			`WHEN ADD_ENTRY =>`
225			`ram_in_wr <='1';`
226			`ram_in_address <=std_logic_vector(to_unsigned(last+1, ADDR_WIDTH));`
227			`weight_up <= '1';`
228			`state_next <= START;`
229			`WHEN OTHERS =>`
230			`state_next<= IDLE;`
231			`END CASE;`
232			`END PROCESS;`
233			`---------------------------------------------------------------------`
234
235			`process (clk)`
236			`variable cnt : integer range 0 to 255;`
237			`begin`
238			`if (rising_edge(clk)) then`
239
240			`if weight_restart = '1' then`
241			`-- Reset the counter to 0`
242			`cnt := 0;`
243
244			`elsif weight_up = '1' then`
245			`-- Increment the counter if counting is enabled`
246			`cnt := cnt + 1;`
247
248			`end if;`
249			`end if;`
250			`weight_i <= cnt+1;`
251			`end process;`
252			`--------------------------------------------------------------------------------------------------------`
253
254			`end Behavioral;`
255