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[/] [loadbalancer/] [trunk/] [TABLE/] [valid_address.vhd.bak] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
USE IEEE.STD_LOGIC_MISC.ALL;
entity valid_address is
generic (
        ADDR_WIDTH :integer := 12
    );
        port (
        clk: IN std_logic;
        reset : IN STD_LOGIC;
        in_wr_address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
        in_wr: IN std_logic;
        in_rd : IN STD_LOGIC;
        in_key : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
        in_rm_address_no : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
        in_rm : IN STD_LOGIC;
        out_address : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
        out_rdy : OUT std_logic
        -------------------------------
--      full_out: OUT std_logic;
--      empty_out: OUT std_logic;
--      current_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      last_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      item_value_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      item_ram_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      item_wr_out : OUT std_logic;
--      item_raddr_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      item_waddr_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      map_wr_out: OUT std_logic;
--      map_raddr_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      map_waddr_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      map_ram_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--      map_value_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
        );
end valid_address;
 
architecture Behavioral of valid_address is
-------------------------------------------------------------
 
        COMPONENT div_binary is
        Port (
 
        ina : in std_logic_vector (11 downto 0);
        inb: in std_logic_vector (11 downto 0);
        quot: out std_logic_vector (11 downto 0)
        );
 
end COMPONENT div_binary;
-------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
        GENERIC(WIDTH :INTEGER := 8;
                        MAX_DEPTH_BITS :INTEGER := 5);
        PORT(
     SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
     SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
     SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word
     SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
     SIGNAL full : OUT STD_LOGIC;--output         full,
     SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
     SIGNAL empty : OUT STD_LOGIC;--output         empty,
     SIGNAL reset :IN STD_LOGIC;
     SIGNAL clk   :IN STD_LOGIC
        );
        END COMPONENT;
-------COMPONENET SMALL FIFO
        TYPE state_type IS(IDLE,  ADD_1, ADD_2, REMOVE_1, REMOVE_2, REMOVE_3, REMOVE_4,REMOVE_5, READ_1, READ_2);
        SIGNAL state, state_next : state_type;
        attribute enum_encoding : string;
        attribute enum_encoding of state_type : type is "onehot";
 
------------------------------------------------------------
 
        SIGNAL item_raddr                       :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL item_waddr                       :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL item_value                       :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL item_wr_en                       :  STD_LOGIC;
        SIGNAL item_ram                         :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL item_raddr_i             :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL item_waddr_i             :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL item_value_i             :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL item_wr_en_i             :  STD_LOGIC;
 
 
        SIGNAL map_raddr                        :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL map_waddr                        :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL map_value                        :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL map_wr_en                        :  STD_LOGIC;
        SIGNAL map_ram                          :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL map_raddr_i                      :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL map_waddr_i                      :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL map_value_i                      :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL map_wr_en_i                      :  STD_LOGIC;
 
 
        SIGNAL last                             :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL last_up                          :  STD_LOGIC;
        SIGNAL last_down                        :  STD_LOGIC;
        SIGNAL current                          :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL current_up                       :  STD_LOGIC;
        SIGNAL last_i                           :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL last_up_i                        :  STD_LOGIC;
        SIGNAL last_down_i                      :  STD_LOGIC;
        SIGNAL current_i                        :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL current_up_i             :  STD_LOGIC;
        SIGNAL out_rdy_i                        :  STD_LOGIC;
        SIGNAL out_rdy_ii                       :  STD_LOGIC;
        SIGNAL empty                            :  STD_LOGIC;
        SIGNAL full                                     :  STD_LOGIC;
        -------------Fifos Signals-------------------------------
        SIGNAL write_cmd_rd             : STD_LOGIC;
        SIGNAL write_cmd_address        :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL write_cmd_empty          : STD_LOGIC;
        SIGNAL remove_cmd_rd            : STD_LOGIC;
        SIGNAL remove_cmd_address       :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL remove_cmd_empty         : STD_LOGIC;
        SIGNAL read_cmd_rd                      : STD_LOGIC;
        SIGNAL read_cmd_empty           : STD_LOGIC;
        SIGNAL write_cmd_rd_i           : STD_LOGIC;
        SIGNAL write_cmd_address_i      :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL write_cmd_empty_i        : STD_LOGIC;
        SIGNAL remove_cmd_rd_i          : STD_LOGIC;
        SIGNAL remove_cmd_address_i :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
        SIGNAL remove_cmd_empty_i       : STD_LOGIC;
        SIGNAL read_cmd_rd_i            : STD_LOGIC;
        SIGNAL read_cmd_empty_i         : STD_LOGIC;
        ---------------------------------------------------------
        COMPONENT ram_256x48 is
 
        generic
        (
                DATA_WIDTH : natural := ADDR_WIDTH;
                ADDR_WIDTH : natural := ADDR_WIDTH
        );
 
        port
        (
                clk             : in std_logic;
                raddr   : in natural range 0 to 2**ADDR_WIDTH - 1;
                waddr   : in natural range 0 to 2**ADDR_WIDTH - 1;
                data    : in std_logic_vector((DATA_WIDTH-1) downto 0);
                we              : in std_logic := '1';
                q               : out std_logic_vector((DATA_WIDTH -1) downto 0)
        );
 
end COMPONENT ram_256x48;
 
begin
-------------timeout management code------------------------
-------------Fifos to collect all the commands for farther processing
        write_command_Inst :  small_fifo
        GENERIC MAP(WIDTH  => ADDR_WIDTH,
                        MAX_DEPTH_BITS  => 5)
        PORT MAP(
                          din =>in_wr_address,
                          wr_en =>in_wr,
                          rd_en => write_cmd_rd,
                          dout =>write_cmd_address,
                          full =>open,
                          nearly_full =>open,
                          empty => write_cmd_empty,
                          reset => reset ,
                          clk  => clk
        );
        remove_command_Inst :  small_fifo
                GENERIC MAP(WIDTH  => ADDR_WIDTH,
                                MAX_DEPTH_BITS  => 5)
                PORT MAP(
                                  din =>in_rm_address_no,
                                  wr_en =>in_rm,
                                  rd_en => remove_cmd_rd,
                                  dout =>remove_cmd_address,
                                  full =>open,
                                  nearly_full =>open,
                                  empty => remove_cmd_empty,
                                  reset => reset ,
                                  clk  => clk
                );
        read_command_Inst :  small_fifo
                GENERIC MAP(WIDTH  => 1,
                                MAX_DEPTH_BITS  => 5)
                PORT MAP(
                                  din =>"1",
                                  wr_en =>in_rd,
                                  rd_en => read_cmd_rd,
                                  dout =>open,
                                  full =>open,
                                  nearly_full =>open,
                                  empty => read_cmd_empty,
                                  reset => reset ,
                                  clk  => clk
                );
 
--Map between the Value and the address used  inside the table the address is provided by out side
                valid_mac_Map_256x48_Inst : ram_256x48
 
                        GENERIC MAP     (
                                        DATA_WIDTH => ADDR_WIDTH, ADDR_WIDTH => ADDR_WIDTH)
 
                                port MAP (
                                        clk                     =>       clk            ,
                                        raddr       =>   CONV_INTEGER(map_raddr)                        ,
                                        waddr       =>   CONV_INTEGER(map_waddr)                        ,---last
                                        data        =>   map_value              ,
                                        we                  =>   map_wr_en              ,
                                        q                   =>   map_ram
                                );
--      item_wr_out<=item_wr_en;
--      item_raddr_out<=item_raddr;
--      item_waddr_out<=item_waddr;
--      item_value_out<=item_value;
--      item_ram_out <=item_ram;
--      map_wr_out<=map_wr_en;
--      map_raddr_out<=map_raddr;
--      map_waddr_out<=map_waddr;
--      map_value_out<=map_value;
--      map_ram_out <=map_ram;
--Write new MAC inside the table the address is provided by out side
                valid_mac_256x48_Inst : ram_256x48
 
                        GENERIC MAP     (
                                        DATA_WIDTH => ADDR_WIDTH, ADDR_WIDTH => ADDR_WIDTH)
 
                                port MAP (
                                        clk                     =>       clk            ,
                                        raddr       =>   CONV_INTEGER(item_raddr)                       ,
                                        waddr       =>   CONV_INTEGER(item_waddr)                       ,---last
                                        data        =>   item_value             ,
                                        we                  =>   item_wr_en             ,
                                        q                   =>   item_ram
                                );
                        out_address                     <=         item_ram  ;
 
--                      last_out <=item_waddr;
--                      current_out <=item_raddr;
--                      out_rdy <=item_wr_en;
        -----------------------------------------------------------------------
 
                PROCESS(clk, reset)
                                BEGIN
                                        IF reset= '1' THEN
                                                                state   <=        IDLE    ;
                                        ELSIF clk'EVENT AND clk = '1' THEN
                                                                state           <=        state_next      ;
                                                                out_rdy <= out_rdy_ii;
                                                                out_rdy_ii <= out_rdy_i;
                                        END IF;
        END PROCESS;
 
        PROCESS(state ,write_cmd_empty, remove_cmd_empty, read_cmd_empty )
                BEGIN
                                                                state_next      <=        state   ;
 
 
                CASE state IS
                WHEN IDLE =>
 
                                        IF (write_cmd_empty = '0')  THEN
                                                                state_next              <= ADD_1;
                                        ELSIF (remove_cmd_empty = '0')  THEN
                                                                state_next              <= REMOVE_1;
                                        ELSIF(read_cmd_empty = '0')THEN
                                                                state_next              <= READ_1;
                                        END IF;
                WHEN ADD_1              =>          state_next          <=        ADD_2   ;
                WHEN ADD_2              =>          state_next          <=        IDLE    ;
                WHEN REMOVE_1   =>          state_next          <=        REMOVE_2        ;
                WHEN REMOVE_2   =>          state_next          <=        REMOVE_3        ;
                WHEN REMOVE_3   =>          state_next          <=        REMOVE_4        ;
                WHEN REMOVE_4   =>          state_next          <=        REMOVE_5        ;
                WHEN REMOVE_5   =>          state_next          <=        IDLE    ;
                WHEN READ_1             =>          state_next          <=        READ_2  ;
                WHEN READ_2             =>          state_next          <=        IDLE    ;
                WHEN OTHERS             =>          state_next          <=        IDLE    ;
 
                END CASE;
        END PROCESS;
        ----------------------------------------------------
--      div_Inst :  div_binary
--      Port MAP (
--
--      ina =>in_key,
--      inb=>last,
--      quot => current
--      );
 
PROCESS(state, remove_cmd_address, last ,in_key,item_ram, write_cmd_address, full, map_ram)
                BEGIN
 
                                                                last_up         <= '0' ;
                                                                last_down       <= '0' ;
                                                                current_up_i    <= '0' ;
                                                            out_rdy_i           <= '0';
                                                            item_wr_en_i        <= '0';
                                                                item_raddr_i    <= (OTHERS=>'0');
                                                                item_waddr_i    <= (OTHERS=>'0');
                                                                item_value_i    <= (OTHERS=>'0');
                                                                map_raddr_i             <= (OTHERS=>'0');
                                                                map_waddr_i             <= (OTHERS=>'0');
                                                                map_value_i             <= (OTHERS=>'0');
                                                                map_wr_en_i             <= '0';
                                                                item_raddr_i    <= current;
                                                                write_cmd_rd    <='0';
                                                                remove_cmd_rd   <= '0';
                                                                read_cmd_rd     <='0';
 
                CASE state IS
                WHEN ADD_1 =>                   write_cmd_rd    <='1';        -- pop write fifo
                WHEN ADD_2      =>
                                                            map_waddr_i         <= write_cmd_address;
                                                            map_value_i         <= last ;
                                                            map_wr_en_i         <= NOT full;
                                                            item_value_i        <= write_cmd_address;
                                                            item_waddr_i    <= last  ;
                                                            item_wr_en_i        <= NOT full;
                                                            last_up             <= NOT full ;
 
                WHEN REMOVE_1   =>          remove_cmd_rd       <= '1';         -- pop remove fifo
                                                                last_down               <= '1';
                WHEN REMOVE_2   =>              map_raddr_i     <= remove_cmd_address;
                                                            item_raddr_i    <= last ;
 
                WHEN REMOVE_3   =>              --map_raddr_i     <= remove_cmd_address;
                                                            --item_raddr_i    <= last ;
--                                                              item_value_i    <= item_ram;--last
--                                                          item_waddr_i    <= map_ram ;--last address
--                                                              item_wr_en_i     <= '1';
--                                                          map_waddr_i         <= item_ram;--Update the Map Ram=last
--                                                          map_value_i         <= map_ram;--last = deleted
--                                                          map_wr_en_i         <= '1';
 
 
                WHEN REMOVE_4   =>              item_value_i    <= item_ram;--last
                                                            item_waddr_i    <= map_ram ;--last address
                                                            item_wr_en_i         <= '1';
                                                            map_waddr_i         <= item_ram;--Update the Map Ram=last
                                                            map_value_i         <= map_ram;--last = deleted
                                                            map_wr_en_i         <= '1';
                WHEN REMOVE_5   =>              item_value_i    <= (OTHERS=>'0');--last
                                                            item_waddr_i    <= last ;--last address
                                                            item_wr_en_i         <= '1';
                                                            map_waddr_i         <= remove_cmd_address;--Update the Map Ram=last
                                                            map_value_i         <= (OTHERS=>'0');--last = deleted
                                                            map_wr_en_i         <= '1';
 
 
                WHEN READ_1     =>                      read_cmd_rd     <='1';                -- pop read fifo
 
                                                                item_raddr_i    <= current;
 
                WHEN READ_2     =>
 
                                                            out_rdy_i           <= '1';
                                                            current_up_i        <= '1' ;
 
                WHEN OTHERS     =>
 
 
                END CASE;
        END PROCESS;
        -----------------Register Output
        process (clk)
        begin
                if (rising_edge(clk)) then
 
--                                                              last_up                 <=         last_up_i ;
--                                                              last_down               <=         last_down_i ;
                                                                current_up              <=         current_up_i ;
                                                                item_wr_en              <=         item_wr_en_i;
                                                                item_raddr              <=         item_raddr_i;
                                                                item_waddr              <=         item_waddr_i;
                                                                item_value              <=         item_value_i;
                                                                map_raddr               <=         map_raddr_i;
                                                                map_waddr               <=         map_waddr_i;
                                                                map_value               <=         map_value_i;
                                                                map_wr_en               <=         map_wr_en_i;
                                                                item_raddr      <=         item_raddr_i;
--                                                              write_cmd_rd    <=        write_cmd_rd_i;
--                                                              remove_cmd_rd   <=         remove_cmd_rd_i;
--                                                              read_cmd_rd             <=        read_cmd_rd_i;
                        end if;
                end PROCESS;
--------------------empty full controls----------------
   empty<='1' when last=1   else '0';
   full<='1'  when  AND_REDUCE(last)='1' else '0';
--   empty_out<=empty;
--      full_out<= full;
        ----------------------last counter------------------
        process (clk,last)
                variable   cnt             : integer range 0 to 2**ADDR_WIDTH-1;
        begin
                if (rising_edge(clk)) then
 
                        if reset = '1' then
                                -- Reset the counter to 0
                                cnt := 0;
 
                        elsif last_up = '1' then
                                -- Increment the counter if counting is enabled
                                cnt := cnt + 1;
                        elsif last_down = '1' then
                                -- Increment the counter if counting is enabled
                                cnt := cnt - 1;
 
                        end if;
                end if;
 
                -- Output the current count
                last <= std_logic_vector(to_unsigned(cnt, ADDR_WIDTH));
--              last_out <= last;
                END PROCESS;
----------------------last counter------------------
        process (clk)
                variable   cnt1            : integer range 0 to 2**ADDR_WIDTH-1;
                variable   cnt2            : integer range 0 to 2**ADDR_WIDTH-1;
        begin
                if (rising_edge(clk)) then
 
                        if ( current + 1 >=  last )AND current_up = '1'  then
                                -- Increment the counter if counting is enabled
                                cnt1 :=0 ;
                        elsif current_up = '1' then
                                -- Increment the counter if counting is enabled
                                cnt1 := cnt1 + 1;
 
                end if;
                end if;
                -- Output the current count
--              cnt2 := cnt1 mod CONV_INTEGER(last);
                current <= std_logic_vector(to_unsigned(cnt1, ADDR_WIDTH));
--         current_out <= current;
 
                END PROCESS;
---------------------------------------------------------
 
        END Behavioral;

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Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [TABLE/] [valid_address.vhd.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5			`use ieee.numeric_std.all;`
6			`USE IEEE.STD_LOGIC_MISC.ALL;`
7			`entity valid_address is`
8			`generic (`
9			`ADDR_WIDTH :integer := 12`
10			`);`
11			`port (`
12			`clk: IN std_logic;`
13			`reset : IN STD_LOGIC;`
14			`in_wr_address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);`
15			`in_wr: IN std_logic;`
16			`in_rd : IN STD_LOGIC;`
17			`in_key : IN STD_LOGIC_VECTOR(11 DOWNTO 0);`
18			`in_rm_address_no : IN STD_LOGIC_VECTOR(11 DOWNTO 0);`
19			`in_rm : IN STD_LOGIC;`
20			`out_address : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
21			`out_rdy : OUT std_logic`
22			`-------------------------------`
23			`-- full_out: OUT std_logic;`
24			`-- empty_out: OUT std_logic;`
25			`-- current_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
26			`-- last_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
27			`-- item_value_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
28			`-- item_ram_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
29			`-- item_wr_out : OUT std_logic;`
30			`-- item_raddr_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
31			`-- item_waddr_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
32			`-- map_wr_out: OUT std_logic;`
33			`-- map_raddr_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
34			`-- map_waddr_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
35			`-- map_ram_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
36			`-- map_value_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0)`
37			`);`
38			`end valid_address;`
39
40			`architecture Behavioral of valid_address is`
41			`-------------------------------------------------------------`
42
43			`COMPONENT div_binary is`
44			`Port (`
45
46			`ina : in std_logic_vector (11 downto 0);`
47			`inb: in std_logic_vector (11 downto 0);`
48			`quot: out std_logic_vector (11 downto 0)`
49			`);`
50
51			`end COMPONENT div_binary;`
52			`-------COMPONENET SMALL FIFO`
53			`COMPONENT small_fifo IS`
54			`GENERIC(WIDTH :INTEGER := 8;`
55			`MAX_DEPTH_BITS :INTEGER := 5);`
56			`PORT(`
57			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din, // Data in`
58			`SIGNAL wr_en : IN STD_LOGIC;--input wr_en, // Write enable`
59			`SIGNAL rd_en : IN STD_LOGIC;--input rd_en, // Read the next word`
60			`SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out`
61			`SIGNAL full : OUT STD_LOGIC;--output full,`
62			`SIGNAL nearly_full : OUT STD_LOGIC;--output nearly_full,`
63			`SIGNAL empty : OUT STD_LOGIC;--output empty,`
64			`SIGNAL reset :IN STD_LOGIC;`
65			`SIGNAL clk :IN STD_LOGIC`
66			`);`
67			`END COMPONENT;`
68			`-------COMPONENET SMALL FIFO`
69			`TYPE state_type IS(IDLE, ADD_1, ADD_2, REMOVE_1, REMOVE_2, REMOVE_3, REMOVE_4,REMOVE_5, READ_1, READ_2);`
70			`SIGNAL state, state_next : state_type;`
71			`attribute enum_encoding : string;`
72			`attribute enum_encoding of state_type : type is "onehot";`
73
74			`------------------------------------------------------------`
75
76			`SIGNAL item_raddr : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
77			`SIGNAL item_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
78			`SIGNAL item_value : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
79			`SIGNAL item_wr_en : STD_LOGIC;`
80			`SIGNAL item_ram : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
81			`SIGNAL item_raddr_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
82			`SIGNAL item_waddr_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
83			`SIGNAL item_value_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
84			`SIGNAL item_wr_en_i : STD_LOGIC;`
85
86
87			`SIGNAL map_raddr : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
88			`SIGNAL map_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
89			`SIGNAL map_value : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
90			`SIGNAL map_wr_en : STD_LOGIC;`
91			`SIGNAL map_ram : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
92			`SIGNAL map_raddr_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
93			`SIGNAL map_waddr_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
94			`SIGNAL map_value_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
95			`SIGNAL map_wr_en_i : STD_LOGIC;`
96
97
98			`SIGNAL last : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
99			`SIGNAL last_up : STD_LOGIC;`
100			`SIGNAL last_down : STD_LOGIC;`
101			`SIGNAL current : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
102			`SIGNAL current_up : STD_LOGIC;`
103			`SIGNAL last_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
104			`SIGNAL last_up_i : STD_LOGIC;`
105			`SIGNAL last_down_i : STD_LOGIC;`
106			`SIGNAL current_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
107			`SIGNAL current_up_i : STD_LOGIC;`
108			`SIGNAL out_rdy_i : STD_LOGIC;`
109			`SIGNAL out_rdy_ii : STD_LOGIC;`
110			`SIGNAL empty : STD_LOGIC;`
111			`SIGNAL full : STD_LOGIC;`
112			`-------------Fifos Signals-------------------------------`
113			`SIGNAL write_cmd_rd : STD_LOGIC;`
114			`SIGNAL write_cmd_address : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
115			`SIGNAL write_cmd_empty : STD_LOGIC;`
116			`SIGNAL remove_cmd_rd : STD_LOGIC;`
117			`SIGNAL remove_cmd_address : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
118			`SIGNAL remove_cmd_empty : STD_LOGIC;`
119			`SIGNAL read_cmd_rd : STD_LOGIC;`
120			`SIGNAL read_cmd_empty : STD_LOGIC;`
121			`SIGNAL write_cmd_rd_i : STD_LOGIC;`
122			`SIGNAL write_cmd_address_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
123			`SIGNAL write_cmd_empty_i : STD_LOGIC;`
124			`SIGNAL remove_cmd_rd_i : STD_LOGIC;`
125			`SIGNAL remove_cmd_address_i : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);`
126			`SIGNAL remove_cmd_empty_i : STD_LOGIC;`
127			`SIGNAL read_cmd_rd_i : STD_LOGIC;`
128			`SIGNAL read_cmd_empty_i : STD_LOGIC;`
129			`---------------------------------------------------------`
130			`COMPONENT ram_256x48 is`
131
132			`generic`
133			`(`
134			`DATA_WIDTH : natural := ADDR_WIDTH;`
135			`ADDR_WIDTH : natural := ADDR_WIDTH`
136			`);`
137
138			`port`
139			`(`
140			`clk : in std_logic;`
141			`raddr : in natural range 0 to 2**ADDR_WIDTH - 1;`
142			`waddr : in natural range 0 to 2**ADDR_WIDTH - 1;`
143			`data : in std_logic_vector((DATA_WIDTH-1) downto 0);`
144			`we : in std_logic := '1';`
145			`q : out std_logic_vector((DATA_WIDTH -1) downto 0)`
146			`);`
147
148			`end COMPONENT ram_256x48;`
149
150			`begin`
151			`-------------timeout management code------------------------`
152			`-------------Fifos to collect all the commands for farther processing`
153			`write_command_Inst : small_fifo`
154			`GENERIC MAP(WIDTH => ADDR_WIDTH,`
155			`MAX_DEPTH_BITS => 5)`
156			`PORT MAP(`
157			`din =>in_wr_address,`
158			`wr_en =>in_wr,`
159			`rd_en => write_cmd_rd,`
160			`dout =>write_cmd_address,`
161			`full =>open,`
162			`nearly_full =>open,`
163			`empty => write_cmd_empty,`
164			`reset => reset ,`
165			`clk => clk`
166			`);`
167			`remove_command_Inst : small_fifo`
168			`GENERIC MAP(WIDTH => ADDR_WIDTH,`
169			`MAX_DEPTH_BITS => 5)`
170			`PORT MAP(`
171			`din =>in_rm_address_no,`
172			`wr_en =>in_rm,`
173			`rd_en => remove_cmd_rd,`
174			`dout =>remove_cmd_address,`
175			`full =>open,`
176			`nearly_full =>open,`
177			`empty => remove_cmd_empty,`
178			`reset => reset ,`
179			`clk => clk`
180			`);`
181			`read_command_Inst : small_fifo`
182			`GENERIC MAP(WIDTH => 1,`
183			`MAX_DEPTH_BITS => 5)`
184			`PORT MAP(`
185			`din =>"1",`
186			`wr_en =>in_rd,`
187			`rd_en => read_cmd_rd,`
188			`dout =>open,`
189			`full =>open,`
190			`nearly_full =>open,`
191			`empty => read_cmd_empty,`
192			`reset => reset ,`
193			`clk => clk`
194			`);`
195
196			`--Map between the Value and the address used inside the table the address is provided by out side`
197			`valid_mac_Map_256x48_Inst : ram_256x48`
198
199			`GENERIC MAP (`
200			`DATA_WIDTH => ADDR_WIDTH, ADDR_WIDTH => ADDR_WIDTH)`
201
202			`port MAP (`
203			`clk => clk ,`
204			`raddr => CONV_INTEGER(map_raddr) ,`
205			`waddr => CONV_INTEGER(map_waddr) ,---last`
206			`data => map_value ,`
207			`we => map_wr_en ,`
208			`q => map_ram`
209			`);`
210			`-- item_wr_out<=item_wr_en;`
211			`-- item_raddr_out<=item_raddr;`
212			`-- item_waddr_out<=item_waddr;`
213			`-- item_value_out<=item_value;`
214			`-- item_ram_out <=item_ram;`
215			`-- map_wr_out<=map_wr_en;`
216			`-- map_raddr_out<=map_raddr;`
217			`-- map_waddr_out<=map_waddr;`
218			`-- map_value_out<=map_value;`
219			`-- map_ram_out <=map_ram;`
220			`--Write new MAC inside the table the address is provided by out side`
221			`valid_mac_256x48_Inst : ram_256x48`
222
223			`GENERIC MAP (`
224			`DATA_WIDTH => ADDR_WIDTH, ADDR_WIDTH => ADDR_WIDTH)`
225
226			`port MAP (`
227			`clk => clk ,`
228			`raddr => CONV_INTEGER(item_raddr) ,`
229			`waddr => CONV_INTEGER(item_waddr) ,---last`
230			`data => item_value ,`
231			`we => item_wr_en ,`
232			`q => item_ram`
233			`);`
234			`out_address <= item_ram ;`
235
236			`-- last_out <=item_waddr;`
237			`-- current_out <=item_raddr;`
238			`-- out_rdy <=item_wr_en;`
239			`-----------------------------------------------------------------------`
240
241			`PROCESS(clk, reset)`
242			`BEGIN`
243			`IF reset= '1' THEN`
244			`state <= IDLE ;`
245			`ELSIF clk'EVENT AND clk = '1' THEN`
246			`state <= state_next ;`
247			`out_rdy <= out_rdy_ii;`
248			`out_rdy_ii <= out_rdy_i;`
249			`END IF;`
250			`END PROCESS;`
251
252			`PROCESS(state ,write_cmd_empty, remove_cmd_empty, read_cmd_empty )`
253			`BEGIN`
254			`state_next <= state ;`
255
256
257			`CASE state IS`
258			`WHEN IDLE =>`
259
260			`IF (write_cmd_empty = '0') THEN`
261			`state_next <= ADD_1;`
262			`ELSIF (remove_cmd_empty = '0') THEN`
263			`state_next <= REMOVE_1;`
264			`ELSIF(read_cmd_empty = '0')THEN`
265			`state_next <= READ_1;`
266			`END IF;`
267			`WHEN ADD_1 => state_next <= ADD_2 ;`
268			`WHEN ADD_2 => state_next <= IDLE ;`
269			`WHEN REMOVE_1 => state_next <= REMOVE_2 ;`
270			`WHEN REMOVE_2 => state_next <= REMOVE_3 ;`
271			`WHEN REMOVE_3 => state_next <= REMOVE_4 ;`
272			`WHEN REMOVE_4 => state_next <= REMOVE_5 ;`
273			`WHEN REMOVE_5 => state_next <= IDLE ;`
274			`WHEN READ_1 => state_next <= READ_2 ;`
275			`WHEN READ_2 => state_next <= IDLE ;`
276			`WHEN OTHERS => state_next <= IDLE ;`
277
278			`END CASE;`
279			`END PROCESS;`
280			`----------------------------------------------------`
281			`-- div_Inst : div_binary`
282			`-- Port MAP (`
283			`--`
284			`-- ina =>in_key,`
285			`-- inb=>last,`
286			`-- quot => current`
287			`-- );`
288
289			`PROCESS(state, remove_cmd_address, last ,in_key,item_ram, write_cmd_address, full, map_ram)`
290			`BEGIN`
291
292			`last_up <= '0' ;`
293			`last_down <= '0' ;`
294			`current_up_i <= '0' ;`
295			`out_rdy_i <= '0';`
296			`item_wr_en_i <= '0';`
297			`item_raddr_i <= (OTHERS=>'0');`
298			`item_waddr_i <= (OTHERS=>'0');`
299			`item_value_i <= (OTHERS=>'0');`
300			`map_raddr_i <= (OTHERS=>'0');`
301			`map_waddr_i <= (OTHERS=>'0');`
302			`map_value_i <= (OTHERS=>'0');`
303			`map_wr_en_i <= '0';`
304			`item_raddr_i <= current;`
305			`write_cmd_rd <='0';`
306			`remove_cmd_rd <= '0';`
307			`read_cmd_rd <='0';`
308
309			`CASE state IS`
310			`WHEN ADD_1 => write_cmd_rd <='1'; -- pop write fifo`
311			`WHEN ADD_2 =>`
312			`map_waddr_i <= write_cmd_address;`
313			`map_value_i <= last ;`
314			`map_wr_en_i <= NOT full;`
315			`item_value_i <= write_cmd_address;`
316			`item_waddr_i <= last ;`
317			`item_wr_en_i <= NOT full;`
318			`last_up <= NOT full ;`
319
320			`WHEN REMOVE_1 => remove_cmd_rd <= '1'; -- pop remove fifo`
321			`last_down <= '1';`
322			`WHEN REMOVE_2 => map_raddr_i <= remove_cmd_address;`
323			`item_raddr_i <= last ;`
324
325			`WHEN REMOVE_3 => --map_raddr_i <= remove_cmd_address;`
326			`--item_raddr_i <= last ;`
327			`-- item_value_i <= item_ram;--last`
328			`-- item_waddr_i <= map_ram ;--last address`
329			`-- item_wr_en_i <= '1';`
330			`-- map_waddr_i <= item_ram;--Update the Map Ram=last`
331			`-- map_value_i <= map_ram;--last = deleted`
332			`-- map_wr_en_i <= '1';`
333
334
335			`WHEN REMOVE_4 => item_value_i <= item_ram;--last`
336			`item_waddr_i <= map_ram ;--last address`
337			`item_wr_en_i <= '1';`
338			`map_waddr_i <= item_ram;--Update the Map Ram=last`
339			`map_value_i <= map_ram;--last = deleted`
340			`map_wr_en_i <= '1';`
341			`WHEN REMOVE_5 => item_value_i <= (OTHERS=>'0');--last`
342			`item_waddr_i <= last ;--last address`
343			`item_wr_en_i <= '1';`
344			`map_waddr_i <= remove_cmd_address;--Update the Map Ram=last`
345			`map_value_i <= (OTHERS=>'0');--last = deleted`
346			`map_wr_en_i <= '1';`
347
348
349			`WHEN READ_1 => read_cmd_rd <='1'; -- pop read fifo`
350
351			`item_raddr_i <= current;`
352
353			`WHEN READ_2 =>`
354
355			`out_rdy_i <= '1';`
356			`current_up_i <= '1' ;`
357
358			`WHEN OTHERS =>`
359
360
361			`END CASE;`
362			`END PROCESS;`
363			`-----------------Register Output`
364			`process (clk)`
365			`begin`
366			`if (rising_edge(clk)) then`
367
368			`-- last_up <= last_up_i ;`
369			`-- last_down <= last_down_i ;`
370			`current_up <= current_up_i ;`
371			`item_wr_en <= item_wr_en_i;`
372			`item_raddr <= item_raddr_i;`
373			`item_waddr <= item_waddr_i;`
374			`item_value <= item_value_i;`
375			`map_raddr <= map_raddr_i;`
376			`map_waddr <= map_waddr_i;`
377			`map_value <= map_value_i;`
378			`map_wr_en <= map_wr_en_i;`
379			`item_raddr <= item_raddr_i;`
380			`-- write_cmd_rd <= write_cmd_rd_i;`
381			`-- remove_cmd_rd <= remove_cmd_rd_i;`
382			`-- read_cmd_rd <= read_cmd_rd_i;`
383			`end if;`
384			`end PROCESS;`
385			`--------------------empty full controls----------------`
386			`empty<='1' when last=1 else '0';`
387			`full<='1' when AND_REDUCE(last)='1' else '0';`
388			`-- empty_out<=empty;`
389			`-- full_out<= full;`
390			`----------------------last counter------------------`
391			`process (clk,last)`
392			`variable cnt : integer range 0 to 2**ADDR_WIDTH-1;`
393			`begin`
394			`if (rising_edge(clk)) then`
395
396			`if reset = '1' then`
397			`-- Reset the counter to 0`
398			`cnt := 0;`
399
400			`elsif last_up = '1' then`
401			`-- Increment the counter if counting is enabled`
402			`cnt := cnt + 1;`
403			`elsif last_down = '1' then`
404			`-- Increment the counter if counting is enabled`
405			`cnt := cnt - 1;`
406
407			`end if;`
408			`end if;`
409
410			`-- Output the current count`
411			`last <= std_logic_vector(to_unsigned(cnt, ADDR_WIDTH));`
412			`-- last_out <= last;`
413			`END PROCESS;`
414			`----------------------last counter------------------`
415			`process (clk)`
416			`variable cnt1 : integer range 0 to 2**ADDR_WIDTH-1;`
417			`variable cnt2 : integer range 0 to 2**ADDR_WIDTH-1;`
418			`begin`
419			`if (rising_edge(clk)) then`
420
421			`if ( current + 1 >= last )AND current_up = '1' then`
422			`-- Increment the counter if counting is enabled`
423			`cnt1 :=0 ;`
424			`elsif current_up = '1' then`
425			`-- Increment the counter if counting is enabled`
426			`cnt1 := cnt1 + 1;`
427
428			`end if;`
429			`end if;`
430			`-- Output the current count`
431			`-- cnt2 := cnt1 mod CONV_INTEGER(last);`
432			`current <= std_logic_vector(to_unsigned(cnt1, ADDR_WIDTH));`
433			`-- current_out <= current;`
434
435			`END PROCESS;`
436			`---------------------------------------------------------`
437
438			`END Behavioral;`