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[/] [loadbalancer/] [trunk/] [balancer_top.vhd.bak] - Blame information for rev 2

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-------------------------------------------
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
-------------------------------
 
        ENTITY  balancer_top IS
        GENERIC(        DATA_WIDTH :INTEGER := 64;
                                CTRL_WIDTH :INTEGER := 8);
        PORT(
 
                                SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                                SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                                SIGNAL in_wr :IN STD_LOGIC;
                                SIGNAL in_rdy : OUT STD_LOGIC;
 
                                SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
                                SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
                                SIGNAL out_wr : OUT STD_LOGIC;
                                SIGNAL out_rdy : IN STD_LOGIC;
                                SIGNAL          dest_out                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                                SIGNAL reset :IN STD_LOGIC;
                                SIGNAL clk   :IN STD_LOGIC
        );
        END ENTITY;
 
        ARCHITECTURE behavior OF balancer_top IS
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
COMPONENT  int2ext_top IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
                SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr :IN STD_LOGIC;
                SIGNAL in_rdy : OUT STD_LOGIC;
 
                SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL out_wr : OUT STD_LOGIC;
                SIGNAL out_rdy : IN STD_LOGIC;
 
                SIGNAL     en : IN STD_LOGIC;
 
                SIGNAL reset :IN STD_LOGIC;
                SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT int2ext_top;
--
--              COMPONENT  hello_pkt IS
--      GENERIC(DATA_WIDTH :INTEGER := 64;
--                      CTRL_WIDTH :INTEGER := 8);
--      PORT(
--
--                       SIGNAL tx_in_data : IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
--                       SIGNAL tx_in_ctrl : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
--                       SIGNAL tx_in_wr :      IN STD_LOGIC;
--                       SIGNAL rx_in_data : IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
--                       SIGNAL rx_in_ctrl : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
--                       SIGNAL rx_in_wr   : IN STD_LOGIC;
--
--                       SIGNAL out_data   : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
--                       SIGNAL out_ctrl   : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
--                       SIGNAL out_wr     : OUT STD_LOGIC;
--              --      SIGNAL out_cnt : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
--              --      SIGNAL cnt_enable :OUT STD_LOGIC;
--                       SIGNAL out_rdy    :    IN STD_LOGIC;
--                       SIGNAL in_rdy     :    OUT STD_LOGIC;
--                       SIGNAL reset      :    IN STD_LOGIC;
--                       SIGNAL clk        :    IN STD_LOGIC
--      );
--      END COMPONENT hello_pkt;
--------------------- Classifier Component------------
        COMPONENT  classifier IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
        SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL in_wr :IN STD_LOGIC;
        SIGNAL in_rdy : OUT STD_LOGIC;
 
        SIGNAL out_data :OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr : OUT STD_LOGIC;
        SIGNAL out_rdy : IN STD_LOGIC;
    SIGNAL              dest                    :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
        );
        END COMPONENT classifier;
------------End Classifier Component
-------- Classifier Arbiter -----------
        COMPONENT classifier_arbiter IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
                SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL out_wr : OUT STD_LOGIC;
                SIGNAL out_rdy : IN STD_LOGIC;
 
                SIGNAL in_data_0 :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl_0 : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr_0 :IN STD_LOGIC;
                SIGNAL in_rdy_0 : OUT STD_LOGIC;
 
                SIGNAL in_data_1 :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl_1 : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr_1 :IN STD_LOGIC;
                SIGNAL in_rdy_1 : OUT STD_LOGIC;
 
                SIGNAL in_data_2 :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl_2 : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr_2 :IN STD_LOGIC;
                SIGNAL in_rdy_2 : OUT STD_LOGIC;
 
                SIGNAL in_data_3 :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl_3 : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr_3 :IN STD_LOGIC;
                SIGNAL in_rdy_3 : OUT STD_LOGIC;
 
                SIGNAL in_data_4 :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl_4 : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr_4 :IN STD_LOGIC;
                SIGNAL in_rdy_4 : OUT STD_LOGIC;
 
                SIGNAL in_data_5 :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl_5 : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr_5 :IN STD_LOGIC;
                SIGNAL in_rdy_5 : OUT STD_LOGIC;
 
                SIGNAL in_data_6 :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl_6 : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr_6 :IN STD_LOGIC;
                SIGNAL in_rdy_6 : OUT STD_LOGIC;
 
                SIGNAL in_data_7 :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                SIGNAL in_ctrl_7 : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                SIGNAL in_wr_7 :IN STD_LOGIC;
                SIGNAL in_rdy_7 : OUT STD_LOGIC;
 
                SIGNAL reset :IN STD_LOGIC;
                SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT classifier_arbiter;
----------------------------Arp Top Component
        COMPONENT arp_top IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
        SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL in_wr :IN STD_LOGIC;
        SIGNAL in_rdy : OUT STD_LOGIC;
 
        SIGNAL out_data :OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr : OUT STD_LOGIC;
        SIGNAL out_rdy : IN STD_LOGIC;
 
 
    --- Misc
     SIGNAL     en : IN STD_LOGIC;
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
        );
        END COMPONENT arp_top;
--      --------------- Balance Component-----
        COMPONENT   balance_top IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
        SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL in_wr :IN STD_LOGIC;
        SIGNAL in_rdy : OUT STD_LOGIC;
 
        ----------------
        SIGNAL in_next_mac :IN   STD_LOGIC_VECTOR(47 DOWNTO 0);
        SIGNAL in_exit_port :IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
        SIGNAL in_next_mac_rdy : IN STD_LOGIC;
        SIGNAL out_rd_next_mac : OUT STD_LOGIC;
        SIGNAL key :  OUT   STD_LOGIC_VECTOR(11 DOWNTO 0);
        -------------------
        SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr : OUT STD_LOGIC;
        SIGNAL out_rdy : IN STD_LOGIC;
        SIGNAL en :IN STD_LOGIC;
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT balance_top;
 
--      --------------- Router Component-----
        COMPONENT  router IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
         SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
         SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
     SIGNAL in_wr :IN STD_LOGIC;
         SIGNAL in_rdy : OUT STD_LOGIC;
 
         SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
         SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
     SIGNAL out_wr : OUT STD_LOGIC;
         SIGNAL out_rdy : IN STD_LOGIC;
 
         SIGNAL     en : IN STD_LOGIC;
     SIGNAL reset :IN STD_LOGIC;
     SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT;
-------------Pass Component-----
        COMPONENT  pass IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
        SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL in_wr :IN STD_LOGIC;
        SIGNAL in_rdy : OUT STD_LOGIC;
 
        SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr : OUT STD_LOGIC;
        SIGNAL out_rdy : IN STD_LOGIC;
         SIGNAL     en : IN STD_LOGIC;
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT  pass;
---------------------------------------------------------------------------------------
-------------Manager Component-----
        COMPONENT manager IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
                                SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                                SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                                SIGNAL in_wr :IN STD_LOGIC;
                                SIGNAL in_rdy : OUT STD_LOGIC;
                                SIGNAL in_rd: IN std_logic;
                                SIGNAL in_key           : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
                                SIGNAL out_mac: OUT std_logic_VECTOR(47 downto 0);
                                SIGNAL out_port: OUT std_logic_VECTOR(7 downto 0);
                                SIGNAL out_rd_rdy: OUT std_logic        ;
                                SIGNAL out_rdy : IN STD_LOGIC;
                                SIGNAL reset :IN STD_LOGIC;
                                SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT  manager;
---------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
        SIGNAL out_data_classifier :    STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl_classifier :  STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr_classifier :  STD_LOGIC;
        SIGNAL out_rdy_classifier :  STD_LOGIC;
         SIGNAL                 dest_i                  :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
-------------------------------------------------------------------------------------
        SIGNAL out_data_arp :    STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl_arp :   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr_arp :  STD_LOGIC;
    SIGNAL in_rdy_arp :  STD_LOGIC;
 
-------------------------------------------------------------------------------------
        SIGNAL out_data_balance :    STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl_balance :   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr_balance :  STD_LOGIC;
    SIGNAL in_rdy_balance :  STD_LOGIC;
-------------------------------------------------------------------------------------
        SIGNAL out_data_router :    STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl_router :   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr_router :  STD_LOGIC;
    SIGNAL in_rdy_router :  STD_LOGIC;
-----------------------------------------------------------------------------------
         SIGNAL out_data_hello :    STD_LOGIC_VECTOR(63 DOWNTO 0);
         SIGNAL out_ctrl_hello :   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr_hello :  STD_LOGIC;
    SIGNAL in_rdy_hello :  STD_LOGIC;
-------------------------------------------------------------------------------------
        SIGNAL out_data_pass :    STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL out_ctrl_pass :   STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL out_wr_pass :  STD_LOGIC;
    SIGNAL in_rdy_pass :  STD_LOGIC;
    SIGNAL in_rdy_0 :  STD_LOGIC;
    SIGNAL in_rdy_1 :  STD_LOGIC;
        SIGNAL in_rdy_2 :  STD_LOGIC;
        SIGNAL in_rdy_3 :  STD_LOGIC;
        SIGNAL in_rdy_4 :  STD_LOGIC;
                SIGNAL in_rdy_5 :  STD_LOGIC;
        ----------------------------------
        SIGNAL in_rdy_manger : STD_LOGIC;
        SIGNAL in_rd_manger:  std_logic;
        SIGNAL out_mac_manger:  std_logic_VECTOR(47 downto 0);
        SIGNAL out_port_manger:  std_logic_VECTOR(7 downto 0);
        SIGNAL key:  std_logic_VECTOR(11 downto 0);
        SIGNAL out_rd_rdy_manger:  std_logic    ;
        ----------------------------
 
         SIGNAL out_data_arb :    STD_LOGIC_VECTOR(63 DOWNTO 0);
         SIGNAL out_ctrl_arb :   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr_arb :  STD_LOGIC;
    SIGNAL out_rdy_arb :  STD_LOGIC;
         ------------------
          SIGNAL out_data_int :    STD_LOGIC_VECTOR(63 DOWNTO 0);
         SIGNAL out_ctrl_int :   STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL out_wr_int :  STD_LOGIC;
    SIGNAL in_rdy_int :  STD_LOGIC;
 
--
        BEGIN
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
--
out_rdy_classifier <=  in_rdy_pass ;--AND in_rdy_int  and in_rdy_balance AND in_rdy_router ;--AND in_rdy_arp;--    AND in_rdy_int AND in_rdy_router;
 
--------------------- Classifier Port Map------------
 
        classifier_Inst :  classifier
        GENERIC MAP(DATA_WIDTH => 64,
                                CTRL_WIDTH  => 8)
        PORT MAP(
        --Input
 
         in_data => in_data,
         in_ctrl => in_ctrl,
     in_wr => in_wr,
          in_rdy => in_rdy,--this is to be connected with out_rdy from the pervious module this is out put port
        ---Output
 
--      out_data => out_data,
--       out_ctrl => out_ctrl,
--    out_wr => out_wr,
--       out_rdy =>  out_rdy ,
                 out_data => out_data_classifier,
                 out_ctrl => out_ctrl_classifier,
                 out_wr => out_wr_classifier,
                 out_rdy =>out_rdy_classifier,-- this is input port
        --- Misc
            dest =>dest_i,
            reset => reset,
            clk   => clk
        );
 
 dest_out <=  dest_i;
--------------End Classifier Port Map
--
------------------------------Arp Top Component
--      arp_top_Ins : arp_top
--      GENERIC MAP(DATA_WIDTH => 64,
--                              CTRL_WIDTH  => 8)
--      PORT MAP(
--        in_data => out_data_classifier ,
--        in_ctrl => out_ctrl_classifier,
--     in_wr => out_wr_classifier,
--        in_rdy =>in_rdy_arp,
--
--        out_data => out_data_arp,
--        out_ctrl => out_ctrl_arp,
--     out_wr => out_wr_arp,
--        out_rdy =>in_rdy_0,
--
--
--    --- Misc
--     en => dest_i(0),
--     reset => reset,
--     clk   => clk
--      );
--
------  ---------------Balance Component----
 
 
        balance_Inst :   balance_top
        GENERIC MAP(DATA_WIDTH => 64,
                                CTRL_WIDTH  => 8)
        PORT MAP(
 
          in_data => out_data_classifier,
          in_ctrl => out_ctrl_classifier,
     in_wr => out_wr_classifier,
          in_rdy => in_rdy_balance,
 
          out_data => out_data_balance,
          out_ctrl => out_ctrl_balance,
     out_wr => out_wr_balance,
          out_rdy =>in_rdy_1,
 
          in_next_mac =>out_mac_manger,
          in_exit_port => out_port_manger,
      out_rd_next_mac => in_rd_manger,
          in_next_mac_rdy =>out_rd_rdy_manger,
          key => open,
 
 
--      out_data => out_data,
--       out_ctrl => out_ctrl,
--    out_wr => out_wr,
--       out_rdy =>  out_rdy ,
 
          en => dest_i(1),
     reset => reset,
     clk   => clk
 
        );
------  ---------------Balance Component-----
        router_Inst :   router
        GENERIC MAP(DATA_WIDTH => 64,
                                CTRL_WIDTH  => 8)
        PORT MAP(
 
         in_data => out_data_classifier,
         in_ctrl => out_ctrl_classifier,
     in_wr => out_wr_classifier,
         in_rdy => in_rdy_router,
 
         out_data => out_data_router,
         out_ctrl => out_ctrl_router,
     out_wr => out_wr_router,
         out_rdy =>in_rdy_3,
         en => dest_i(2),
     reset => reset,
     clk   => clk
 
        );
-----------------Pass Component-----
        pass_Inst :   pass
        GENERIC MAP(DATA_WIDTH => 64,
                                CTRL_WIDTH  => 8)
        PORT MAP(
 
         in_data => out_data_classifier,
         in_ctrl => out_ctrl_classifier,
    in_wr => out_wr_classifier,
         in_rdy => in_rdy_pass,
 
         out_data => out_data_pass,
         out_ctrl => out_ctrl_pass,
    out_wr => out_wr_pass,
         out_rdy =>in_rdy_5,
--       out_data => out_data,
--       out_ctrl => out_ctrl,
--       out_wr => out_wr,
--       out_rdy =>  out_rdy ,
         en =>dest_i(7),
     reset => reset,
     clk   => clk
 
        );
--      ----------------------------------------------
------  ----------------Pass Component-----
------
------
        manager_Inst :   manager
        GENERIC MAP(DATA_WIDTH => 64,
                                CTRL_WIDTH  => 8)
        PORT MAP(
 
         in_data => out_data_classifier,
         in_ctrl => out_ctrl_classifier,
     in_wr => out_wr_classifier,
         in_rdy => in_rdy_manger,
 
          in_rd => in_rd_manger,
          in_key => (OTHERS=>'0'),
          out_mac => out_mac_manger,
          out_port=>out_port_manger,
     out_rd_rdy => out_rd_rdy_manger,
         out_rdy =>'1',
 
     reset => reset,
     clk   => clk
 
        );
--------------------------Hello----
------  Hello_Ist :   hello_pkt
------  GENERIC MAP(DATA_WIDTH => 64,
------                          CTRL_WIDTH  => 8)
------  PORT MAP(
------
------                    tx_in_data   => out_data_arb,
------                    tx_in_ctrl   => out_ctrl_arb,
------                    tx_in_wr     => out_wr_arb,
------                    rx_in_data   => out_data_classifier,
------                    rx_in_ctrl   => out_ctrl_classifier,
------                    rx_in_wr     => out_wr_classifier,
------
------                    out_data      =>      out_data_hello,
------                    out_ctrl      => out_ctrl_hello,
------                    out_wr        => out_wr_hello,
------          --      SIGNAL out_cnt : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
------          --      SIGNAL cnt_enable :OUT STD_LOGIC;
------                    out_rdy     =>in_rdy_2,
------                    in_rdy      =>in_rdy_hello,
------                    reset      => reset ,
------                    clk        => clk
------  );
------  ----------------------------------------
--              int2ext_top_Inst :   int2ext_top
--              GENERIC MAP(DATA_WIDTH => 64,
--                              CTRL_WIDTH  => 8)
--      PORT MAP(
--
--               in_data => out_data_classifier,
--          in_ctrl => out_ctrl_classifier,
--       in_wr => out_wr_classifier,
--               in_rdy  => in_rdy_int,
--
--               out_data  =>out_data_int,
--               out_ctrl  =>out_ctrl_int,
--               out_wr  => out_wr_int,
--               out_rdy  =>in_rdy_4,
----                    out_data => out_data,
----                    out_ctrl => out_ctrl,
----                    out_wr => out_wr,
----                    out_rdy =>  out_rdy ,
--               en =>dest_i(4),
--               reset => reset ,
--               clk    =>clk
--
--      );
----
--      -------- Classifier Arbiter -----------
         classifier_arbiter_Inst : classifier_arbiter
        GENERIC MAP(DATA_WIDTH => 64,
                                CTRL_WIDTH  => 8)
        PORT MAP(
 
         out_data => out_data_arb,
         out_ctrl =>out_ctrl_arb,
     out_wr =>out_wr_arb,
         out_rdy =>out_rdy_arb,---this is input from the next mudlue
 
          in_data_0 =>out_data_arp,
          in_ctrl_0 =>out_ctrl_arp,
     in_wr_0 => '0',--out_wr_arp,--out_wr_arp,
          in_rdy_0 =>in_rdy_0,
 
         in_data_1 =>(others=>'0'),
         in_ctrl_1 =>(others=>'0'),
    in_wr_1 => '0',
         in_rdy_1 =>open,
 
         in_data_2 =>out_data_hello,
         in_ctrl_2 =>out_ctrl_hello,
     in_wr_2 => '0',--out_wr_hello,--out_wr_balance,
          in_rdy_2 =>in_rdy_2,
 
         in_data_3 =>out_data_router,
         in_ctrl_3 =>out_ctrl_router,
    in_wr_3 => out_wr_router,--out_wr_router,--out_wr_router,
         in_rdy_3 =>in_rdy_3,
 
         in_data_4 =>out_data_int,
         in_ctrl_4 =>out_ctrl_int,
    in_wr_4 => out_wr_int,--out_wr_balance,
         in_rdy_4 =>in_rdy_4,
 
         in_data_5 =>out_data_pass,
         in_ctrl_5 =>out_ctrl_pass,
    in_wr_5 => out_wr_pass,
         in_rdy_5 =>in_rdy_5,
 
 
 
          in_data_6 =>out_data_balance,
          in_ctrl_6 =>out_ctrl_balance,
     in_wr_6 => out_wr_balance,
          in_rdy_6 =>in_rdy_1,
 
 
 
--               in_data_6 =>out_data_classifier,
--        in_ctrl_6 =>out_ctrl_classifier,
--     in_wr_6 => out_wr_classifier,
--        in_rdy_6 =>in_rdy_1,
 
         in_data_7 =>(others=>'0'),
         in_ctrl_7 =>(others=>'0'),
    in_wr_7 => '0',
         in_rdy_7 =>open,
 
     reset => reset,
     clk   => clk
 
        );
 
 
    out_data <= out_data_arb;
         out_ctrl <=out_ctrl_arb;
    out_wr <=out_wr_arb;
         out_rdy_arb <= out_rdy ;---this is input from the next mudlue
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
 
        END behavior;

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[/] [loadbalancer/] [trunk/] [balancer_top.vhd.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`-------------------------------------------`
2			`LIBRARY IEEE;`
3			`USE IEEE.STD_LOGIC_1164.ALL;`
4			`-------------------------------`
5
6			`ENTITY balancer_top IS`
7			`GENERIC( DATA_WIDTH :INTEGER := 64;`
8			`CTRL_WIDTH :INTEGER := 8);`
9			`PORT(`
10
11			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
12			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
13			`SIGNAL in_wr :IN STD_LOGIC;`
14			`SIGNAL in_rdy : OUT STD_LOGIC;`
15
16			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
17			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
18			`SIGNAL out_wr : OUT STD_LOGIC;`
19			`SIGNAL out_rdy : IN STD_LOGIC;`
20			`SIGNAL dest_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
21			`SIGNAL reset :IN STD_LOGIC;`
22			`SIGNAL clk :IN STD_LOGIC`
23			`);`
24			`END ENTITY;`
25
26			`ARCHITECTURE behavior OF balancer_top IS`
27			`-----------------------------------------------------------------------------------`
28			`-----------------------------------------------------------------------------------`
29			`-----------------------------------------------------------------------------------`
30			`COMPONENT int2ext_top IS`
31			`GENERIC(DATA_WIDTH :INTEGER := 64;`
32			`CTRL_WIDTH :INTEGER := 8);`
33			`PORT(`
34
35			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
36			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
37			`SIGNAL in_wr :IN STD_LOGIC;`
38			`SIGNAL in_rdy : OUT STD_LOGIC;`
39
40			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
41			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
42			`SIGNAL out_wr : OUT STD_LOGIC;`
43			`SIGNAL out_rdy : IN STD_LOGIC;`
44
45			`SIGNAL en : IN STD_LOGIC;`
46
47			`SIGNAL reset :IN STD_LOGIC;`
48			`SIGNAL clk :IN STD_LOGIC`
49
50			`);`
51			`END COMPONENT int2ext_top;`
52			`--`
53			`-- COMPONENT hello_pkt IS`
54			`-- GENERIC(DATA_WIDTH :INTEGER := 64;`
55			`-- CTRL_WIDTH :INTEGER := 8);`
56			`-- PORT(`
57			`--`
58			`-- SIGNAL tx_in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
59			`-- SIGNAL tx_in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
60			`-- SIGNAL tx_in_wr : IN STD_LOGIC;`
61			`-- SIGNAL rx_in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
62			`-- SIGNAL rx_in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
63			`-- SIGNAL rx_in_wr : IN STD_LOGIC;`
64			`--`
65			`-- SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
66			`-- SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
67			`-- SIGNAL out_wr : OUT STD_LOGIC;`
68			`-- -- SIGNAL out_cnt : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
69			`-- -- SIGNAL cnt_enable :OUT STD_LOGIC;`
70			`-- SIGNAL out_rdy : IN STD_LOGIC;`
71			`-- SIGNAL in_rdy : OUT STD_LOGIC;`
72			`-- SIGNAL reset : IN STD_LOGIC;`
73			`-- SIGNAL clk : IN STD_LOGIC`
74			`-- );`
75			`-- END COMPONENT hello_pkt;`
76			`--------------------- Classifier Component------------`
77			`COMPONENT classifier IS`
78			`GENERIC(DATA_WIDTH :INTEGER := 64;`
79			`CTRL_WIDTH :INTEGER := 8);`
80			`PORT(`
81
82			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
83			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
84			`SIGNAL in_wr :IN STD_LOGIC;`
85			`SIGNAL in_rdy : OUT STD_LOGIC;`
86
87			`SIGNAL out_data :OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
88			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
89			`SIGNAL out_wr : OUT STD_LOGIC;`
90			`SIGNAL out_rdy : IN STD_LOGIC;`
91			`SIGNAL dest : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
92			`SIGNAL reset :IN STD_LOGIC;`
93			`SIGNAL clk :IN STD_LOGIC`
94			`);`
95			`END COMPONENT classifier;`
96			`------------End Classifier Component`
97			`-------- Classifier Arbiter -----------`
98			`COMPONENT classifier_arbiter IS`
99			`GENERIC(DATA_WIDTH :INTEGER := 64;`
100			`CTRL_WIDTH :INTEGER := 8);`
101			`PORT(`
102
103			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
104			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
105			`SIGNAL out_wr : OUT STD_LOGIC;`
106			`SIGNAL out_rdy : IN STD_LOGIC;`
107
108			`SIGNAL in_data_0 :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
109			`SIGNAL in_ctrl_0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
110			`SIGNAL in_wr_0 :IN STD_LOGIC;`
111			`SIGNAL in_rdy_0 : OUT STD_LOGIC;`
112
113			`SIGNAL in_data_1 :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
114			`SIGNAL in_ctrl_1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
115			`SIGNAL in_wr_1 :IN STD_LOGIC;`
116			`SIGNAL in_rdy_1 : OUT STD_LOGIC;`
117
118			`SIGNAL in_data_2 :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
119			`SIGNAL in_ctrl_2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
120			`SIGNAL in_wr_2 :IN STD_LOGIC;`
121			`SIGNAL in_rdy_2 : OUT STD_LOGIC;`
122
123			`SIGNAL in_data_3 :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
124			`SIGNAL in_ctrl_3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
125			`SIGNAL in_wr_3 :IN STD_LOGIC;`
126			`SIGNAL in_rdy_3 : OUT STD_LOGIC;`
127
128			`SIGNAL in_data_4 :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
129			`SIGNAL in_ctrl_4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
130			`SIGNAL in_wr_4 :IN STD_LOGIC;`
131			`SIGNAL in_rdy_4 : OUT STD_LOGIC;`
132
133			`SIGNAL in_data_5 :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
134			`SIGNAL in_ctrl_5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
135			`SIGNAL in_wr_5 :IN STD_LOGIC;`
136			`SIGNAL in_rdy_5 : OUT STD_LOGIC;`
137
138			`SIGNAL in_data_6 :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
139			`SIGNAL in_ctrl_6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
140			`SIGNAL in_wr_6 :IN STD_LOGIC;`
141			`SIGNAL in_rdy_6 : OUT STD_LOGIC;`
142
143			`SIGNAL in_data_7 :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
144			`SIGNAL in_ctrl_7 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
145			`SIGNAL in_wr_7 :IN STD_LOGIC;`
146			`SIGNAL in_rdy_7 : OUT STD_LOGIC;`
147
148			`SIGNAL reset :IN STD_LOGIC;`
149			`SIGNAL clk :IN STD_LOGIC`
150
151			`);`
152			`END COMPONENT classifier_arbiter;`
153			`----------------------------Arp Top Component`
154			`COMPONENT arp_top IS`
155			`GENERIC(DATA_WIDTH :INTEGER := 64;`
156			`CTRL_WIDTH :INTEGER := 8);`
157			`PORT(`
158			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
159			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
160			`SIGNAL in_wr :IN STD_LOGIC;`
161			`SIGNAL in_rdy : OUT STD_LOGIC;`
162
163			`SIGNAL out_data :OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
164			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
165			`SIGNAL out_wr : OUT STD_LOGIC;`
166			`SIGNAL out_rdy : IN STD_LOGIC;`
167
168
169			`--- Misc`
170			`SIGNAL en : IN STD_LOGIC;`
171			`SIGNAL reset :IN STD_LOGIC;`
172			`SIGNAL clk :IN STD_LOGIC`
173			`);`
174			`END COMPONENT arp_top;`
175			`-- --------------- Balance Component-----`
176			`COMPONENT balance_top IS`
177			`GENERIC(DATA_WIDTH :INTEGER := 64;`
178			`CTRL_WIDTH :INTEGER := 8);`
179			`PORT(`
180
181			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
182			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
183			`SIGNAL in_wr :IN STD_LOGIC;`
184			`SIGNAL in_rdy : OUT STD_LOGIC;`
185
186			`----------------`
187			`SIGNAL in_next_mac :IN STD_LOGIC_VECTOR(47 DOWNTO 0);`
188			`SIGNAL in_exit_port :IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
189			`SIGNAL in_next_mac_rdy : IN STD_LOGIC;`
190			`SIGNAL out_rd_next_mac : OUT STD_LOGIC;`
191			`SIGNAL key : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
192			`-------------------`
193			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
194			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
195			`SIGNAL out_wr : OUT STD_LOGIC;`
196			`SIGNAL out_rdy : IN STD_LOGIC;`
197			`SIGNAL en :IN STD_LOGIC;`
198			`SIGNAL reset :IN STD_LOGIC;`
199			`SIGNAL clk :IN STD_LOGIC`
200
201			`);`
202			`END COMPONENT balance_top;`
203
204			`-- --------------- Router Component-----`
205			`COMPONENT router IS`
206			`GENERIC(DATA_WIDTH :INTEGER := 64;`
207			`CTRL_WIDTH :INTEGER := 8);`
208			`PORT(`
209
210			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
211			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
212			`SIGNAL in_wr :IN STD_LOGIC;`
213			`SIGNAL in_rdy : OUT STD_LOGIC;`
214
215			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
216			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
217			`SIGNAL out_wr : OUT STD_LOGIC;`
218			`SIGNAL out_rdy : IN STD_LOGIC;`
219
220			`SIGNAL en : IN STD_LOGIC;`
221			`SIGNAL reset :IN STD_LOGIC;`
222			`SIGNAL clk :IN STD_LOGIC`
223
224			`);`
225			`END COMPONENT;`
226			`-------------Pass Component-----`
227			`COMPONENT pass IS`
228			`GENERIC(DATA_WIDTH :INTEGER := 64;`
229			`CTRL_WIDTH :INTEGER := 8);`
230			`PORT(`
231
232			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
233			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
234			`SIGNAL in_wr :IN STD_LOGIC;`
235			`SIGNAL in_rdy : OUT STD_LOGIC;`
236
237			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
238			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
239			`SIGNAL out_wr : OUT STD_LOGIC;`
240			`SIGNAL out_rdy : IN STD_LOGIC;`
241			`SIGNAL en : IN STD_LOGIC;`
242			`SIGNAL reset :IN STD_LOGIC;`
243			`SIGNAL clk :IN STD_LOGIC`
244
245			`);`
246			`END COMPONENT pass;`
247			`---------------------------------------------------------------------------------------`
248			`-------------Manager Component-----`
249			`COMPONENT manager IS`
250			`GENERIC(DATA_WIDTH :INTEGER := 64;`
251			`CTRL_WIDTH :INTEGER := 8);`
252			`PORT(`
253
254			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
255			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
256			`SIGNAL in_wr :IN STD_LOGIC;`
257			`SIGNAL in_rdy : OUT STD_LOGIC;`
258			`SIGNAL in_rd: IN std_logic;`
259			`SIGNAL in_key : IN STD_LOGIC_VECTOR(11 DOWNTO 0);`
260			`SIGNAL out_mac: OUT std_logic_VECTOR(47 downto 0);`
261			`SIGNAL out_port: OUT std_logic_VECTOR(7 downto 0);`
262			`SIGNAL out_rd_rdy: OUT std_logic ;`
263			`SIGNAL out_rdy : IN STD_LOGIC;`
264			`SIGNAL reset :IN STD_LOGIC;`
265			`SIGNAL clk :IN STD_LOGIC`
266
267			`);`
268			`END COMPONENT manager;`
269			`---------------------------------------------------------------------------------------`
270			`-------------------------------------------------------------------------------------`
271			`SIGNAL out_data_classifier : STD_LOGIC_VECTOR(63 DOWNTO 0);`
272			`SIGNAL out_ctrl_classifier : STD_LOGIC_VECTOR(7 DOWNTO 0);`
273			`SIGNAL out_wr_classifier : STD_LOGIC;`
274			`SIGNAL out_rdy_classifier : STD_LOGIC;`
275			`SIGNAL dest_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
276			`-------------------------------------------------------------------------------------`
277			`SIGNAL out_data_arp : STD_LOGIC_VECTOR(63 DOWNTO 0);`
278			`SIGNAL out_ctrl_arp : STD_LOGIC_VECTOR(7 DOWNTO 0);`
279			`SIGNAL out_wr_arp : STD_LOGIC;`
280			`SIGNAL in_rdy_arp : STD_LOGIC;`
281
282			`-------------------------------------------------------------------------------------`
283			`SIGNAL out_data_balance : STD_LOGIC_VECTOR(63 DOWNTO 0);`
284			`SIGNAL out_ctrl_balance : STD_LOGIC_VECTOR(7 DOWNTO 0);`
285			`SIGNAL out_wr_balance : STD_LOGIC;`
286			`SIGNAL in_rdy_balance : STD_LOGIC;`
287			`-------------------------------------------------------------------------------------`
288			`SIGNAL out_data_router : STD_LOGIC_VECTOR(63 DOWNTO 0);`
289			`SIGNAL out_ctrl_router : STD_LOGIC_VECTOR(7 DOWNTO 0);`
290			`SIGNAL out_wr_router : STD_LOGIC;`
291			`SIGNAL in_rdy_router : STD_LOGIC;`
292			`-----------------------------------------------------------------------------------`
293			`SIGNAL out_data_hello : STD_LOGIC_VECTOR(63 DOWNTO 0);`
294			`SIGNAL out_ctrl_hello : STD_LOGIC_VECTOR(7 DOWNTO 0);`
295			`SIGNAL out_wr_hello : STD_LOGIC;`
296			`SIGNAL in_rdy_hello : STD_LOGIC;`
297			`-------------------------------------------------------------------------------------`
298			`SIGNAL out_data_pass : STD_LOGIC_VECTOR(63 DOWNTO 0);`
299			`SIGNAL out_ctrl_pass : STD_LOGIC_VECTOR(7 DOWNTO 0);`
300			`SIGNAL out_wr_pass : STD_LOGIC;`
301			`SIGNAL in_rdy_pass : STD_LOGIC;`
302			`SIGNAL in_rdy_0 : STD_LOGIC;`
303			`SIGNAL in_rdy_1 : STD_LOGIC;`
304			`SIGNAL in_rdy_2 : STD_LOGIC;`
305			`SIGNAL in_rdy_3 : STD_LOGIC;`
306			`SIGNAL in_rdy_4 : STD_LOGIC;`
307			`SIGNAL in_rdy_5 : STD_LOGIC;`
308			`----------------------------------`
309			`SIGNAL in_rdy_manger : STD_LOGIC;`
310			`SIGNAL in_rd_manger: std_logic;`
311			`SIGNAL out_mac_manger: std_logic_VECTOR(47 downto 0);`
312			`SIGNAL out_port_manger: std_logic_VECTOR(7 downto 0);`
313			`SIGNAL key: std_logic_VECTOR(11 downto 0);`
314			`SIGNAL out_rd_rdy_manger: std_logic ;`
315			`----------------------------`
316
317			`SIGNAL out_data_arb : STD_LOGIC_VECTOR(63 DOWNTO 0);`
318			`SIGNAL out_ctrl_arb : STD_LOGIC_VECTOR(7 DOWNTO 0);`
319			`SIGNAL out_wr_arb : STD_LOGIC;`
320			`SIGNAL out_rdy_arb : STD_LOGIC;`
321			`------------------`
322			`SIGNAL out_data_int : STD_LOGIC_VECTOR(63 DOWNTO 0);`
323			`SIGNAL out_ctrl_int : STD_LOGIC_VECTOR(7 DOWNTO 0);`
324			`SIGNAL out_wr_int : STD_LOGIC;`
325			`SIGNAL in_rdy_int : STD_LOGIC;`
326
327			`--`
328			`BEGIN`
329			`---------------------------------------------------------------------------------------`
330			`---------------------------------------------------------------------------------------`
331			`---------------------------------------------------------------------------------------`
332			`--`
333			`out_rdy_classifier <= in_rdy_pass ;--AND in_rdy_int and in_rdy_balance AND in_rdy_router ;--AND in_rdy_arp;-- AND in_rdy_int AND in_rdy_router;`
334
335			`--------------------- Classifier Port Map------------`
336
337			`classifier_Inst : classifier`
338			`GENERIC MAP(DATA_WIDTH => 64,`
339			`CTRL_WIDTH => 8)`
340			`PORT MAP(`
341			`--Input`
342
343			`in_data => in_data,`
344			`in_ctrl => in_ctrl,`
345			`in_wr => in_wr,`
346			`in_rdy => in_rdy,--this is to be connected with out_rdy from the pervious module this is out put port`
347			`---Output`
348
349			`-- out_data => out_data,`
350			`-- out_ctrl => out_ctrl,`
351			`-- out_wr => out_wr,`
352			`-- out_rdy => out_rdy ,`
353			`out_data => out_data_classifier,`
354			`out_ctrl => out_ctrl_classifier,`
355			`out_wr => out_wr_classifier,`
356			`out_rdy =>out_rdy_classifier,-- this is input port`
357			`--- Misc`
358			`dest =>dest_i,`
359			`reset => reset,`
360			`clk => clk`
361			`);`
362
363			`dest_out <= dest_i;`
364			`--------------End Classifier Port Map`
365			`--`
366			`------------------------------Arp Top Component`
367			`-- arp_top_Ins : arp_top`
368			`-- GENERIC MAP(DATA_WIDTH => 64,`
369			`-- CTRL_WIDTH => 8)`
370			`-- PORT MAP(`
371			`-- in_data => out_data_classifier ,`
372			`-- in_ctrl => out_ctrl_classifier,`
373			`-- in_wr => out_wr_classifier,`
374			`-- in_rdy =>in_rdy_arp,`
375			`--`
376			`-- out_data => out_data_arp,`
377			`-- out_ctrl => out_ctrl_arp,`
378			`-- out_wr => out_wr_arp,`
379			`-- out_rdy =>in_rdy_0,`
380			`--`
381			`--`
382			`-- --- Misc`
383			`-- en => dest_i(0),`
384			`-- reset => reset,`
385			`-- clk => clk`
386			`-- );`
387			`--`
388			`------ ---------------Balance Component----`
389
390
391			`balance_Inst : balance_top`
392			`GENERIC MAP(DATA_WIDTH => 64,`
393			`CTRL_WIDTH => 8)`
394			`PORT MAP(`
395
396			`in_data => out_data_classifier,`
397			`in_ctrl => out_ctrl_classifier,`
398			`in_wr => out_wr_classifier,`
399			`in_rdy => in_rdy_balance,`
400
401			`out_data => out_data_balance,`
402			`out_ctrl => out_ctrl_balance,`
403			`out_wr => out_wr_balance,`
404			`out_rdy =>in_rdy_1,`
405
406			`in_next_mac =>out_mac_manger,`
407			`in_exit_port => out_port_manger,`
408			`out_rd_next_mac => in_rd_manger,`
409			`in_next_mac_rdy =>out_rd_rdy_manger,`
410			`key => open,`
411
412
413			`-- out_data => out_data,`
414			`-- out_ctrl => out_ctrl,`
415			`-- out_wr => out_wr,`
416			`-- out_rdy => out_rdy ,`
417
418			`en => dest_i(1),`
419			`reset => reset,`
420			`clk => clk`
421
422			`);`
423			`------ ---------------Balance Component-----`
424			`router_Inst : router`
425			`GENERIC MAP(DATA_WIDTH => 64,`
426			`CTRL_WIDTH => 8)`
427			`PORT MAP(`
428
429			`in_data => out_data_classifier,`
430			`in_ctrl => out_ctrl_classifier,`
431			`in_wr => out_wr_classifier,`
432			`in_rdy => in_rdy_router,`
433
434			`out_data => out_data_router,`
435			`out_ctrl => out_ctrl_router,`
436			`out_wr => out_wr_router,`
437			`out_rdy =>in_rdy_3,`
438			`en => dest_i(2),`
439			`reset => reset,`
440			`clk => clk`
441
442			`);`
443			`-----------------Pass Component-----`
444			`pass_Inst : pass`
445			`GENERIC MAP(DATA_WIDTH => 64,`
446			`CTRL_WIDTH => 8)`
447			`PORT MAP(`
448
449			`in_data => out_data_classifier,`
450			`in_ctrl => out_ctrl_classifier,`
451			`in_wr => out_wr_classifier,`
452			`in_rdy => in_rdy_pass,`
453
454			`out_data => out_data_pass,`
455			`out_ctrl => out_ctrl_pass,`
456			`out_wr => out_wr_pass,`
457			`out_rdy =>in_rdy_5,`
458			`-- out_data => out_data,`
459			`-- out_ctrl => out_ctrl,`
460			`-- out_wr => out_wr,`
461			`-- out_rdy => out_rdy ,`
462			`en =>dest_i(7),`
463			`reset => reset,`
464			`clk => clk`
465
466			`);`
467			`-- ----------------------------------------------`
468			`------ ----------------Pass Component-----`
469			`------`
470			`------`
471			`manager_Inst : manager`
472			`GENERIC MAP(DATA_WIDTH => 64,`
473			`CTRL_WIDTH => 8)`
474			`PORT MAP(`
475
476			`in_data => out_data_classifier,`
477			`in_ctrl => out_ctrl_classifier,`
478			`in_wr => out_wr_classifier,`
479			`in_rdy => in_rdy_manger,`
480
481			`in_rd => in_rd_manger,`
482			`in_key => (OTHERS=>'0'),`
483			`out_mac => out_mac_manger,`
484			`out_port=>out_port_manger,`
485			`out_rd_rdy => out_rd_rdy_manger,`
486			`out_rdy =>'1',`
487
488			`reset => reset,`
489			`clk => clk`
490
491			`);`
492			`--------------------------Hello----`
493			`------ Hello_Ist : hello_pkt`
494			`------ GENERIC MAP(DATA_WIDTH => 64,`
495			`------ CTRL_WIDTH => 8)`
496			`------ PORT MAP(`
497			`------`
498			`------ tx_in_data => out_data_arb,`
499			`------ tx_in_ctrl => out_ctrl_arb,`
500			`------ tx_in_wr => out_wr_arb,`
501			`------ rx_in_data => out_data_classifier,`
502			`------ rx_in_ctrl => out_ctrl_classifier,`
503			`------ rx_in_wr => out_wr_classifier,`
504			`------`
505			`------ out_data => out_data_hello,`
506			`------ out_ctrl => out_ctrl_hello,`
507			`------ out_wr => out_wr_hello,`
508			`------ -- SIGNAL out_cnt : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
509			`------ -- SIGNAL cnt_enable :OUT STD_LOGIC;`
510			`------ out_rdy =>in_rdy_2,`
511			`------ in_rdy =>in_rdy_hello,`
512			`------ reset => reset ,`
513			`------ clk => clk`
514			`------ );`
515			`------ ----------------------------------------`
516			`-- int2ext_top_Inst : int2ext_top`
517			`-- GENERIC MAP(DATA_WIDTH => 64,`
518			`-- CTRL_WIDTH => 8)`
519			`-- PORT MAP(`
520			`--`
521			`-- in_data => out_data_classifier,`
522			`-- in_ctrl => out_ctrl_classifier,`
523			`-- in_wr => out_wr_classifier,`
524			`-- in_rdy => in_rdy_int,`
525			`--`
526			`-- out_data =>out_data_int,`
527			`-- out_ctrl =>out_ctrl_int,`
528			`-- out_wr => out_wr_int,`
529			`-- out_rdy =>in_rdy_4,`
530			`---- out_data => out_data,`
531			`---- out_ctrl => out_ctrl,`
532			`---- out_wr => out_wr,`
533			`---- out_rdy => out_rdy ,`
534			`-- en =>dest_i(4),`
535			`-- reset => reset ,`
536			`-- clk =>clk`
537			`--`
538			`-- );`
539			`----`
540			`-- -------- Classifier Arbiter -----------`
541			`classifier_arbiter_Inst : classifier_arbiter`
542			`GENERIC MAP(DATA_WIDTH => 64,`
543			`CTRL_WIDTH => 8)`
544			`PORT MAP(`
545
546			`out_data => out_data_arb,`
547			`out_ctrl =>out_ctrl_arb,`
548			`out_wr =>out_wr_arb,`
549			`out_rdy =>out_rdy_arb,---this is input from the next mudlue`
550
551			`in_data_0 =>out_data_arp,`
552			`in_ctrl_0 =>out_ctrl_arp,`
553			`in_wr_0 => '0',--out_wr_arp,--out_wr_arp,`
554			`in_rdy_0 =>in_rdy_0,`
555
556			`in_data_1 =>(others=>'0'),`
557			`in_ctrl_1 =>(others=>'0'),`
558			`in_wr_1 => '0',`
559			`in_rdy_1 =>open,`
560
561			`in_data_2 =>out_data_hello,`
562			`in_ctrl_2 =>out_ctrl_hello,`
563			`in_wr_2 => '0',--out_wr_hello,--out_wr_balance,`
564			`in_rdy_2 =>in_rdy_2,`
565
566			`in_data_3 =>out_data_router,`
567			`in_ctrl_3 =>out_ctrl_router,`
568			`in_wr_3 => out_wr_router,--out_wr_router,--out_wr_router,`
569			`in_rdy_3 =>in_rdy_3,`
570
571			`in_data_4 =>out_data_int,`
572			`in_ctrl_4 =>out_ctrl_int,`
573			`in_wr_4 => out_wr_int,--out_wr_balance,`
574			`in_rdy_4 =>in_rdy_4,`
575
576			`in_data_5 =>out_data_pass,`
577			`in_ctrl_5 =>out_ctrl_pass,`
578			`in_wr_5 => out_wr_pass,`
579			`in_rdy_5 =>in_rdy_5,`
580
581
582
583			`in_data_6 =>out_data_balance,`
584			`in_ctrl_6 =>out_ctrl_balance,`
585			`in_wr_6 => out_wr_balance,`
586			`in_rdy_6 =>in_rdy_1,`
587
588
589
590			`-- in_data_6 =>out_data_classifier,`
591			`-- in_ctrl_6 =>out_ctrl_classifier,`
592			`-- in_wr_6 => out_wr_classifier,`
593			`-- in_rdy_6 =>in_rdy_1,`
594
595			`in_data_7 =>(others=>'0'),`
596			`in_ctrl_7 =>(others=>'0'),`
597			`in_wr_7 => '0',`
598			`in_rdy_7 =>open,`
599
600			`reset => reset,`
601			`clk => clk`
602
603			`);`
604
605
606			`out_data <= out_data_arb;`
607			`out_ctrl <=out_ctrl_arb;`
608			`out_wr <=out_wr_arb;`
609			`out_rdy_arb <= out_rdy ;---this is input from the next mudlue`
610			`---------------------------------------------------------------------------------------`
611			`---------------------------------------------------------------------------------------`
612			`---------------------------------------------------------------------------------------`
613
614			`END behavior;`