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URL https://opencores.org/ocsvn/loadbalancer/loadbalancer/trunk

Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [db/] [LB.fnsim.qmsg] - Blame information for rev 2

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1 2 atalla 
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
2 
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 20:16:18 2010 " "Info: Processing started: Sun Jan 10 20:16:18 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
3 
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LB -c LB --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LB -c LB --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
4 
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "dst_mac ethernet_parser.v(57) " "Warning (10236): Verilog HDL Implicit Net warning at ethernet_parser.v(57): created implicit net for \"dst_mac\"" {  } { { "ethernet_parser.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser.v" 57 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
5 
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "src_mac ethernet_parser.v(58) " "Warning (10236): Verilog HDL Implicit Net warning at ethernet_parser.v(58): created implicit net for \"src_mac\"" {  } { { "ethernet_parser.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser.v" 58 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
6 
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "ethertype ethernet_parser.v(59) " "Warning (10236): Verilog HDL Implicit Net warning at ethernet_parser.v(59): created implicit net for \"ethertype\"" {  } { { "ethernet_parser.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser.v" 59 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
7 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ethernet_parser.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ethernet_parser.v" { { "Info" "ISGN_ENTITY_NAME" "1 ethernet_parser " "Info: Found entity 1: ethernet_parser" {  } { { "ethernet_parser.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
8 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ethernet_parser_32bit.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ethernet_parser_32bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 ethernet_parser_32bit " "Info: Found entity 1: ethernet_parser_32bit" {  } { { "ethernet_parser_32bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_32bit.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
9 
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "2 ethernet_parser_64bit.v(59) " "Warning (10229): Verilog HDL Expression warning at ethernet_parser_64bit.v(59): truncated literal to match 2 bits" {  } { { "ethernet_parser_64bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_64bit.v" 59 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
10 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ethernet_parser_64bit.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ethernet_parser_64bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 ethernet_parser_64bit " "Info: Found entity 1: ethernet_parser_64bit" {  } { { "ethernet_parser_64bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_64bit.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
11 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "classifier_arbiter/classifier_arbiter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file classifier_arbiter/classifier_arbiter.v" { { "Info" "ISGN_ENTITY_NAME" "1 classifier_arbiter " "Info: Found entity 1: classifier_arbiter" {  } { { "classifier_arbiter/classifier_arbiter.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/classifier_arbiter/classifier_arbiter.v" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
12 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PASS/pass.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PASS/pass.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pass-behavior " "Info: Found design unit 1: pass-behavior" {  } { { "PASS/pass.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/PASS/pass.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pass " "Info: Found entity 1: pass" {  } { { "PASS/pass.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/PASS/pass.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
13 
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "NEARLY_FULL nearly_full small_fifo.v(18) " "Info (10281): Verilog HDL Declaration information at small_fifo.v(18): object \"NEARLY_FULL\" differs only in case from object \"nearly_full\" in the same scope" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 18 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
14 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "small_fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file small_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 small_fifo " "Info: Found entity 1: small_fifo" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
15 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TABLE/Aging_Timer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TABLE/Aging_Timer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Aging_Timer-beh " "Info: Found design unit 1: Aging_Timer-beh" {  } { { "TABLE/Aging_Timer.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/Aging_Timer.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 Aging_Timer " "Info: Found entity 1: Aging_Timer" {  } { { "TABLE/Aging_Timer.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/Aging_Timer.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
16 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TABLE/div_binary.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TABLE/div_binary.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div_binary-Behavioral " "Info: Found design unit 1: div_binary-Behavioral" {  } { { "TABLE/div_binary.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/div_binary.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 div_binary " "Info: Found entity 1: div_binary" {  } { { "TABLE/div_binary.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/div_binary.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
17 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TABLE/mac_ram_table.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TABLE/mac_ram_table.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mac_ram_table-Behavioral " "Info: Found design unit 1: mac_ram_table-Behavioral" {  } { { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 33 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 mac_ram_table " "Info: Found entity 1: mac_ram_table" {  } { { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
18 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TABLE/manager.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TABLE/manager.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 manager-behavior " "Info: Found design unit 1: manager-behavior" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 39 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 manager " "Info: Found entity 1: manager" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
19 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TABLE/ram_256x48.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TABLE/ram_256x48.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram_256x48-rtl " "Info: Found design unit 1: ram_256x48-rtl" {  } { { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ram_256x48 " "Info: Found entity 1: ram_256x48" {  } { { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
20 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TABLE/table.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TABLE/table.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 table-Behavioral " "Info: Found design unit 1: table-Behavioral" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 31 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 table " "Info: Found entity 1: table" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
21 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TABLE/valid_address.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TABLE/valid_address.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 valid_address-Behavioral " "Info: Found design unit 1: valid_address-Behavioral" {  } { { "TABLE/valid_address.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/valid_address.vhd" 40 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 valid_address " "Info: Found entity 1: valid_address" {  } { { "TABLE/valid_address.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/valid_address.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
22 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Router/router.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Router/router.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 router-behavior " "Info: Found design unit 1: router-behavior" {  } { { "Router/router.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Router/router.vhd" 33 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 router " "Info: Found entity 1: router" {  } { { "Router/router.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Router/router.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
23 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int2ext/int2ext.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int2ext/int2ext.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int2ext-behavior " "Info: Found design unit 1: int2ext-behavior" {  } { { "int2ext/int2ext.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/int2ext/int2ext.vhd" 31 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 int2ext " "Info: Found entity 1: int2ext" {  } { { "int2ext/int2ext.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/int2ext/int2ext.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
24 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int2ext/int2ext_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int2ext/int2ext_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int2ext_top-behavior " "Info: Found design unit 1: int2ext_top-behavior" {  } { { "int2ext/int2ext_top.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/int2ext/int2ext_top.vhd" 32 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 int2ext_top " "Info: Found entity 1: int2ext_top" {  } { { "int2ext/int2ext_top.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/int2ext/int2ext_top.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
25 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int2ext/vlan2ext.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int2ext/vlan2ext.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vlan2ext-behavior " "Info: Found design unit 1: vlan2ext-behavior" {  } { { "int2ext/vlan2ext.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/int2ext/vlan2ext.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 vlan2ext " "Info: Found entity 1: vlan2ext" {  } { { "int2ext/vlan2ext.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/int2ext/vlan2ext.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
26 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Balance/balance.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Balance/balance.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 balance-behavior " "Info: Found design unit 1: balance-behavior" {  } { { "Balance/balance.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Balance/balance.vhd" 36 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 balance " "Info: Found entity 1: balance" {  } { { "Balance/balance.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Balance/balance.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
27 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Balance/balance_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Balance/balance_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 balance_top-behavior " "Info: Found design unit 1: balance_top-behavior" {  } { { "Balance/balance_top.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Balance/balance_top.vhd" 36 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 balance_top " "Info: Found entity 1: balance_top" {  } { { "Balance/balance_top.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Balance/balance_top.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
28 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Balance/hash.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Balance/hash.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hash-behavioral " "Info: Found design unit 1: hash-behavioral" {  } { { "Balance/hash.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Balance/hash.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 hash " "Info: Found entity 1: hash" {  } { { "Balance/hash.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Balance/hash.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
29 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Balance/n_mac.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Balance/n_mac.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 n_mac-behavior " "Info: Found design unit 1: n_mac-behavior" {  } { { "Balance/n_mac.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Balance/n_mac.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 n_mac " "Info: Found entity 1: n_mac" {  } { { "Balance/n_mac.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Balance/n_mac.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
30 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ARP/arp_parser.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ARP/arp_parser.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 arp_parser-behavior " "Info: Found design unit 1: arp_parser-behavior" {  } { { "ARP/arp_parser.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ARP/arp_parser.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 arp_parser " "Info: Found entity 1: arp_parser" {  } { { "ARP/arp_parser.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ARP/arp_parser.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
31 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ARP/arp_response.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ARP/arp_response.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 arp_response-behavior " "Info: Found design unit 1: arp_response-behavior" {  } { { "ARP/arp_response.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ARP/arp_response.vhd" 34 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 arp_response " "Info: Found entity 1: arp_response" {  } { { "ARP/arp_response.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ARP/arp_response.vhd" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
32 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ARP/arp_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ARP/arp_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 arp_top-behavior " "Info: Found design unit 1: arp_top-behavior" {  } { { "ARP/arp_top.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ARP/arp_top.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 arp_top " "Info: Found entity 1: arp_top" {  } { { "ARP/arp_top.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ARP/arp_top.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
33 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Classfier/classifier.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Classfier/classifier.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 classifier-behavior " "Info: Found design unit 1: classifier-behavior" {  } { { "Classfier/classifier.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Classfier/classifier.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 classifier " "Info: Found entity 1: classifier" {  } { { "Classfier/classifier.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Classfier/classifier.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
34 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Classfier/open_header.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Classfier/open_header.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 open_header-behavior " "Info: Found design unit 1: open_header-behavior" {  } { { "Classfier/open_header.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Classfier/open_header.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 open_header " "Info: Found entity 1: open_header" {  } { { "Classfier/open_header.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/Classfier/open_header.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
35 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "balancer_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file balancer_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 balancer_top-behavior " "Info: Found design unit 1: balancer_top-behavior" {  } { { "balancer_top.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/balancer_top.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 balancer_top " "Info: Found entity 1: balancer_top" {  } { { "balancer_top.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/balancer_top.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
36 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "config.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file config.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 config " "Info: Found design unit 1: config" {  } { { "config.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/config.vhd" 5 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
37 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LB.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file LB.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 LB " "Info: Found entity 1: LB" {  } { { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
38 
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "2 output_port_lookup.v(177) " "Warning (10229): Verilog HDL Expression warning at output_port_lookup.v(177): truncated literal to match 2 bits" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 177 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
39 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "output_port_lookup.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file output_port_lookup.v" { { "Info" "ISGN_ENTITY_NAME" "1 output_port_lookup " "Info: Found entity 1: output_port_lookup" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
40 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_64bit ethernet_parser_64bit.v(35) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_64bit.v(35): Parameter Declaration in module \"ethernet_parser_64bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_64bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_64bit.v" 35 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
41 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_64bit ethernet_parser_64bit.v(36) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_64bit.v(36): Parameter Declaration in module \"ethernet_parser_64bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_64bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_64bit.v" 36 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
42 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_64bit ethernet_parser_64bit.v(37) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_64bit.v(37): Parameter Declaration in module \"ethernet_parser_64bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_64bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_64bit.v" 37 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
43 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_64bit ethernet_parser_64bit.v(38) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_64bit.v(38): Parameter Declaration in module \"ethernet_parser_64bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_64bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_64bit.v" 38 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
44 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_32bit ethernet_parser_32bit.v(37) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_32bit.v(37): Parameter Declaration in module \"ethernet_parser_32bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_32bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_32bit.v" 37 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
45 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_32bit ethernet_parser_32bit.v(38) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_32bit.v(38): Parameter Declaration in module \"ethernet_parser_32bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_32bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_32bit.v" 38 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
46 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_32bit ethernet_parser_32bit.v(39) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_32bit.v(39): Parameter Declaration in module \"ethernet_parser_32bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_32bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_32bit.v" 39 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
47 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_32bit ethernet_parser_32bit.v(40) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_32bit.v(40): Parameter Declaration in module \"ethernet_parser_32bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_32bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_32bit.v" 40 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
48 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_32bit ethernet_parser_32bit.v(41) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_32bit.v(41): Parameter Declaration in module \"ethernet_parser_32bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_32bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_32bit.v" 41 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
49 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "ethernet_parser_32bit ethernet_parser_32bit.v(42) " "Warning (10222): Verilog HDL Parameter Declaration warning at ethernet_parser_32bit.v(42): Parameter Declaration in module \"ethernet_parser_32bit\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "ethernet_parser_32bit.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/ethernet_parser_32bit.v" 42 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
50 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "classifier_arbiter classifier_arbiter.v(90) " "Warning (10222): Verilog HDL Parameter Declaration warning at classifier_arbiter.v(90): Parameter Declaration in module \"classifier_arbiter\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "classifier_arbiter/classifier_arbiter.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/classifier_arbiter/classifier_arbiter.v" 90 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
51 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "classifier_arbiter classifier_arbiter.v(92) " "Warning (10222): Verilog HDL Parameter Declaration warning at classifier_arbiter.v(92): Parameter Declaration in module \"classifier_arbiter\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "classifier_arbiter/classifier_arbiter.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/classifier_arbiter/classifier_arbiter.v" 92 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
52 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "classifier_arbiter classifier_arbiter.v(93) " "Warning (10222): Verilog HDL Parameter Declaration warning at classifier_arbiter.v(93): Parameter Declaration in module \"classifier_arbiter\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "classifier_arbiter/classifier_arbiter.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/classifier_arbiter/classifier_arbiter.v" 93 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
53 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "classifier_arbiter classifier_arbiter.v(94) " "Warning (10222): Verilog HDL Parameter Declaration warning at classifier_arbiter.v(94): Parameter Declaration in module \"classifier_arbiter\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "classifier_arbiter/classifier_arbiter.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/classifier_arbiter/classifier_arbiter.v" 94 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
54 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "small_fifo small_fifo.v(36) " "Warning (10222): Verilog HDL Parameter Declaration warning at small_fifo.v(36): Parameter Declaration in module \"small_fifo\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 36 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
55 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "output_port_lookup output_port_lookup.v(52) " "Warning (10222): Verilog HDL Parameter Declaration warning at output_port_lookup.v(52): Parameter Declaration in module \"output_port_lookup\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 52 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
56 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "output_port_lookup output_port_lookup.v(53) " "Warning (10222): Verilog HDL Parameter Declaration warning at output_port_lookup.v(53): Parameter Declaration in module \"output_port_lookup\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 53 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
57 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "output_port_lookup output_port_lookup.v(55) " "Warning (10222): Verilog HDL Parameter Declaration warning at output_port_lookup.v(55): Parameter Declaration in module \"output_port_lookup\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 55 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
58 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "output_port_lookup output_port_lookup.v(56) " "Warning (10222): Verilog HDL Parameter Declaration warning at output_port_lookup.v(56): Parameter Declaration in module \"output_port_lookup\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 56 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
59 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "output_port_lookup output_port_lookup.v(57) " "Warning (10222): Verilog HDL Parameter Declaration warning at output_port_lookup.v(57): Parameter Declaration in module \"output_port_lookup\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 57 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
60 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "output_port_lookup output_port_lookup.v(58) " "Warning (10222): Verilog HDL Parameter Declaration warning at output_port_lookup.v(58): Parameter Declaration in module \"output_port_lookup\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 58 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
61 
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "output_port_lookup output_port_lookup.v(59) " "Warning (10222): Verilog HDL Parameter Declaration warning at output_port_lookup.v(59): Parameter Declaration in module \"output_port_lookup\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "output_port_lookup.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/output_port_lookup.v" 59 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "" 0}
62 
{ "Info" "ISGN_START_ELABORATION_TOP" "LB " "Info: Elaborating entity \"LB\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
63 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "manager manager:inst " "Info: Elaborating entity \"manager\" for hierarchy \"manager:inst\"" {  } { { "LB.bdf" "inst" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 368 616 808 560 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
64 
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "rd_en manager.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at manager.vhd(91): used implicit default value for signal \"rd_en\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 91 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0}
65 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "word_cnt manager.vhd(109) " "Warning (10036): Verilog HDL or VHDL warning at manager.vhd(109): object \"word_cnt\" assigned a value but never read" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 109 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
66 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(202) " "Warning (10492): VHDL Process Statement warning at manager.vhd(202): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 202 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
67 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(208) " "Warning (10492): VHDL Process Statement warning at manager.vhd(208): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 208 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
68 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(213) " "Warning (10492): VHDL Process Statement warning at manager.vhd(213): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 213 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
69 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(218) " "Warning (10492): VHDL Process Statement warning at manager.vhd(218): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 218 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
70 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(224) " "Warning (10492): VHDL Process Statement warning at manager.vhd(224): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 224 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
71 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(230) " "Warning (10492): VHDL Process Statement warning at manager.vhd(230): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 230 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
72 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(236) " "Warning (10492): VHDL Process Statement warning at manager.vhd(236): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 236 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
73 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(246) " "Warning (10492): VHDL Process Statement warning at manager.vhd(246): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 246 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
74 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "wr_en manager.vhd(248) " "Warning (10492): VHDL Process Statement warning at manager.vhd(248): signal \"wr_en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 248 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
75 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "done_macs manager.vhd(248) " "Warning (10492): VHDL Process Statement warning at manager.vhd(248): signal \"done_macs\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 248 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
76 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mac_cnt manager.vhd(248) " "Warning (10492): VHDL Process Statement warning at manager.vhd(248): signal \"mac_cnt\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 248 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
77 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "in_rdy manager.vhd(17) " "Warning (10034): Output port \"in_rdy\" at manager.vhd(17) has no driver" {  } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
78 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "table manager:inst\|table:table_Inst " "Info: Elaborating entity \"table\" for hierarchy \"manager:inst\|table:table_Inst\"" {  } { { "TABLE/manager.vhd" "table_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 124 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
79 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "fifo_full table.vhd(98) " "Warning (10036): Verilog HDL or VHDL warning at table.vhd(98): object \"fifo_full\" assigned a value but never read" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 98 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
80 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "fifo_nearly_fulL table.vhd(99) " "Warning (10036): Verilog HDL or VHDL warning at table.vhd(99): object \"fifo_nearly_fulL\" assigned a value but never read" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 99 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
81 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "fifo_empty table.vhd(192) " "Warning (10492): VHDL Process Statement warning at table.vhd(192): signal \"fifo_empty\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 192 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
82 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "weight_i table.vhd(200) " "Warning (10492): VHDL Process Statement warning at table.vhd(200): signal \"weight_i\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 200 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
83 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "fifo_out table.vhd(200) " "Warning (10492): VHDL Process Statement warning at table.vhd(200): signal \"fifo_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 200 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
84 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ram_match table.vhd(212) " "Warning (10492): VHDL Process Statement warning at table.vhd(212): signal \"ram_match\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 212 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
85 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ram_unmatch table.vhd(214) " "Warning (10492): VHDL Process Statement warning at table.vhd(214): signal \"ram_unmatch\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 214 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
86 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ram_match_address table.vhd(220) " "Warning (10492): VHDL Process Statement warning at table.vhd(220): signal \"ram_match_address\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 220 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
87 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "last table.vhd(226) " "Warning (10492): VHDL Process Statement warning at table.vhd(226): signal \"last\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 226 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
88 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "small_fifo manager:inst\|table:table_Inst\|small_fifo:small_fifo_Inst " "Info: Elaborating entity \"small_fifo\" for hierarchy \"manager:inst\|table:table_Inst\|small_fifo:small_fifo_Inst\"" {  } { { "TABLE/table.vhd" "small_fifo_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 115 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
89 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 small_fifo.v(64) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(64): truncated value with size 32 to match size of target (8)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
90 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 small_fifo.v(65) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(65): truncated value with size 32 to match size of target (8)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
91 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 small_fifo.v(66) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(66): truncated value with size 32 to match size of target (9)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
92 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 small_fifo.v(71) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(71): truncated value with size 32 to match size of target (9)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
93 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_ram_table manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst " "Info: Elaborating entity \"mac_ram_table\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\"" {  } { { "TABLE/table.vhd" "ram_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 133 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
94 
{ "Warning" "WVRFX_VHDL_2050_UNCONVERTED" "write_cmd_address mac_ram_table.vhd(365) " "Warning (10812): VHDL warning at mac_ram_table.vhd(365): sensitivity list already contains write_cmd_address" {  } { { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 365 0 0 } }  } 0 10812 "VHDL warning at %2!s!: sensitivity list already contains %1!s!" 0 0 "" 0}
95 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "last_address mac_ram_table.vhd(415) " "Warning (10492): VHDL Process Statement warning at mac_ram_table.vhd(415): signal \"last_address\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 415 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
96 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Aging_Timer manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Aging_Timer:Aging_Timer_Inst " "Info: Elaborating entity \"Aging_Timer\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Aging_Timer:Aging_Timer_Inst\"" {  } { { "TABLE/mac_ram_table.vhd" "Aging_Timer_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 168 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
97 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram_256x48 manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst " "Info: Elaborating entity \"ram_256x48\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\"" {  } { { "TABLE/mac_ram_table.vhd" "ram_256x48_search_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 183 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
98 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "small_fifo manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|small_fifo:WRITE_command_Inst " "Info: Elaborating entity \"small_fifo\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|small_fifo:WRITE_command_Inst\"" {  } { { "TABLE/mac_ram_table.vhd" "WRITE_command_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 290 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
99 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 small_fifo.v(64) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(64): truncated value with size 32 to match size of target (5)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
100 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 small_fifo.v(65) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(65): truncated value with size 32 to match size of target (5)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
101 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 small_fifo.v(66) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(66): truncated value with size 32 to match size of target (6)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
102 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 small_fifo.v(71) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(71): truncated value with size 32 to match size of target (6)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
103 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "small_fifo manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|small_fifo:time_command_Inst " "Info: Elaborating entity \"small_fifo\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|small_fifo:time_command_Inst\"" {  } { { "TABLE/mac_ram_table.vhd" "time_command_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 304 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
104 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 small_fifo.v(64) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(64): truncated value with size 32 to match size of target (2)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
105 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 small_fifo.v(65) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(65): truncated value with size 32 to match size of target (2)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
106 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 small_fifo.v(66) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(66): truncated value with size 32 to match size of target (3)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
107 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 small_fifo.v(71) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(71): truncated value with size 32 to match size of target (3)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
108 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram_256x48 manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst " "Info: Elaborating entity \"ram_256x48\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\"" {  } { { "TABLE/mac_ram_table.vhd" "Aging_Valid_256x48_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 322 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
109 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "valid_address manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst " "Info: Elaborating entity \"valid_address\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\"" {  } { { "TABLE/mac_ram_table.vhd" "valid_address_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 336 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
110 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "empty valid_address.vhd(110) " "Warning (10036): Verilog HDL or VHDL warning at valid_address.vhd(110): object \"empty\" assigned a value but never read" {  } { { "TABLE/valid_address.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/valid_address.vhd" 110 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
111 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "current valid_address.vhd(304) " "Warning (10492): VHDL Process Statement warning at valid_address.vhd(304): signal \"current\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/valid_address.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/valid_address.vhd" 304 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
112 
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "current valid_address.vhd(351) " "Warning (10492): VHDL Process Statement warning at valid_address.vhd(351): signal \"current\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "TABLE/valid_address.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/valid_address.vhd" 351 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
113 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "small_fifo manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|small_fifo:read_command_Inst " "Info: Elaborating entity \"small_fifo\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|small_fifo:read_command_Inst\"" {  } { { "TABLE/valid_address.vhd" "read_command_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/valid_address.vhd" 181 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
114 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 small_fifo.v(64) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(64): truncated value with size 32 to match size of target (5)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
115 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 small_fifo.v(65) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(65): truncated value with size 32 to match size of target (5)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
116 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 small_fifo.v(66) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(66): truncated value with size 32 to match size of target (6)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
117 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 small_fifo.v(71) " "Warning (10230): Verilog HDL assignment warning at small_fifo.v(71): truncated value with size 32 to match size of target (6)" {  } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
118 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram_256x48 manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|ram_256x48:valid_mac_Map_256x48_Inst " "Info: Elaborating entity \"ram_256x48\" for hierarchy \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|ram_256x48:valid_mac_Map_256x48_Inst\"" {  } { { "TABLE/valid_address.vhd" "valid_mac_Map_256x48_Inst" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/valid_address.vhd" 197 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
119 
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|ram_256x48:valid_mac_256x48_Inst\|ram~21 " "Warning: Inferred RAM node \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|ram_256x48:valid_mac_256x48_Inst\|ram~21\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "TABLE/ram_256x48.vhd" "ram~21" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 35 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0}
120 
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|ram_256x48:valid_mac_Map_256x48_Inst\|ram~21 " "Warning: Inferred RAM node \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|ram_256x48:valid_mac_Map_256x48_Inst\|ram~21\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "TABLE/ram_256x48.vhd" "ram~21" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 35 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0}
121 
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|small_fifo:remove_command_Inst\|queue~0 " "Warning: Inferred RAM node \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|small_fifo:remove_command_Inst\|queue~0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "small_fifo.v" "queue~0" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 38 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0}
122 
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|small_fifo:write_command_Inst\|queue~0 " "Warning: Inferred RAM node \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|small_fifo:write_command_Inst\|queue~0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "small_fifo.v" "queue~0" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 38 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0}
123 
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|small_fifo:WRITE_command_Inst\|queue~0 " "Warning: Inferred RAM node \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|small_fifo:WRITE_command_Inst\|queue~0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "small_fifo.v" "queue~0" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 38 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0}
124 
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|ram~67 " "Warning: Inferred RAM node \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|ram~67\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "TABLE/ram_256x48.vhd" "ram~67" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 35 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0}
125 
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|ram~67 " "Warning: Inferred RAM node \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|ram~67\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "TABLE/ram_256x48.vhd" "ram~67" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 35 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0}
126 
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "manager:inst\|table:table_Inst\|small_fifo:small_fifo_Inst\|queue~0 " "Warning: Inferred RAM node \"manager:inst\|table:table_Inst\|small_fifo:small_fifo_Inst\|queue~0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "small_fifo.v" "queue~0" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 38 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0}
127 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
128 
{ "Info" "ISGN_ELABORATION_HEADER" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|ram_256x48:valid_mac_256x48_Inst\|altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|ram_256x48:valid_mac_256x48_Inst\|altsyncram:ram_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
129 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_n2j1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_n2j1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_n2j1 " "Info: Found entity 1: altsyncram_n2j1" {  } { { "db/altsyncram_n2j1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_n2j1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
130 
{ "Info" "ISGN_ELABORATION_HEADER" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|small_fifo:remove_command_Inst\|altsyncram:queue_rtl_2 " "Info: Elaborated megafunction instantiation \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|valid_address:valid_address_Inst\|small_fifo:remove_command_Inst\|altsyncram:queue_rtl_2\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
131 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rpi1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rpi1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rpi1 " "Info: Found entity 1: altsyncram_rpi1" {  } { { "db/altsyncram_rpi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_rpi1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
132 
{ "Info" "ISGN_ELABORATION_HEADER" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_4 " "Info: Elaborated megafunction instantiation \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_4\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
133 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_pvi1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pvi1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_pvi1 " "Info: Found entity 1: altsyncram_pvi1" {  } { { "db/altsyncram_pvi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_pvi1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
134 
{ "Info" "ISGN_ELABORATION_HEADER" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|altsyncram:ram_rtl_6 " "Info: Elaborated megafunction instantiation \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|altsyncram:ram_rtl_6\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
135 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_b3j1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_b3j1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_b3j1 " "Info: Found entity 1: altsyncram_b3j1" {  } { { "db/altsyncram_b3j1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_b3j1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
136 
{ "Info" "ISGN_ELABORATION_HEADER" "manager:inst\|table:table_Inst\|small_fifo:small_fifo_Inst\|altsyncram:queue_rtl_8 " "Info: Elaborated megafunction instantiation \"manager:inst\|table:table_Inst\|small_fifo:small_fifo_Inst\|altsyncram:queue_rtl_8\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
137 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3ui1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3ui1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3ui1 " "Info: Found entity 1: altsyncram_3ui1" {  } { { "db/altsyncram_3ui1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_3ui1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
138 
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 76 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 76 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "169 " "Info: Allocated 169 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 20:16:37 2010 " "Info: Processing ended: Sun Jan 10 20:16:37 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}

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