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atalla |
--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=8 NUMWORDS_B=8 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=72 WIDTH_B=72 WIDTHAD_A=3 WIDTHAD_B=3 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 7.2SP3 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ VERSION_END
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-- Copyright (C) 1991-2007 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
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WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = ram_bits (AUTO) 576
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_dni1
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(
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address_a[2..0] : input;
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address_b[2..0] : input;
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clock0 : input;
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data_a[71..0] : input;
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q_b[71..0] : output;
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wren_a : input;
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)
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VARIABLE
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ram_block1a0 : stratixii_ram_block
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WITH (
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 3,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 7,
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PORT_A_LOGICAL_RAM_DEPTH = 8,
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PORT_A_LOGICAL_RAM_WIDTH = 72,
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 3,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_OUT_CLOCK = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 0,
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PORT_B_LAST_ADDRESS = 7,
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PORT_B_LOGICAL_RAM_DEPTH = 8,
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PORT_B_LOGICAL_RAM_WIDTH = 72,
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : stratixii_ram_block
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WITH (
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 3,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 7,
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PORT_A_LOGICAL_RAM_DEPTH = 8,
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PORT_A_LOGICAL_RAM_WIDTH = 72,
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 3,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_OUT_CLOCK = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 1,
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PORT_B_LAST_ADDRESS = 7,
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PORT_B_LOGICAL_RAM_DEPTH = 8,
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PORT_B_LOGICAL_RAM_WIDTH = 72,
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a2 : stratixii_ram_block
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WITH (
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| 99 |
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 3,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 2,
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PORT_A_LAST_ADDRESS = 7,
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PORT_A_LOGICAL_RAM_DEPTH = 8,
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PORT_A_LOGICAL_RAM_WIDTH = 72,
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 3,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_OUT_CLOCK = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 2,
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PORT_B_LAST_ADDRESS = 7,
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PORT_B_LOGICAL_RAM_DEPTH = 8,
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PORT_B_LOGICAL_RAM_WIDTH = 72,
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a3 : stratixii_ram_block
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WITH (
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| 129 |
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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| 131 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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| 134 |
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PORT_A_ADDRESS_WIDTH = 3,
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| 135 |
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PORT_A_DATA_WIDTH = 1,
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| 136 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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| 137 |
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PORT_A_FIRST_ADDRESS = 0,
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| 138 |
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PORT_A_FIRST_BIT_NUMBER = 3,
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| 139 |
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PORT_A_LAST_ADDRESS = 7,
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| 140 |
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PORT_A_LOGICAL_RAM_DEPTH = 8,
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| 141 |
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PORT_A_LOGICAL_RAM_WIDTH = 72,
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| 142 |
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PORT_B_ADDRESS_CLOCK = "clock0",
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| 143 |
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PORT_B_ADDRESS_WIDTH = 3,
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| 144 |
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PORT_B_DATA_OUT_CLEAR = "none",
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| 145 |
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PORT_B_DATA_OUT_CLOCK = "none",
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| 146 |
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PORT_B_DATA_WIDTH = 1,
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| 147 |
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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| 148 |
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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| 149 |
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PORT_B_FIRST_ADDRESS = 0,
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| 150 |
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PORT_B_FIRST_BIT_NUMBER = 3,
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| 151 |
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PORT_B_LAST_ADDRESS = 7,
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| 152 |
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PORT_B_LOGICAL_RAM_DEPTH = 8,
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| 153 |
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PORT_B_LOGICAL_RAM_WIDTH = 72,
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| 154 |
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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| 155 |
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RAM_BLOCK_TYPE = "AUTO"
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| 156 |
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);
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| 157 |
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ram_block1a4 : stratixii_ram_block
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| 158 |
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WITH (
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| 159 |
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CONNECTIVITY_CHECKING = "OFF",
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| 160 |
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DONT_POWER_OPTIMIZE = "ON",
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| 161 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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| 162 |
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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| 163 |
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OPERATION_MODE = "dual_port",
|
| 164 |
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PORT_A_ADDRESS_WIDTH = 3,
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| 165 |
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PORT_A_DATA_WIDTH = 1,
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| 166 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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| 167 |
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PORT_A_FIRST_ADDRESS = 0,
|
| 168 |
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PORT_A_FIRST_BIT_NUMBER = 4,
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| 169 |
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PORT_A_LAST_ADDRESS = 7,
|
| 170 |
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PORT_A_LOGICAL_RAM_DEPTH = 8,
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| 171 |
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PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 172 |
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PORT_B_ADDRESS_CLOCK = "clock0",
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| 173 |
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PORT_B_ADDRESS_WIDTH = 3,
|
| 174 |
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PORT_B_DATA_OUT_CLEAR = "none",
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| 175 |
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PORT_B_DATA_OUT_CLOCK = "none",
|
| 176 |
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PORT_B_DATA_WIDTH = 1,
|
| 177 |
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 178 |
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 179 |
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PORT_B_FIRST_ADDRESS = 0,
|
| 180 |
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PORT_B_FIRST_BIT_NUMBER = 4,
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| 181 |
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PORT_B_LAST_ADDRESS = 7,
|
| 182 |
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PORT_B_LOGICAL_RAM_DEPTH = 8,
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| 183 |
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PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 184 |
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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| 185 |
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RAM_BLOCK_TYPE = "AUTO"
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| 186 |
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);
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| 187 |
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ram_block1a5 : stratixii_ram_block
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| 188 |
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WITH (
|
| 189 |
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CONNECTIVITY_CHECKING = "OFF",
|
| 190 |
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DONT_POWER_OPTIMIZE = "ON",
|
| 191 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 192 |
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MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 193 |
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OPERATION_MODE = "dual_port",
|
| 194 |
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PORT_A_ADDRESS_WIDTH = 3,
|
| 195 |
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PORT_A_DATA_WIDTH = 1,
|
| 196 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 197 |
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PORT_A_FIRST_ADDRESS = 0,
|
| 198 |
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PORT_A_FIRST_BIT_NUMBER = 5,
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| 199 |
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PORT_A_LAST_ADDRESS = 7,
|
| 200 |
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PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 201 |
|
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PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 202 |
|
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PORT_B_ADDRESS_CLOCK = "clock0",
|
| 203 |
|
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PORT_B_ADDRESS_WIDTH = 3,
|
| 204 |
|
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PORT_B_DATA_OUT_CLEAR = "none",
|
| 205 |
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PORT_B_DATA_OUT_CLOCK = "none",
|
| 206 |
|
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PORT_B_DATA_WIDTH = 1,
|
| 207 |
|
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 208 |
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 209 |
|
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PORT_B_FIRST_ADDRESS = 0,
|
| 210 |
|
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PORT_B_FIRST_BIT_NUMBER = 5,
|
| 211 |
|
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PORT_B_LAST_ADDRESS = 7,
|
| 212 |
|
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PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 213 |
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PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 214 |
|
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 215 |
|
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RAM_BLOCK_TYPE = "AUTO"
|
| 216 |
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);
|
| 217 |
|
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ram_block1a6 : stratixii_ram_block
|
| 218 |
|
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WITH (
|
| 219 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 220 |
|
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DONT_POWER_OPTIMIZE = "ON",
|
| 221 |
|
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 222 |
|
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MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 223 |
|
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OPERATION_MODE = "dual_port",
|
| 224 |
|
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PORT_A_ADDRESS_WIDTH = 3,
|
| 225 |
|
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PORT_A_DATA_WIDTH = 1,
|
| 226 |
|
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 227 |
|
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PORT_A_FIRST_ADDRESS = 0,
|
| 228 |
|
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PORT_A_FIRST_BIT_NUMBER = 6,
|
| 229 |
|
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PORT_A_LAST_ADDRESS = 7,
|
| 230 |
|
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PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 231 |
|
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PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 232 |
|
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PORT_B_ADDRESS_CLOCK = "clock0",
|
| 233 |
|
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PORT_B_ADDRESS_WIDTH = 3,
|
| 234 |
|
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PORT_B_DATA_OUT_CLEAR = "none",
|
| 235 |
|
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PORT_B_DATA_OUT_CLOCK = "none",
|
| 236 |
|
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PORT_B_DATA_WIDTH = 1,
|
| 237 |
|
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 238 |
|
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 239 |
|
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PORT_B_FIRST_ADDRESS = 0,
|
| 240 |
|
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PORT_B_FIRST_BIT_NUMBER = 6,
|
| 241 |
|
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PORT_B_LAST_ADDRESS = 7,
|
| 242 |
|
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PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 243 |
|
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PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 244 |
|
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 245 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 246 |
|
|
);
|
| 247 |
|
|
ram_block1a7 : stratixii_ram_block
|
| 248 |
|
|
WITH (
|
| 249 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 250 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 251 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 252 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 253 |
|
|
OPERATION_MODE = "dual_port",
|
| 254 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 255 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 256 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 257 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 258 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 259 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 260 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 261 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 262 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 263 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 264 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 265 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 266 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 267 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 268 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 269 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 270 |
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
| 271 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 272 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 273 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 274 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 275 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 276 |
|
|
);
|
| 277 |
|
|
ram_block1a8 : stratixii_ram_block
|
| 278 |
|
|
WITH (
|
| 279 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 280 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 281 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 282 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 283 |
|
|
OPERATION_MODE = "dual_port",
|
| 284 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 285 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 286 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 287 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 288 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 289 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 290 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 291 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 292 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 293 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 294 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 295 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 296 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 297 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 298 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 299 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 300 |
|
|
PORT_B_FIRST_BIT_NUMBER = 8,
|
| 301 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 302 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 303 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 304 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 305 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 306 |
|
|
);
|
| 307 |
|
|
ram_block1a9 : stratixii_ram_block
|
| 308 |
|
|
WITH (
|
| 309 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 310 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 311 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 312 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 313 |
|
|
OPERATION_MODE = "dual_port",
|
| 314 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 315 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 316 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 317 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 318 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 319 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 320 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 321 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 322 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 323 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 324 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 325 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 326 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 327 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 328 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 329 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 330 |
|
|
PORT_B_FIRST_BIT_NUMBER = 9,
|
| 331 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 332 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 333 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 334 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 335 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 336 |
|
|
);
|
| 337 |
|
|
ram_block1a10 : stratixii_ram_block
|
| 338 |
|
|
WITH (
|
| 339 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 340 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 341 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 342 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 343 |
|
|
OPERATION_MODE = "dual_port",
|
| 344 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 345 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 346 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 347 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 348 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 349 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 350 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 351 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 352 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 353 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 354 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 355 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 356 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 357 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 358 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 359 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 360 |
|
|
PORT_B_FIRST_BIT_NUMBER = 10,
|
| 361 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 362 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 363 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 364 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 365 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 366 |
|
|
);
|
| 367 |
|
|
ram_block1a11 : stratixii_ram_block
|
| 368 |
|
|
WITH (
|
| 369 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 370 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 371 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 372 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 373 |
|
|
OPERATION_MODE = "dual_port",
|
| 374 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 375 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 376 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 377 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 378 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 379 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 380 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 381 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 382 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 383 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 384 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 385 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 386 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 387 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 388 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 389 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 390 |
|
|
PORT_B_FIRST_BIT_NUMBER = 11,
|
| 391 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 392 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 393 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 394 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 395 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 396 |
|
|
);
|
| 397 |
|
|
ram_block1a12 : stratixii_ram_block
|
| 398 |
|
|
WITH (
|
| 399 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 400 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 401 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 402 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 403 |
|
|
OPERATION_MODE = "dual_port",
|
| 404 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 405 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 406 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 407 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 408 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 409 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 410 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 411 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 412 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 413 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 414 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 415 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 416 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 417 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 418 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 419 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 420 |
|
|
PORT_B_FIRST_BIT_NUMBER = 12,
|
| 421 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 422 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 423 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 424 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 425 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 426 |
|
|
);
|
| 427 |
|
|
ram_block1a13 : stratixii_ram_block
|
| 428 |
|
|
WITH (
|
| 429 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 430 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 431 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 432 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 433 |
|
|
OPERATION_MODE = "dual_port",
|
| 434 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 435 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 436 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 437 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 438 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 439 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 440 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 441 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 442 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 443 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 444 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 445 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 446 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 447 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 448 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 449 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 450 |
|
|
PORT_B_FIRST_BIT_NUMBER = 13,
|
| 451 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 452 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 453 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 454 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 455 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 456 |
|
|
);
|
| 457 |
|
|
ram_block1a14 : stratixii_ram_block
|
| 458 |
|
|
WITH (
|
| 459 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 460 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 461 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 462 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 463 |
|
|
OPERATION_MODE = "dual_port",
|
| 464 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 465 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 466 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 467 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 468 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 469 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 470 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 471 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 472 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 473 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 474 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 475 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 476 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 477 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 478 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 479 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 480 |
|
|
PORT_B_FIRST_BIT_NUMBER = 14,
|
| 481 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 482 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 483 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 484 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 485 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 486 |
|
|
);
|
| 487 |
|
|
ram_block1a15 : stratixii_ram_block
|
| 488 |
|
|
WITH (
|
| 489 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 490 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 491 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 492 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 493 |
|
|
OPERATION_MODE = "dual_port",
|
| 494 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 495 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 496 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 497 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 498 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 499 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 500 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 501 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 502 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 503 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 504 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 505 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 506 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 507 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 508 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 509 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 510 |
|
|
PORT_B_FIRST_BIT_NUMBER = 15,
|
| 511 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 512 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 513 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 514 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 515 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 516 |
|
|
);
|
| 517 |
|
|
ram_block1a16 : stratixii_ram_block
|
| 518 |
|
|
WITH (
|
| 519 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 520 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 521 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 522 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 523 |
|
|
OPERATION_MODE = "dual_port",
|
| 524 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 525 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 526 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 527 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 528 |
|
|
PORT_A_FIRST_BIT_NUMBER = 16,
|
| 529 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 530 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 531 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 532 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 533 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 534 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 535 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 536 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 537 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 538 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 539 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 540 |
|
|
PORT_B_FIRST_BIT_NUMBER = 16,
|
| 541 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 542 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 543 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 544 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 545 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 546 |
|
|
);
|
| 547 |
|
|
ram_block1a17 : stratixii_ram_block
|
| 548 |
|
|
WITH (
|
| 549 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 550 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 551 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 552 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 553 |
|
|
OPERATION_MODE = "dual_port",
|
| 554 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 555 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 556 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 557 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 558 |
|
|
PORT_A_FIRST_BIT_NUMBER = 17,
|
| 559 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 560 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 561 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 562 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 563 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 564 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 565 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 566 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 567 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 568 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 569 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 570 |
|
|
PORT_B_FIRST_BIT_NUMBER = 17,
|
| 571 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 572 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 573 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 574 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 575 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 576 |
|
|
);
|
| 577 |
|
|
ram_block1a18 : stratixii_ram_block
|
| 578 |
|
|
WITH (
|
| 579 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 580 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 581 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 582 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 583 |
|
|
OPERATION_MODE = "dual_port",
|
| 584 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 585 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 586 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 587 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 588 |
|
|
PORT_A_FIRST_BIT_NUMBER = 18,
|
| 589 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 590 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 591 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 592 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 593 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 594 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 595 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 596 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 597 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 598 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 599 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 600 |
|
|
PORT_B_FIRST_BIT_NUMBER = 18,
|
| 601 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 602 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 603 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 604 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 605 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 606 |
|
|
);
|
| 607 |
|
|
ram_block1a19 : stratixii_ram_block
|
| 608 |
|
|
WITH (
|
| 609 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 610 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 611 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 612 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 613 |
|
|
OPERATION_MODE = "dual_port",
|
| 614 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 615 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 616 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 617 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 618 |
|
|
PORT_A_FIRST_BIT_NUMBER = 19,
|
| 619 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 620 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 621 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 622 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 623 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 624 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 625 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 626 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 627 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 628 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 629 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 630 |
|
|
PORT_B_FIRST_BIT_NUMBER = 19,
|
| 631 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 632 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 633 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 634 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 635 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 636 |
|
|
);
|
| 637 |
|
|
ram_block1a20 : stratixii_ram_block
|
| 638 |
|
|
WITH (
|
| 639 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 640 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 641 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 642 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 643 |
|
|
OPERATION_MODE = "dual_port",
|
| 644 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 645 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 646 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 647 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 648 |
|
|
PORT_A_FIRST_BIT_NUMBER = 20,
|
| 649 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 650 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 651 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 652 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 653 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 654 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 655 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 656 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 657 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 658 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 659 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 660 |
|
|
PORT_B_FIRST_BIT_NUMBER = 20,
|
| 661 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 662 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 663 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 664 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 665 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 666 |
|
|
);
|
| 667 |
|
|
ram_block1a21 : stratixii_ram_block
|
| 668 |
|
|
WITH (
|
| 669 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 670 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 671 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 672 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 673 |
|
|
OPERATION_MODE = "dual_port",
|
| 674 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 675 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 676 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 677 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 678 |
|
|
PORT_A_FIRST_BIT_NUMBER = 21,
|
| 679 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 680 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 681 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 682 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 683 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 684 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 685 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 686 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 687 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 688 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 689 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 690 |
|
|
PORT_B_FIRST_BIT_NUMBER = 21,
|
| 691 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 692 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 693 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 694 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 695 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 696 |
|
|
);
|
| 697 |
|
|
ram_block1a22 : stratixii_ram_block
|
| 698 |
|
|
WITH (
|
| 699 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 700 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 701 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 702 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 703 |
|
|
OPERATION_MODE = "dual_port",
|
| 704 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 705 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 706 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 707 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 708 |
|
|
PORT_A_FIRST_BIT_NUMBER = 22,
|
| 709 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 710 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 711 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 712 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 713 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 714 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 715 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 716 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 717 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 718 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 719 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 720 |
|
|
PORT_B_FIRST_BIT_NUMBER = 22,
|
| 721 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 722 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 723 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 724 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 725 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 726 |
|
|
);
|
| 727 |
|
|
ram_block1a23 : stratixii_ram_block
|
| 728 |
|
|
WITH (
|
| 729 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 730 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 731 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 732 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 733 |
|
|
OPERATION_MODE = "dual_port",
|
| 734 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 735 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 736 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 737 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 738 |
|
|
PORT_A_FIRST_BIT_NUMBER = 23,
|
| 739 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 740 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 741 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 742 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 743 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 744 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 745 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 746 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 747 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 748 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 749 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 750 |
|
|
PORT_B_FIRST_BIT_NUMBER = 23,
|
| 751 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 752 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 753 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 754 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 755 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 756 |
|
|
);
|
| 757 |
|
|
ram_block1a24 : stratixii_ram_block
|
| 758 |
|
|
WITH (
|
| 759 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 760 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 761 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 762 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 763 |
|
|
OPERATION_MODE = "dual_port",
|
| 764 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 765 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 766 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 767 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 768 |
|
|
PORT_A_FIRST_BIT_NUMBER = 24,
|
| 769 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 770 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 771 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 772 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 773 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 774 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 775 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 776 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 777 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 778 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 779 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 780 |
|
|
PORT_B_FIRST_BIT_NUMBER = 24,
|
| 781 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 782 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 783 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 784 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 785 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 786 |
|
|
);
|
| 787 |
|
|
ram_block1a25 : stratixii_ram_block
|
| 788 |
|
|
WITH (
|
| 789 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 790 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 791 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 792 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 793 |
|
|
OPERATION_MODE = "dual_port",
|
| 794 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 795 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 796 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 797 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 798 |
|
|
PORT_A_FIRST_BIT_NUMBER = 25,
|
| 799 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 800 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 801 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 802 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 803 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 804 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 805 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 806 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 807 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 808 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 809 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 810 |
|
|
PORT_B_FIRST_BIT_NUMBER = 25,
|
| 811 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 812 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 813 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 814 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 815 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 816 |
|
|
);
|
| 817 |
|
|
ram_block1a26 : stratixii_ram_block
|
| 818 |
|
|
WITH (
|
| 819 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 820 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 821 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 822 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 823 |
|
|
OPERATION_MODE = "dual_port",
|
| 824 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 825 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 826 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 827 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 828 |
|
|
PORT_A_FIRST_BIT_NUMBER = 26,
|
| 829 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 830 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 831 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 832 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 833 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 834 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 835 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 836 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 837 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 838 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 839 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 840 |
|
|
PORT_B_FIRST_BIT_NUMBER = 26,
|
| 841 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 842 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 843 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 844 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 845 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 846 |
|
|
);
|
| 847 |
|
|
ram_block1a27 : stratixii_ram_block
|
| 848 |
|
|
WITH (
|
| 849 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 850 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 851 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 852 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 853 |
|
|
OPERATION_MODE = "dual_port",
|
| 854 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 855 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 856 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 857 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 858 |
|
|
PORT_A_FIRST_BIT_NUMBER = 27,
|
| 859 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 860 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 861 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 862 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 863 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 864 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 865 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 866 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 867 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 868 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 869 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 870 |
|
|
PORT_B_FIRST_BIT_NUMBER = 27,
|
| 871 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 872 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 873 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 874 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 875 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 876 |
|
|
);
|
| 877 |
|
|
ram_block1a28 : stratixii_ram_block
|
| 878 |
|
|
WITH (
|
| 879 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 880 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 881 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 882 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 883 |
|
|
OPERATION_MODE = "dual_port",
|
| 884 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 885 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 886 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 887 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 888 |
|
|
PORT_A_FIRST_BIT_NUMBER = 28,
|
| 889 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 890 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 891 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 892 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 893 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 894 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 895 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 896 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 897 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 898 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 899 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 900 |
|
|
PORT_B_FIRST_BIT_NUMBER = 28,
|
| 901 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 902 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 903 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 904 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 905 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 906 |
|
|
);
|
| 907 |
|
|
ram_block1a29 : stratixii_ram_block
|
| 908 |
|
|
WITH (
|
| 909 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 910 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 911 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 912 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 913 |
|
|
OPERATION_MODE = "dual_port",
|
| 914 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 915 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 916 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 917 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 918 |
|
|
PORT_A_FIRST_BIT_NUMBER = 29,
|
| 919 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 920 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 921 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 922 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 923 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 924 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 925 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 926 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 927 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 928 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 929 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 930 |
|
|
PORT_B_FIRST_BIT_NUMBER = 29,
|
| 931 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 932 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 933 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 934 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 935 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 936 |
|
|
);
|
| 937 |
|
|
ram_block1a30 : stratixii_ram_block
|
| 938 |
|
|
WITH (
|
| 939 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 940 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 941 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 942 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 943 |
|
|
OPERATION_MODE = "dual_port",
|
| 944 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 945 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 946 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 947 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 948 |
|
|
PORT_A_FIRST_BIT_NUMBER = 30,
|
| 949 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 950 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 951 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 952 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 953 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 954 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 955 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 956 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 957 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 958 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 959 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 960 |
|
|
PORT_B_FIRST_BIT_NUMBER = 30,
|
| 961 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 962 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 963 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 964 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 965 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 966 |
|
|
);
|
| 967 |
|
|
ram_block1a31 : stratixii_ram_block
|
| 968 |
|
|
WITH (
|
| 969 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 970 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 971 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 972 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 973 |
|
|
OPERATION_MODE = "dual_port",
|
| 974 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 975 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 976 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 977 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 978 |
|
|
PORT_A_FIRST_BIT_NUMBER = 31,
|
| 979 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 980 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 981 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 982 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 983 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 984 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 985 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 986 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 987 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 988 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 989 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 990 |
|
|
PORT_B_FIRST_BIT_NUMBER = 31,
|
| 991 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 992 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 993 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 994 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 995 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 996 |
|
|
);
|
| 997 |
|
|
ram_block1a32 : stratixii_ram_block
|
| 998 |
|
|
WITH (
|
| 999 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1000 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1001 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1002 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1003 |
|
|
OPERATION_MODE = "dual_port",
|
| 1004 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1005 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1006 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1007 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1008 |
|
|
PORT_A_FIRST_BIT_NUMBER = 32,
|
| 1009 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1010 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1011 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1012 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1013 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1014 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1015 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1016 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1017 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1018 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1019 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1020 |
|
|
PORT_B_FIRST_BIT_NUMBER = 32,
|
| 1021 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1022 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1023 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1024 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1025 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1026 |
|
|
);
|
| 1027 |
|
|
ram_block1a33 : stratixii_ram_block
|
| 1028 |
|
|
WITH (
|
| 1029 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1030 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1031 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1032 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1033 |
|
|
OPERATION_MODE = "dual_port",
|
| 1034 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1035 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1036 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1037 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1038 |
|
|
PORT_A_FIRST_BIT_NUMBER = 33,
|
| 1039 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1040 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1041 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1042 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1043 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1044 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1045 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1046 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1047 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1048 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1049 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1050 |
|
|
PORT_B_FIRST_BIT_NUMBER = 33,
|
| 1051 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1052 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1053 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1054 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1055 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1056 |
|
|
);
|
| 1057 |
|
|
ram_block1a34 : stratixii_ram_block
|
| 1058 |
|
|
WITH (
|
| 1059 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1060 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1061 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1062 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1063 |
|
|
OPERATION_MODE = "dual_port",
|
| 1064 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1065 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1066 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1067 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1068 |
|
|
PORT_A_FIRST_BIT_NUMBER = 34,
|
| 1069 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1070 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1071 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1072 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1073 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1074 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1075 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1076 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1077 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1078 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1079 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1080 |
|
|
PORT_B_FIRST_BIT_NUMBER = 34,
|
| 1081 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1082 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1083 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1084 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1085 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1086 |
|
|
);
|
| 1087 |
|
|
ram_block1a35 : stratixii_ram_block
|
| 1088 |
|
|
WITH (
|
| 1089 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1090 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1091 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1092 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1093 |
|
|
OPERATION_MODE = "dual_port",
|
| 1094 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1095 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1096 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1097 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1098 |
|
|
PORT_A_FIRST_BIT_NUMBER = 35,
|
| 1099 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1100 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1101 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1102 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1103 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1104 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1105 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1106 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1107 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1108 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1109 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1110 |
|
|
PORT_B_FIRST_BIT_NUMBER = 35,
|
| 1111 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1112 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1113 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1114 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1115 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1116 |
|
|
);
|
| 1117 |
|
|
ram_block1a36 : stratixii_ram_block
|
| 1118 |
|
|
WITH (
|
| 1119 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1120 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1121 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1122 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1123 |
|
|
OPERATION_MODE = "dual_port",
|
| 1124 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1125 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1126 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1127 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1128 |
|
|
PORT_A_FIRST_BIT_NUMBER = 36,
|
| 1129 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1130 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1131 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1132 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1133 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1134 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1135 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1136 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1137 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1138 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1139 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1140 |
|
|
PORT_B_FIRST_BIT_NUMBER = 36,
|
| 1141 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1142 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1143 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1144 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1145 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1146 |
|
|
);
|
| 1147 |
|
|
ram_block1a37 : stratixii_ram_block
|
| 1148 |
|
|
WITH (
|
| 1149 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1150 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1151 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1152 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1153 |
|
|
OPERATION_MODE = "dual_port",
|
| 1154 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1155 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1156 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1157 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1158 |
|
|
PORT_A_FIRST_BIT_NUMBER = 37,
|
| 1159 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1160 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1161 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1162 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1163 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1164 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1165 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1166 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1167 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1168 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1169 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1170 |
|
|
PORT_B_FIRST_BIT_NUMBER = 37,
|
| 1171 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1172 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1173 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1174 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1175 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1176 |
|
|
);
|
| 1177 |
|
|
ram_block1a38 : stratixii_ram_block
|
| 1178 |
|
|
WITH (
|
| 1179 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1180 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1181 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1182 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1183 |
|
|
OPERATION_MODE = "dual_port",
|
| 1184 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1185 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1186 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1187 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1188 |
|
|
PORT_A_FIRST_BIT_NUMBER = 38,
|
| 1189 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1190 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1191 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1192 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1193 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1194 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1195 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1196 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1197 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1198 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1199 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1200 |
|
|
PORT_B_FIRST_BIT_NUMBER = 38,
|
| 1201 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1202 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1203 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1204 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1205 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1206 |
|
|
);
|
| 1207 |
|
|
ram_block1a39 : stratixii_ram_block
|
| 1208 |
|
|
WITH (
|
| 1209 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1210 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1211 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1212 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1213 |
|
|
OPERATION_MODE = "dual_port",
|
| 1214 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1215 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1216 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1217 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1218 |
|
|
PORT_A_FIRST_BIT_NUMBER = 39,
|
| 1219 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1220 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1221 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1222 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1223 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1224 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1225 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1226 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1227 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1228 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1229 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1230 |
|
|
PORT_B_FIRST_BIT_NUMBER = 39,
|
| 1231 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1232 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1233 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1234 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1235 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1236 |
|
|
);
|
| 1237 |
|
|
ram_block1a40 : stratixii_ram_block
|
| 1238 |
|
|
WITH (
|
| 1239 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1240 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1241 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1242 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1243 |
|
|
OPERATION_MODE = "dual_port",
|
| 1244 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1245 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1246 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1247 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1248 |
|
|
PORT_A_FIRST_BIT_NUMBER = 40,
|
| 1249 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1250 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1251 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1252 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1253 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1254 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1255 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1256 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1257 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1258 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1259 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1260 |
|
|
PORT_B_FIRST_BIT_NUMBER = 40,
|
| 1261 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1262 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1263 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1264 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1265 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1266 |
|
|
);
|
| 1267 |
|
|
ram_block1a41 : stratixii_ram_block
|
| 1268 |
|
|
WITH (
|
| 1269 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1270 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1271 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1272 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1273 |
|
|
OPERATION_MODE = "dual_port",
|
| 1274 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1275 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1276 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1277 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1278 |
|
|
PORT_A_FIRST_BIT_NUMBER = 41,
|
| 1279 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1280 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1281 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1282 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1283 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1284 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1285 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1286 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1287 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1288 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1289 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1290 |
|
|
PORT_B_FIRST_BIT_NUMBER = 41,
|
| 1291 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1292 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1293 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1294 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1295 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1296 |
|
|
);
|
| 1297 |
|
|
ram_block1a42 : stratixii_ram_block
|
| 1298 |
|
|
WITH (
|
| 1299 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1300 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1301 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1302 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1303 |
|
|
OPERATION_MODE = "dual_port",
|
| 1304 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1305 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1306 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1307 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1308 |
|
|
PORT_A_FIRST_BIT_NUMBER = 42,
|
| 1309 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1310 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1311 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1312 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1313 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1314 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1315 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1316 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1317 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1318 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1319 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1320 |
|
|
PORT_B_FIRST_BIT_NUMBER = 42,
|
| 1321 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1322 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1323 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1324 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1325 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1326 |
|
|
);
|
| 1327 |
|
|
ram_block1a43 : stratixii_ram_block
|
| 1328 |
|
|
WITH (
|
| 1329 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1330 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1331 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1332 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1333 |
|
|
OPERATION_MODE = "dual_port",
|
| 1334 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1335 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1336 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1337 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1338 |
|
|
PORT_A_FIRST_BIT_NUMBER = 43,
|
| 1339 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1340 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1341 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1342 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1343 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1344 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1345 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1346 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1347 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1348 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1349 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1350 |
|
|
PORT_B_FIRST_BIT_NUMBER = 43,
|
| 1351 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1352 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1353 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1354 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1355 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1356 |
|
|
);
|
| 1357 |
|
|
ram_block1a44 : stratixii_ram_block
|
| 1358 |
|
|
WITH (
|
| 1359 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1360 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1361 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1362 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1363 |
|
|
OPERATION_MODE = "dual_port",
|
| 1364 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1365 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1366 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1367 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1368 |
|
|
PORT_A_FIRST_BIT_NUMBER = 44,
|
| 1369 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1370 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1371 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1372 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1373 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1374 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1375 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1376 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1377 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1378 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1379 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1380 |
|
|
PORT_B_FIRST_BIT_NUMBER = 44,
|
| 1381 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1382 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1383 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1384 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1385 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1386 |
|
|
);
|
| 1387 |
|
|
ram_block1a45 : stratixii_ram_block
|
| 1388 |
|
|
WITH (
|
| 1389 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1390 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1391 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1392 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1393 |
|
|
OPERATION_MODE = "dual_port",
|
| 1394 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1395 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1396 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1397 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1398 |
|
|
PORT_A_FIRST_BIT_NUMBER = 45,
|
| 1399 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1400 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1401 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1402 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1403 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1404 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1405 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1406 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1407 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1408 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1409 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1410 |
|
|
PORT_B_FIRST_BIT_NUMBER = 45,
|
| 1411 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1412 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1413 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1414 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1415 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1416 |
|
|
);
|
| 1417 |
|
|
ram_block1a46 : stratixii_ram_block
|
| 1418 |
|
|
WITH (
|
| 1419 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1420 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1421 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1422 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1423 |
|
|
OPERATION_MODE = "dual_port",
|
| 1424 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1425 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1426 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1427 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1428 |
|
|
PORT_A_FIRST_BIT_NUMBER = 46,
|
| 1429 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1430 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1431 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1432 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1433 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1434 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1435 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1436 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1437 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1438 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1439 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1440 |
|
|
PORT_B_FIRST_BIT_NUMBER = 46,
|
| 1441 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1442 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1443 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1444 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1445 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1446 |
|
|
);
|
| 1447 |
|
|
ram_block1a47 : stratixii_ram_block
|
| 1448 |
|
|
WITH (
|
| 1449 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1450 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1451 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1452 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1453 |
|
|
OPERATION_MODE = "dual_port",
|
| 1454 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1455 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1456 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1457 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1458 |
|
|
PORT_A_FIRST_BIT_NUMBER = 47,
|
| 1459 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1460 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1461 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1462 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1463 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1464 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1465 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1466 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1467 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1468 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1469 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1470 |
|
|
PORT_B_FIRST_BIT_NUMBER = 47,
|
| 1471 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1472 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1473 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1474 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1475 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1476 |
|
|
);
|
| 1477 |
|
|
ram_block1a48 : stratixii_ram_block
|
| 1478 |
|
|
WITH (
|
| 1479 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1480 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1481 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1482 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1483 |
|
|
OPERATION_MODE = "dual_port",
|
| 1484 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1485 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1486 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1487 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1488 |
|
|
PORT_A_FIRST_BIT_NUMBER = 48,
|
| 1489 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1490 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1491 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1492 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1493 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1494 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1495 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1496 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1497 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1498 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1499 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1500 |
|
|
PORT_B_FIRST_BIT_NUMBER = 48,
|
| 1501 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1502 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1503 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1504 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1505 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1506 |
|
|
);
|
| 1507 |
|
|
ram_block1a49 : stratixii_ram_block
|
| 1508 |
|
|
WITH (
|
| 1509 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1510 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1511 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1512 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1513 |
|
|
OPERATION_MODE = "dual_port",
|
| 1514 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1515 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1516 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1517 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1518 |
|
|
PORT_A_FIRST_BIT_NUMBER = 49,
|
| 1519 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1520 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1521 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1522 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1523 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1524 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1525 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1526 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1527 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1528 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1529 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1530 |
|
|
PORT_B_FIRST_BIT_NUMBER = 49,
|
| 1531 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1532 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1533 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1534 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1535 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1536 |
|
|
);
|
| 1537 |
|
|
ram_block1a50 : stratixii_ram_block
|
| 1538 |
|
|
WITH (
|
| 1539 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1540 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1541 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1542 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1543 |
|
|
OPERATION_MODE = "dual_port",
|
| 1544 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1545 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1546 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1547 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1548 |
|
|
PORT_A_FIRST_BIT_NUMBER = 50,
|
| 1549 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1550 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1551 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1552 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1553 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1554 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1555 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1556 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1557 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1558 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1559 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1560 |
|
|
PORT_B_FIRST_BIT_NUMBER = 50,
|
| 1561 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1562 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1563 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1564 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1565 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1566 |
|
|
);
|
| 1567 |
|
|
ram_block1a51 : stratixii_ram_block
|
| 1568 |
|
|
WITH (
|
| 1569 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1570 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1571 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1572 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1573 |
|
|
OPERATION_MODE = "dual_port",
|
| 1574 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1575 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1576 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1577 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1578 |
|
|
PORT_A_FIRST_BIT_NUMBER = 51,
|
| 1579 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1580 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1581 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1582 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1583 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1584 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1585 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1586 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1587 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1588 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1589 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1590 |
|
|
PORT_B_FIRST_BIT_NUMBER = 51,
|
| 1591 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1592 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1593 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1594 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1595 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1596 |
|
|
);
|
| 1597 |
|
|
ram_block1a52 : stratixii_ram_block
|
| 1598 |
|
|
WITH (
|
| 1599 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1600 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1601 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1602 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1603 |
|
|
OPERATION_MODE = "dual_port",
|
| 1604 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1605 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1606 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1607 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1608 |
|
|
PORT_A_FIRST_BIT_NUMBER = 52,
|
| 1609 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1610 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1611 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1612 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1613 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1614 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1615 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1616 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1617 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1618 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1619 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1620 |
|
|
PORT_B_FIRST_BIT_NUMBER = 52,
|
| 1621 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1622 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1623 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1624 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1625 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1626 |
|
|
);
|
| 1627 |
|
|
ram_block1a53 : stratixii_ram_block
|
| 1628 |
|
|
WITH (
|
| 1629 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1630 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1631 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1632 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1633 |
|
|
OPERATION_MODE = "dual_port",
|
| 1634 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1635 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1636 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1637 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1638 |
|
|
PORT_A_FIRST_BIT_NUMBER = 53,
|
| 1639 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1640 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1641 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1642 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1643 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1644 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1645 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1646 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1647 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1648 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1649 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1650 |
|
|
PORT_B_FIRST_BIT_NUMBER = 53,
|
| 1651 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1652 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1653 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1654 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1655 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1656 |
|
|
);
|
| 1657 |
|
|
ram_block1a54 : stratixii_ram_block
|
| 1658 |
|
|
WITH (
|
| 1659 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1660 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1661 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1662 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1663 |
|
|
OPERATION_MODE = "dual_port",
|
| 1664 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1665 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1666 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1667 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1668 |
|
|
PORT_A_FIRST_BIT_NUMBER = 54,
|
| 1669 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1670 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1671 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1672 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1673 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1674 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1675 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1676 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1677 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1678 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1679 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1680 |
|
|
PORT_B_FIRST_BIT_NUMBER = 54,
|
| 1681 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1682 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1683 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1684 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1685 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1686 |
|
|
);
|
| 1687 |
|
|
ram_block1a55 : stratixii_ram_block
|
| 1688 |
|
|
WITH (
|
| 1689 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1690 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1691 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1692 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1693 |
|
|
OPERATION_MODE = "dual_port",
|
| 1694 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1695 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1696 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1697 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1698 |
|
|
PORT_A_FIRST_BIT_NUMBER = 55,
|
| 1699 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1700 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1701 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1702 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1703 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1704 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1705 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1706 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1707 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1708 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1709 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1710 |
|
|
PORT_B_FIRST_BIT_NUMBER = 55,
|
| 1711 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1712 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1713 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1714 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1715 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1716 |
|
|
);
|
| 1717 |
|
|
ram_block1a56 : stratixii_ram_block
|
| 1718 |
|
|
WITH (
|
| 1719 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1720 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1721 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1722 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1723 |
|
|
OPERATION_MODE = "dual_port",
|
| 1724 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1725 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1726 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1727 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1728 |
|
|
PORT_A_FIRST_BIT_NUMBER = 56,
|
| 1729 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1730 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1731 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1732 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1733 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1734 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1735 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1736 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1737 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1738 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1739 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1740 |
|
|
PORT_B_FIRST_BIT_NUMBER = 56,
|
| 1741 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1742 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1743 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1744 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1745 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1746 |
|
|
);
|
| 1747 |
|
|
ram_block1a57 : stratixii_ram_block
|
| 1748 |
|
|
WITH (
|
| 1749 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1750 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1751 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1752 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1753 |
|
|
OPERATION_MODE = "dual_port",
|
| 1754 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1755 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1756 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1757 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1758 |
|
|
PORT_A_FIRST_BIT_NUMBER = 57,
|
| 1759 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1760 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1761 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1762 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1763 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1764 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1765 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1766 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1767 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1768 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1769 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1770 |
|
|
PORT_B_FIRST_BIT_NUMBER = 57,
|
| 1771 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1772 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1773 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1774 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1775 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1776 |
|
|
);
|
| 1777 |
|
|
ram_block1a58 : stratixii_ram_block
|
| 1778 |
|
|
WITH (
|
| 1779 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1780 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1781 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1782 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1783 |
|
|
OPERATION_MODE = "dual_port",
|
| 1784 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1785 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1786 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1787 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1788 |
|
|
PORT_A_FIRST_BIT_NUMBER = 58,
|
| 1789 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1790 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1791 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1792 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1793 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1794 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1795 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1796 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1797 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1798 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1799 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1800 |
|
|
PORT_B_FIRST_BIT_NUMBER = 58,
|
| 1801 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1802 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1803 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1804 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1805 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1806 |
|
|
);
|
| 1807 |
|
|
ram_block1a59 : stratixii_ram_block
|
| 1808 |
|
|
WITH (
|
| 1809 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1810 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1811 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1812 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1813 |
|
|
OPERATION_MODE = "dual_port",
|
| 1814 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1815 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1816 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1817 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1818 |
|
|
PORT_A_FIRST_BIT_NUMBER = 59,
|
| 1819 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1820 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1821 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1822 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1823 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1824 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1825 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1826 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1827 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1828 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1829 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1830 |
|
|
PORT_B_FIRST_BIT_NUMBER = 59,
|
| 1831 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1832 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1833 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1834 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1835 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1836 |
|
|
);
|
| 1837 |
|
|
ram_block1a60 : stratixii_ram_block
|
| 1838 |
|
|
WITH (
|
| 1839 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1840 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1841 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1842 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1843 |
|
|
OPERATION_MODE = "dual_port",
|
| 1844 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1845 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1846 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1847 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1848 |
|
|
PORT_A_FIRST_BIT_NUMBER = 60,
|
| 1849 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1850 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1851 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1852 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1853 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1854 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1855 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1856 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1857 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1858 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1859 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1860 |
|
|
PORT_B_FIRST_BIT_NUMBER = 60,
|
| 1861 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1862 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1863 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1864 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1865 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1866 |
|
|
);
|
| 1867 |
|
|
ram_block1a61 : stratixii_ram_block
|
| 1868 |
|
|
WITH (
|
| 1869 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1870 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1871 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1872 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1873 |
|
|
OPERATION_MODE = "dual_port",
|
| 1874 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1875 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1876 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1877 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1878 |
|
|
PORT_A_FIRST_BIT_NUMBER = 61,
|
| 1879 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1880 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1881 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1882 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1883 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1884 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1885 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1886 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1887 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1888 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1889 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1890 |
|
|
PORT_B_FIRST_BIT_NUMBER = 61,
|
| 1891 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1892 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1893 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1894 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1895 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1896 |
|
|
);
|
| 1897 |
|
|
ram_block1a62 : stratixii_ram_block
|
| 1898 |
|
|
WITH (
|
| 1899 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1900 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1901 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1902 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1903 |
|
|
OPERATION_MODE = "dual_port",
|
| 1904 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1905 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1906 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1907 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1908 |
|
|
PORT_A_FIRST_BIT_NUMBER = 62,
|
| 1909 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1910 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1911 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1912 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1913 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1914 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1915 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1916 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1917 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1918 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1919 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1920 |
|
|
PORT_B_FIRST_BIT_NUMBER = 62,
|
| 1921 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1922 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1923 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1924 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1925 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1926 |
|
|
);
|
| 1927 |
|
|
ram_block1a63 : stratixii_ram_block
|
| 1928 |
|
|
WITH (
|
| 1929 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1930 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1931 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1932 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1933 |
|
|
OPERATION_MODE = "dual_port",
|
| 1934 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1935 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1936 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1937 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1938 |
|
|
PORT_A_FIRST_BIT_NUMBER = 63,
|
| 1939 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1940 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1941 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1942 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1943 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1944 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1945 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1946 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1947 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1948 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1949 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1950 |
|
|
PORT_B_FIRST_BIT_NUMBER = 63,
|
| 1951 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1952 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1953 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1954 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1955 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1956 |
|
|
);
|
| 1957 |
|
|
ram_block1a64 : stratixii_ram_block
|
| 1958 |
|
|
WITH (
|
| 1959 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1960 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1961 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1962 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1963 |
|
|
OPERATION_MODE = "dual_port",
|
| 1964 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1965 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1966 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1967 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1968 |
|
|
PORT_A_FIRST_BIT_NUMBER = 64,
|
| 1969 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 1970 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 1971 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 1972 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 1973 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 1974 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 1975 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 1976 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 1977 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1978 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 1979 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 1980 |
|
|
PORT_B_FIRST_BIT_NUMBER = 64,
|
| 1981 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 1982 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 1983 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 1984 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 1985 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1986 |
|
|
);
|
| 1987 |
|
|
ram_block1a65 : stratixii_ram_block
|
| 1988 |
|
|
WITH (
|
| 1989 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1990 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 1991 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1992 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 1993 |
|
|
OPERATION_MODE = "dual_port",
|
| 1994 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 1995 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1996 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 1997 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 1998 |
|
|
PORT_A_FIRST_BIT_NUMBER = 65,
|
| 1999 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 2000 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 2001 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 2002 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 2003 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 2004 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 2005 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 2006 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 2007 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2008 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 2009 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 2010 |
|
|
PORT_B_FIRST_BIT_NUMBER = 65,
|
| 2011 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 2012 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 2013 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 2014 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 2015 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2016 |
|
|
);
|
| 2017 |
|
|
ram_block1a66 : stratixii_ram_block
|
| 2018 |
|
|
WITH (
|
| 2019 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2020 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 2021 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2022 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 2023 |
|
|
OPERATION_MODE = "dual_port",
|
| 2024 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 2025 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2026 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2027 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 2028 |
|
|
PORT_A_FIRST_BIT_NUMBER = 66,
|
| 2029 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 2030 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 2031 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 2032 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 2033 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 2034 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 2035 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 2036 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 2037 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2038 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 2039 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 2040 |
|
|
PORT_B_FIRST_BIT_NUMBER = 66,
|
| 2041 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 2042 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 2043 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 2044 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 2045 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2046 |
|
|
);
|
| 2047 |
|
|
ram_block1a67 : stratixii_ram_block
|
| 2048 |
|
|
WITH (
|
| 2049 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2050 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 2051 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2052 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 2053 |
|
|
OPERATION_MODE = "dual_port",
|
| 2054 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 2055 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2056 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2057 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 2058 |
|
|
PORT_A_FIRST_BIT_NUMBER = 67,
|
| 2059 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 2060 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 2061 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 2062 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 2063 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 2064 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 2065 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 2066 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 2067 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2068 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 2069 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 2070 |
|
|
PORT_B_FIRST_BIT_NUMBER = 67,
|
| 2071 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 2072 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 2073 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 2074 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 2075 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2076 |
|
|
);
|
| 2077 |
|
|
ram_block1a68 : stratixii_ram_block
|
| 2078 |
|
|
WITH (
|
| 2079 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2080 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 2081 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2082 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 2083 |
|
|
OPERATION_MODE = "dual_port",
|
| 2084 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 2085 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2086 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2087 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 2088 |
|
|
PORT_A_FIRST_BIT_NUMBER = 68,
|
| 2089 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 2090 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 2091 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 2092 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 2093 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 2094 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 2095 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 2096 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 2097 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2098 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 2099 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 2100 |
|
|
PORT_B_FIRST_BIT_NUMBER = 68,
|
| 2101 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 2102 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 2103 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 2104 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 2105 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2106 |
|
|
);
|
| 2107 |
|
|
ram_block1a69 : stratixii_ram_block
|
| 2108 |
|
|
WITH (
|
| 2109 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2110 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 2111 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2112 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 2113 |
|
|
OPERATION_MODE = "dual_port",
|
| 2114 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 2115 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2116 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2117 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 2118 |
|
|
PORT_A_FIRST_BIT_NUMBER = 69,
|
| 2119 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 2120 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 2121 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 2122 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 2123 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 2124 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 2125 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 2126 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 2127 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2128 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 2129 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 2130 |
|
|
PORT_B_FIRST_BIT_NUMBER = 69,
|
| 2131 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 2132 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 2133 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 2134 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 2135 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2136 |
|
|
);
|
| 2137 |
|
|
ram_block1a70 : stratixii_ram_block
|
| 2138 |
|
|
WITH (
|
| 2139 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2140 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 2141 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2142 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 2143 |
|
|
OPERATION_MODE = "dual_port",
|
| 2144 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 2145 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2146 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2147 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 2148 |
|
|
PORT_A_FIRST_BIT_NUMBER = 70,
|
| 2149 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 2150 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 2151 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 2152 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 2153 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 2154 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 2155 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 2156 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 2157 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2158 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 2159 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 2160 |
|
|
PORT_B_FIRST_BIT_NUMBER = 70,
|
| 2161 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 2162 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 2163 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 2164 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 2165 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2166 |
|
|
);
|
| 2167 |
|
|
ram_block1a71 : stratixii_ram_block
|
| 2168 |
|
|
WITH (
|
| 2169 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2170 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 2171 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2172 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 2173 |
|
|
OPERATION_MODE = "dual_port",
|
| 2174 |
|
|
PORT_A_ADDRESS_WIDTH = 3,
|
| 2175 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2176 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2177 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 2178 |
|
|
PORT_A_FIRST_BIT_NUMBER = 71,
|
| 2179 |
|
|
PORT_A_LAST_ADDRESS = 7,
|
| 2180 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 8,
|
| 2181 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 72,
|
| 2182 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 2183 |
|
|
PORT_B_ADDRESS_WIDTH = 3,
|
| 2184 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 2185 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 2186 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 2187 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 2188 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 2189 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 2190 |
|
|
PORT_B_FIRST_BIT_NUMBER = 71,
|
| 2191 |
|
|
PORT_B_LAST_ADDRESS = 7,
|
| 2192 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 8,
|
| 2193 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 72,
|
| 2194 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 2195 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2196 |
|
|
);
|
| 2197 |
|
|
address_a_wire[2..0] : WIRE;
|
| 2198 |
|
|
address_b_wire[2..0] : WIRE;
|
| 2199 |
|
|
|
| 2200 |
|
|
BEGIN
|
| 2201 |
|
|
ram_block1a[71..0].clk0 = clock0;
|
| 2202 |
|
|
ram_block1a[71..0].portaaddr[] = ( address_a_wire[2..0]);
|
| 2203 |
|
|
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
| 2204 |
|
|
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
| 2205 |
|
|
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
| 2206 |
|
|
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
| 2207 |
|
|
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
| 2208 |
|
|
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
| 2209 |
|
|
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
| 2210 |
|
|
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
| 2211 |
|
|
ram_block1a[8].portadatain[] = ( data_a[8..8]);
|
| 2212 |
|
|
ram_block1a[9].portadatain[] = ( data_a[9..9]);
|
| 2213 |
|
|
ram_block1a[10].portadatain[] = ( data_a[10..10]);
|
| 2214 |
|
|
ram_block1a[11].portadatain[] = ( data_a[11..11]);
|
| 2215 |
|
|
ram_block1a[12].portadatain[] = ( data_a[12..12]);
|
| 2216 |
|
|
ram_block1a[13].portadatain[] = ( data_a[13..13]);
|
| 2217 |
|
|
ram_block1a[14].portadatain[] = ( data_a[14..14]);
|
| 2218 |
|
|
ram_block1a[15].portadatain[] = ( data_a[15..15]);
|
| 2219 |
|
|
ram_block1a[16].portadatain[] = ( data_a[16..16]);
|
| 2220 |
|
|
ram_block1a[17].portadatain[] = ( data_a[17..17]);
|
| 2221 |
|
|
ram_block1a[18].portadatain[] = ( data_a[18..18]);
|
| 2222 |
|
|
ram_block1a[19].portadatain[] = ( data_a[19..19]);
|
| 2223 |
|
|
ram_block1a[20].portadatain[] = ( data_a[20..20]);
|
| 2224 |
|
|
ram_block1a[21].portadatain[] = ( data_a[21..21]);
|
| 2225 |
|
|
ram_block1a[22].portadatain[] = ( data_a[22..22]);
|
| 2226 |
|
|
ram_block1a[23].portadatain[] = ( data_a[23..23]);
|
| 2227 |
|
|
ram_block1a[24].portadatain[] = ( data_a[24..24]);
|
| 2228 |
|
|
ram_block1a[25].portadatain[] = ( data_a[25..25]);
|
| 2229 |
|
|
ram_block1a[26].portadatain[] = ( data_a[26..26]);
|
| 2230 |
|
|
ram_block1a[27].portadatain[] = ( data_a[27..27]);
|
| 2231 |
|
|
ram_block1a[28].portadatain[] = ( data_a[28..28]);
|
| 2232 |
|
|
ram_block1a[29].portadatain[] = ( data_a[29..29]);
|
| 2233 |
|
|
ram_block1a[30].portadatain[] = ( data_a[30..30]);
|
| 2234 |
|
|
ram_block1a[31].portadatain[] = ( data_a[31..31]);
|
| 2235 |
|
|
ram_block1a[32].portadatain[] = ( data_a[32..32]);
|
| 2236 |
|
|
ram_block1a[33].portadatain[] = ( data_a[33..33]);
|
| 2237 |
|
|
ram_block1a[34].portadatain[] = ( data_a[34..34]);
|
| 2238 |
|
|
ram_block1a[35].portadatain[] = ( data_a[35..35]);
|
| 2239 |
|
|
ram_block1a[36].portadatain[] = ( data_a[36..36]);
|
| 2240 |
|
|
ram_block1a[37].portadatain[] = ( data_a[37..37]);
|
| 2241 |
|
|
ram_block1a[38].portadatain[] = ( data_a[38..38]);
|
| 2242 |
|
|
ram_block1a[39].portadatain[] = ( data_a[39..39]);
|
| 2243 |
|
|
ram_block1a[40].portadatain[] = ( data_a[40..40]);
|
| 2244 |
|
|
ram_block1a[41].portadatain[] = ( data_a[41..41]);
|
| 2245 |
|
|
ram_block1a[42].portadatain[] = ( data_a[42..42]);
|
| 2246 |
|
|
ram_block1a[43].portadatain[] = ( data_a[43..43]);
|
| 2247 |
|
|
ram_block1a[44].portadatain[] = ( data_a[44..44]);
|
| 2248 |
|
|
ram_block1a[45].portadatain[] = ( data_a[45..45]);
|
| 2249 |
|
|
ram_block1a[46].portadatain[] = ( data_a[46..46]);
|
| 2250 |
|
|
ram_block1a[47].portadatain[] = ( data_a[47..47]);
|
| 2251 |
|
|
ram_block1a[48].portadatain[] = ( data_a[48..48]);
|
| 2252 |
|
|
ram_block1a[49].portadatain[] = ( data_a[49..49]);
|
| 2253 |
|
|
ram_block1a[50].portadatain[] = ( data_a[50..50]);
|
| 2254 |
|
|
ram_block1a[51].portadatain[] = ( data_a[51..51]);
|
| 2255 |
|
|
ram_block1a[52].portadatain[] = ( data_a[52..52]);
|
| 2256 |
|
|
ram_block1a[53].portadatain[] = ( data_a[53..53]);
|
| 2257 |
|
|
ram_block1a[54].portadatain[] = ( data_a[54..54]);
|
| 2258 |
|
|
ram_block1a[55].portadatain[] = ( data_a[55..55]);
|
| 2259 |
|
|
ram_block1a[56].portadatain[] = ( data_a[56..56]);
|
| 2260 |
|
|
ram_block1a[57].portadatain[] = ( data_a[57..57]);
|
| 2261 |
|
|
ram_block1a[58].portadatain[] = ( data_a[58..58]);
|
| 2262 |
|
|
ram_block1a[59].portadatain[] = ( data_a[59..59]);
|
| 2263 |
|
|
ram_block1a[60].portadatain[] = ( data_a[60..60]);
|
| 2264 |
|
|
ram_block1a[61].portadatain[] = ( data_a[61..61]);
|
| 2265 |
|
|
ram_block1a[62].portadatain[] = ( data_a[62..62]);
|
| 2266 |
|
|
ram_block1a[63].portadatain[] = ( data_a[63..63]);
|
| 2267 |
|
|
ram_block1a[64].portadatain[] = ( data_a[64..64]);
|
| 2268 |
|
|
ram_block1a[65].portadatain[] = ( data_a[65..65]);
|
| 2269 |
|
|
ram_block1a[66].portadatain[] = ( data_a[66..66]);
|
| 2270 |
|
|
ram_block1a[67].portadatain[] = ( data_a[67..67]);
|
| 2271 |
|
|
ram_block1a[68].portadatain[] = ( data_a[68..68]);
|
| 2272 |
|
|
ram_block1a[69].portadatain[] = ( data_a[69..69]);
|
| 2273 |
|
|
ram_block1a[70].portadatain[] = ( data_a[70..70]);
|
| 2274 |
|
|
ram_block1a[71].portadatain[] = ( data_a[71..71]);
|
| 2275 |
|
|
ram_block1a[71..0].portawe = wren_a;
|
| 2276 |
|
|
ram_block1a[71..0].portbaddr[] = ( address_b_wire[2..0]);
|
| 2277 |
|
|
ram_block1a[71..0].portbrewe = B"111111111111111111111111111111111111111111111111111111111111111111111111";
|
| 2278 |
|
|
address_a_wire[] = address_a[];
|
| 2279 |
|
|
address_b_wire[] = address_b[];
|
| 2280 |
|
|
q_b[] = ( ram_block1a[71..0].portbdataout[0..0]);
|
| 2281 |
|
|
END;
|
| 2282 |
|
|
--VALID FILE
|
