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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=1 WIDTH_B=1 WIDTHAD_A=8 WIDTHAD_B=8 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48

--VERSION_BEGIN 7.2SP3 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END

-- Copyright (C) 1991-2007 Altera Corporation

--  Your use of Altera Corporation's design tools, logic functions

--  and other software and tools, and its AMPP partner logic

--  functions, and any output files from any of the foregoing

--  (including device programming or simulation files), and any

--  associated documentation or information are expressly subject

--  to the terms and conditions of the Altera Program License

--  Subscription Agreement, Altera MegaCore Function License

--  Agreement, or other applicable license agreement, including,

--  without limitation, that your use is for the sole purpose of

--  programming logic devices manufactured by Altera and sold by

--  Altera or its authorized distributors.  Please refer to the

--  applicable agreement for further details.

FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)

WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)

RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = ram_bits (AUTO) 256

OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_iqi1

(

        address_a[7..0] :       input;

        address_b[7..0] :       input;

        clock0  :       input;

        data_a[0..0]    :       input;

        q_b[0..0]       :       output;

        wren_a  :       input;

)

VARIABLE

        ram_block1a0 : stratixii_ram_block

                WITH (

                        CONNECTIVITY_CHECKING = "OFF",

                        DONT_POWER_OPTIMIZE = "ON",

                        LOGICAL_RAM_NAME = "ALTSYNCRAM",

                        MIXED_PORT_FEED_THROUGH_MODE = "old",

                        OPERATION_MODE = "dual_port",

                        PORT_A_ADDRESS_WIDTH = 8,

                        PORT_A_DATA_WIDTH = 1,

                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",

                        PORT_A_FIRST_ADDRESS = 0,

                        PORT_A_FIRST_BIT_NUMBER = 0,

                        PORT_A_LAST_ADDRESS = 255,

                        PORT_A_LOGICAL_RAM_DEPTH = 256,

                        PORT_A_LOGICAL_RAM_WIDTH = 1,

                        PORT_B_ADDRESS_CLOCK = "clock0",

                        PORT_B_ADDRESS_WIDTH = 8,

                        PORT_B_DATA_OUT_CLEAR = "none",

                        PORT_B_DATA_OUT_CLOCK = "none",

                        PORT_B_DATA_WIDTH = 1,

                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",

                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",

                        PORT_B_FIRST_ADDRESS = 0,

                        PORT_B_FIRST_BIT_NUMBER = 0,

                        PORT_B_LAST_ADDRESS = 255,

                        PORT_B_LOGICAL_RAM_DEPTH = 256,

                        PORT_B_LOGICAL_RAM_WIDTH = 1,

                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

                        RAM_BLOCK_TYPE = "AUTO"

                );

        address_a_wire[7..0]    : WIRE;

        address_b_wire[7..0]    : WIRE;

BEGIN

        ram_block1a[0..0].clk0 = clock0;

        ram_block1a[0].portaaddr[] = ( address_a_wire[7..0]);

        ram_block1a[0].portadatain[] = ( data_a[0..0]);

        ram_block1a[0..0].portawe = wren_a;

        ram_block1a[0].portbaddr[] = ( address_b_wire[7..0]);

        ram_block1a[0..0].portbrewe = B"1";

        address_a_wire[] = address_a[];

        address_b_wire[] = address_b[];

        q_b[] = ( ram_block1a[0].portbdataout[0..0]);

END;

--VALID FILE