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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=2 WIDTH_B=2 WIDTHAD_A=10 WIDTHAD_B=10 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 7.2SP3 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ VERSION_END
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-- Copyright (C) 1991-2007 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
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WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = ram_bits (AUTO) 2048
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_pvi1
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(
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address_a[9..0] : input;
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address_b[9..0] : input;
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clock0 : input;
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data_a[1..0] : input;
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q_b[1..0] : output;
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wren_a : input;
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)
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VARIABLE
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ram_block1a0 : stratixii_ram_block
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WITH (
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 10,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 1023,
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PORT_A_LOGICAL_RAM_DEPTH = 1024,
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PORT_A_LOGICAL_RAM_WIDTH = 2,
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 10,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_OUT_CLOCK = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 0,
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PORT_B_LAST_ADDRESS = 1023,
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PORT_B_LOGICAL_RAM_DEPTH = 1024,
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PORT_B_LOGICAL_RAM_WIDTH = 2,
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : stratixii_ram_block
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WITH (
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 10,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 1023,
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PORT_A_LOGICAL_RAM_DEPTH = 1024,
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PORT_A_LOGICAL_RAM_WIDTH = 2,
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 10,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_OUT_CLOCK = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 1,
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PORT_B_LAST_ADDRESS = 1023,
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PORT_B_LOGICAL_RAM_DEPTH = 1024,
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PORT_B_LOGICAL_RAM_WIDTH = 2,
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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address_a_wire[9..0] : WIRE;
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address_b_wire[9..0] : WIRE;
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BEGIN
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ram_block1a[1..0].clk0 = clock0;
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ram_block1a[1..0].portaaddr[] = ( address_a_wire[9..0]);
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ram_block1a[0].portadatain[] = ( data_a[0..0]);
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ram_block1a[1].portadatain[] = ( data_a[1..1]);
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ram_block1a[1..0].portawe = wren_a;
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ram_block1a[1..0].portbaddr[] = ( address_b_wire[9..0]);
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ram_block1a[1..0].portbrewe = B"11";
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address_a_wire[] = address_a[];
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address_b_wire[] = address_b[];
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q_b[] = ( ram_block1a[1..0].portbdataout[0..0]);
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END;
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--VALID FILE
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