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[/] [loadbalancer/] [trunk/] [db/] [altsyncram_vqi1.tdf] - Blame information for rev 2

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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=8 WIDTHAD_B=8 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
2
--VERSION_BEGIN 7.2SP3 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END
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-- Copyright (C) 1991-2007 Altera Corporation
6
--  Your use of Altera Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Altera Program License
12
--  Subscription Agreement, Altera MegaCore Function License
13
--  Agreement, or other applicable license agreement, including,
14
--  without limitation, that your use is for the sole purpose of
15
--  programming logic devices manufactured by Altera and sold by
16
--  Altera or its authorized distributors.  Please refer to the
17
--  applicable agreement for further details.
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19
 
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FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
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WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = ram_bits (AUTO) 2048
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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27
SUBDESIGN altsyncram_vqi1
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(
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        address_a[7..0] :       input;
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        address_b[7..0] :       input;
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        clock0  :       input;
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        data_a[7..0]    :       input;
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        q_b[7..0]       :       output;
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        wren_a  :       input;
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)
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VARIABLE
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        ram_block1a0 : stratixii_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        DONT_POWER_OPTIMIZE = "ON",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        MIXED_PORT_FEED_THROUGH_MODE = "old",
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                        OPERATION_MODE = "dual_port",
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                        PORT_A_ADDRESS_WIDTH = 8,
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 0,
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                        PORT_A_LAST_ADDRESS = 255,
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                        PORT_A_LOGICAL_RAM_DEPTH = 256,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_ADDRESS_CLOCK = "clock0",
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                        PORT_B_ADDRESS_WIDTH = 8,
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                        PORT_B_DATA_OUT_CLEAR = "none",
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                        PORT_B_DATA_OUT_CLOCK = "none",
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                        PORT_B_DATA_WIDTH = 1,
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                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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                        PORT_B_FIRST_ADDRESS = 0,
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                        PORT_B_FIRST_BIT_NUMBER = 0,
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                        PORT_B_LAST_ADDRESS = 255,
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                        PORT_B_LOGICAL_RAM_DEPTH = 256,
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                        PORT_B_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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                        RAM_BLOCK_TYPE = "AUTO"
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                );
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        ram_block1a1 : stratixii_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        DONT_POWER_OPTIMIZE = "ON",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        MIXED_PORT_FEED_THROUGH_MODE = "old",
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                        OPERATION_MODE = "dual_port",
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                        PORT_A_ADDRESS_WIDTH = 8,
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 1,
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                        PORT_A_LAST_ADDRESS = 255,
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                        PORT_A_LOGICAL_RAM_DEPTH = 256,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_ADDRESS_CLOCK = "clock0",
83
                        PORT_B_ADDRESS_WIDTH = 8,
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                        PORT_B_DATA_OUT_CLEAR = "none",
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                        PORT_B_DATA_OUT_CLOCK = "none",
86
                        PORT_B_DATA_WIDTH = 1,
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                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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                        PORT_B_FIRST_ADDRESS = 0,
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                        PORT_B_FIRST_BIT_NUMBER = 1,
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                        PORT_B_LAST_ADDRESS = 255,
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                        PORT_B_LOGICAL_RAM_DEPTH = 256,
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                        PORT_B_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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                        RAM_BLOCK_TYPE = "AUTO"
96
                );
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        ram_block1a2 : stratixii_ram_block
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                WITH (
99
                        CONNECTIVITY_CHECKING = "OFF",
100
                        DONT_POWER_OPTIMIZE = "ON",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
102
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
103
                        OPERATION_MODE = "dual_port",
104
                        PORT_A_ADDRESS_WIDTH = 8,
105
                        PORT_A_DATA_WIDTH = 1,
106
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
107
                        PORT_A_FIRST_ADDRESS = 0,
108
                        PORT_A_FIRST_BIT_NUMBER = 2,
109
                        PORT_A_LAST_ADDRESS = 255,
110
                        PORT_A_LOGICAL_RAM_DEPTH = 256,
111
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
112
                        PORT_B_ADDRESS_CLOCK = "clock0",
113
                        PORT_B_ADDRESS_WIDTH = 8,
114
                        PORT_B_DATA_OUT_CLEAR = "none",
115
                        PORT_B_DATA_OUT_CLOCK = "none",
116
                        PORT_B_DATA_WIDTH = 1,
117
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
118
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
119
                        PORT_B_FIRST_ADDRESS = 0,
120
                        PORT_B_FIRST_BIT_NUMBER = 2,
121
                        PORT_B_LAST_ADDRESS = 255,
122
                        PORT_B_LOGICAL_RAM_DEPTH = 256,
123
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
124
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
125
                        RAM_BLOCK_TYPE = "AUTO"
126
                );
127
        ram_block1a3 : stratixii_ram_block
128
                WITH (
129
                        CONNECTIVITY_CHECKING = "OFF",
130
                        DONT_POWER_OPTIMIZE = "ON",
131
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
132
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
133
                        OPERATION_MODE = "dual_port",
134
                        PORT_A_ADDRESS_WIDTH = 8,
135
                        PORT_A_DATA_WIDTH = 1,
136
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
137
                        PORT_A_FIRST_ADDRESS = 0,
138
                        PORT_A_FIRST_BIT_NUMBER = 3,
139
                        PORT_A_LAST_ADDRESS = 255,
140
                        PORT_A_LOGICAL_RAM_DEPTH = 256,
141
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
142
                        PORT_B_ADDRESS_CLOCK = "clock0",
143
                        PORT_B_ADDRESS_WIDTH = 8,
144
                        PORT_B_DATA_OUT_CLEAR = "none",
145
                        PORT_B_DATA_OUT_CLOCK = "none",
146
                        PORT_B_DATA_WIDTH = 1,
147
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
148
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
149
                        PORT_B_FIRST_ADDRESS = 0,
150
                        PORT_B_FIRST_BIT_NUMBER = 3,
151
                        PORT_B_LAST_ADDRESS = 255,
152
                        PORT_B_LOGICAL_RAM_DEPTH = 256,
153
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
154
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
155
                        RAM_BLOCK_TYPE = "AUTO"
156
                );
157
        ram_block1a4 : stratixii_ram_block
158
                WITH (
159
                        CONNECTIVITY_CHECKING = "OFF",
160
                        DONT_POWER_OPTIMIZE = "ON",
161
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
162
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
163
                        OPERATION_MODE = "dual_port",
164
                        PORT_A_ADDRESS_WIDTH = 8,
165
                        PORT_A_DATA_WIDTH = 1,
166
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
167
                        PORT_A_FIRST_ADDRESS = 0,
168
                        PORT_A_FIRST_BIT_NUMBER = 4,
169
                        PORT_A_LAST_ADDRESS = 255,
170
                        PORT_A_LOGICAL_RAM_DEPTH = 256,
171
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
172
                        PORT_B_ADDRESS_CLOCK = "clock0",
173
                        PORT_B_ADDRESS_WIDTH = 8,
174
                        PORT_B_DATA_OUT_CLEAR = "none",
175
                        PORT_B_DATA_OUT_CLOCK = "none",
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                        PORT_B_DATA_WIDTH = 1,
177
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
178
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
179
                        PORT_B_FIRST_ADDRESS = 0,
180
                        PORT_B_FIRST_BIT_NUMBER = 4,
181
                        PORT_B_LAST_ADDRESS = 255,
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                        PORT_B_LOGICAL_RAM_DEPTH = 256,
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                        PORT_B_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
185
                        RAM_BLOCK_TYPE = "AUTO"
186
                );
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        ram_block1a5 : stratixii_ram_block
188
                WITH (
189
                        CONNECTIVITY_CHECKING = "OFF",
190
                        DONT_POWER_OPTIMIZE = "ON",
191
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
192
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
193
                        OPERATION_MODE = "dual_port",
194
                        PORT_A_ADDRESS_WIDTH = 8,
195
                        PORT_A_DATA_WIDTH = 1,
196
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
197
                        PORT_A_FIRST_ADDRESS = 0,
198
                        PORT_A_FIRST_BIT_NUMBER = 5,
199
                        PORT_A_LAST_ADDRESS = 255,
200
                        PORT_A_LOGICAL_RAM_DEPTH = 256,
201
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
202
                        PORT_B_ADDRESS_CLOCK = "clock0",
203
                        PORT_B_ADDRESS_WIDTH = 8,
204
                        PORT_B_DATA_OUT_CLEAR = "none",
205
                        PORT_B_DATA_OUT_CLOCK = "none",
206
                        PORT_B_DATA_WIDTH = 1,
207
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
208
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
209
                        PORT_B_FIRST_ADDRESS = 0,
210
                        PORT_B_FIRST_BIT_NUMBER = 5,
211
                        PORT_B_LAST_ADDRESS = 255,
212
                        PORT_B_LOGICAL_RAM_DEPTH = 256,
213
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
214
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
215
                        RAM_BLOCK_TYPE = "AUTO"
216
                );
217
        ram_block1a6 : stratixii_ram_block
218
                WITH (
219
                        CONNECTIVITY_CHECKING = "OFF",
220
                        DONT_POWER_OPTIMIZE = "ON",
221
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
222
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
223
                        OPERATION_MODE = "dual_port",
224
                        PORT_A_ADDRESS_WIDTH = 8,
225
                        PORT_A_DATA_WIDTH = 1,
226
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
227
                        PORT_A_FIRST_ADDRESS = 0,
228
                        PORT_A_FIRST_BIT_NUMBER = 6,
229
                        PORT_A_LAST_ADDRESS = 255,
230
                        PORT_A_LOGICAL_RAM_DEPTH = 256,
231
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
232
                        PORT_B_ADDRESS_CLOCK = "clock0",
233
                        PORT_B_ADDRESS_WIDTH = 8,
234
                        PORT_B_DATA_OUT_CLEAR = "none",
235
                        PORT_B_DATA_OUT_CLOCK = "none",
236
                        PORT_B_DATA_WIDTH = 1,
237
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
238
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
239
                        PORT_B_FIRST_ADDRESS = 0,
240
                        PORT_B_FIRST_BIT_NUMBER = 6,
241
                        PORT_B_LAST_ADDRESS = 255,
242
                        PORT_B_LOGICAL_RAM_DEPTH = 256,
243
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
244
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
245
                        RAM_BLOCK_TYPE = "AUTO"
246
                );
247
        ram_block1a7 : stratixii_ram_block
248
                WITH (
249
                        CONNECTIVITY_CHECKING = "OFF",
250
                        DONT_POWER_OPTIMIZE = "ON",
251
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
252
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
253
                        OPERATION_MODE = "dual_port",
254
                        PORT_A_ADDRESS_WIDTH = 8,
255
                        PORT_A_DATA_WIDTH = 1,
256
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
257
                        PORT_A_FIRST_ADDRESS = 0,
258
                        PORT_A_FIRST_BIT_NUMBER = 7,
259
                        PORT_A_LAST_ADDRESS = 255,
260
                        PORT_A_LOGICAL_RAM_DEPTH = 256,
261
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
262
                        PORT_B_ADDRESS_CLOCK = "clock0",
263
                        PORT_B_ADDRESS_WIDTH = 8,
264
                        PORT_B_DATA_OUT_CLEAR = "none",
265
                        PORT_B_DATA_OUT_CLOCK = "none",
266
                        PORT_B_DATA_WIDTH = 1,
267
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
268
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
269
                        PORT_B_FIRST_ADDRESS = 0,
270
                        PORT_B_FIRST_BIT_NUMBER = 7,
271
                        PORT_B_LAST_ADDRESS = 255,
272
                        PORT_B_LOGICAL_RAM_DEPTH = 256,
273
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
274
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
275
                        RAM_BLOCK_TYPE = "AUTO"
276
                );
277
        address_a_wire[7..0]    : WIRE;
278
        address_b_wire[7..0]    : WIRE;
279
 
280
BEGIN
281
        ram_block1a[7..0].clk0 = clock0;
282
        ram_block1a[7..0].portaaddr[] = ( address_a_wire[7..0]);
283
        ram_block1a[0].portadatain[] = ( data_a[0..0]);
284
        ram_block1a[1].portadatain[] = ( data_a[1..1]);
285
        ram_block1a[2].portadatain[] = ( data_a[2..2]);
286
        ram_block1a[3].portadatain[] = ( data_a[3..3]);
287
        ram_block1a[4].portadatain[] = ( data_a[4..4]);
288
        ram_block1a[5].portadatain[] = ( data_a[5..5]);
289
        ram_block1a[6].portadatain[] = ( data_a[6..6]);
290
        ram_block1a[7].portadatain[] = ( data_a[7..7]);
291
        ram_block1a[7..0].portawe = wren_a;
292
        ram_block1a[7..0].portbaddr[] = ( address_b_wire[7..0]);
293
        ram_block1a[7..0].portbrewe = B"11111111";
294
        address_a_wire[] = address_a[];
295
        address_b_wire[] = address_b[];
296
        q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
297
END;
298
--VALID FILE

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