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--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Stratix II" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=8 LPM_WIDTH=1 LPM_WIDTHS=3 data result sel

--VERSION_BEGIN 7.2SP3 cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ  VERSION_END

-- Copyright (C) 1991-2007 Altera Corporation

--  Your use of Altera Corporation's design tools, logic functions

--  and other software and tools, and its AMPP partner logic

--  functions, and any output files from any of the foregoing

--  (including device programming or simulation files), and any

--  associated documentation or information are expressly subject

--  to the terms and conditions of the Altera Program License

--  Subscription Agreement, Altera MegaCore Function License

--  Agreement, or other applicable license agreement, including,

--  without limitation, that your use is for the sole purpose of

--  programming logic devices manufactured by Altera and sold by

--  Altera or its authorized distributors.  Please refer to the

--  applicable agreement for further details.

--synthesis_resources = lut 3

SUBDESIGN mux_5oc

(

        data[7..0]      :       input;

        result[0..0]    :       output;

        sel[2..0]       :       input;

)

VARIABLE

        l1_w0_n0_mux_dataout    :       WIRE;

        l1_w0_n1_mux_dataout    :       WIRE;

        l1_w0_n2_mux_dataout    :       WIRE;

        l1_w0_n3_mux_dataout    :       WIRE;

        l2_w0_n0_mux_dataout    :       WIRE;

        l2_w0_n1_mux_dataout    :       WIRE;

        l3_w0_n0_mux_dataout    :       WIRE;

        data_wire[13..0]        : WIRE;

        sel_wire[2..0]  : WIRE;

BEGIN

        l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[1..1] # !(sel_wire[0..0]) & data_wire[0..0];

        l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[3..3] # !(sel_wire[0..0]) & data_wire[2..2];

        l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[5..5] # !(sel_wire[0..0]) & data_wire[4..4];

        l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[7..7] # !(sel_wire[0..0]) & data_wire[6..6];

        l2_w0_n0_mux_dataout = sel_wire[1..1] & data_wire[9..9] # !(sel_wire[1..1]) & data_wire[8..8];

        l2_w0_n1_mux_dataout = sel_wire[1..1] & data_wire[11..11] # !(sel_wire[1..1]) & data_wire[10..10];

        l3_w0_n0_mux_dataout = sel_wire[2..2] & data_wire[13..13] # !(sel_wire[2..2]) & data_wire[12..12];

        data_wire[] = ( l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);

        result[] = ( l3_w0_n0_mux_dataout);

        sel_wire[] = ( sel[2..0]);

END;

--VALID FILE