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[/] [loadbalancer/] [trunk/] [ethernet_parser.v.bak] - Blame information for rev 2
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atalla |
///////////////////////////////////////////////////////////////////////////////
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// $Id: ethernet_parser.v 1976 2007-07-20 00:59:57Z grg $
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//
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// Module: ethernet_parser.v
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// Project: NF2.1
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// Description: parses the Ethernet header for a 32 or 64 bit datapath
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//
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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module ethernet_parser
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#(parameter DATA_WIDTH = 64,
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parameter CTRL_WIDTH=DATA_WIDTH/8,
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parameter NUM_IQ_BITS = 3,
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parameter INPUT_ARBITER_STAGE_NUM = 2
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)
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(// --- Interface to the previous stage
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input [DATA_WIDTH-1:0] in_data,
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input [CTRL_WIDTH-1:0] in_ctrl,
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input in_wr,
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// --- Interface to output_port_lookup
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output [47:0] dst_mac,
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output [47:0] src_mac,
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output [15:0] ethertype,
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output eth_done,
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output [NUM_IQ_BITS-1:0] src_port,
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// --- Misc
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input reset,
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input clk
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);
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generate
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genvar i;
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if(DATA_WIDTH==64) begin: eth_parser_64bit
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ethernet_parser_64bit
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#(
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.NUM_IQ_BITS(NUM_IQ_BITS),
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.INPUT_ARBITER_STAGE_NUM(INPUT_ARBITER_STAGE_NUM))
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eth_parser
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(.in_data(in_data),
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.in_ctrl(in_ctrl),
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.in_wr(in_wr),
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.eth_done (eth_done),
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.src_port(src_port),
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.reset(reset),
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.clk(clk));
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end // block: eth_parser_64bit
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else if(DATA_WIDTH==32) begin: eth_parser_32bit
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ethernet_parser_32bit
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#(
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.NUM_IQ_BITS(NUM_IQ_BITS),
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.INPUT_ARBITER_STAGE_NUM(INPUT_ARBITER_STAGE_NUM))
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eth_parser
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(.in_data(in_data),
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.in_ctrl(in_ctrl),
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.in_wr(in_wr),
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.dst_mac (dst_mac),
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.src_mac(src_mac),
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.ethertype (ethertype),
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.eth_done (eth_done),
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.src_port(src_port),
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.reset(reset),
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.clk(clk));
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end // block: eth_parser_32bit
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endgenerate
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endmodule // ethernet_parser_64bit
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