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[/] [loadbalancer/] [trunk/] [ethernet_parser_64bit.v.bak] - Blame information for rev 2

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///////////////////////////////////////////////////////////////////////////////
// $Id: ethernet_parser_64bit.v 2201 2007-08-21 06:52:51Z jnaous $
//
// Module: ethernet_parser_64bit.v
// Project: NF2.1
// Description: parses the Ethernet header for a 64 bit datapath
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
  module ethernet_parser_64bit
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH=DATA_WIDTH/8,
      parameter NUM_IQ_BITS = 3,
      parameter INPUT_ARBITER_STAGE_NUM = 2
      )
   (// --- Interface to the previous stage
    input  [DATA_WIDTH-1:0]            in_data,
    input  [CTRL_WIDTH-1:0]            in_ctrl,
    input                              in_wr,
 
    // --- Interface to output_port_lookup
 
    output reg                         eth_done,
    output reg [NUM_IQ_BITS-1:0]       src_port,
 
    // --- Misc
 
    input                              reset,
    input                              clk
   );
 
 
   // ------------ Internal Params --------
 
   parameter NUM_STATES  = 3;
   parameter READ_WORD_1 = 1;
   parameter READ_WORD_2 = 2;
   parameter WAIT_EOP    = 4;
 
   // ------------- Regs/ wires -----------
 
   reg [NUM_STATES-1:0]                state;
   reg [NUM_STATES-1:0]                state_next;
 
 
   reg                                 eth_done_next;
   reg [NUM_IQ_BITS-1:0]               src_port_next;
 
   // ------------ Logic ----------------
 
   always @(*) begin
 
      eth_done_next    = eth_done;
      src_port_next    = src_port;
      state_next       = state;
      case(state)
        /* read the input source header and get the first word */
        READ_WORD_1: begin
           if(in_wr && in_ctrl==2'hFF) begin
              src_port_next = in_data[15 :0];
           end
           else if(in_wr && in_ctrl==0) begin
 
              state_next            = READ_WORD_2;
           end
        end // case: READ_WORD_1
 
        READ_WORD_2: begin
           if(in_wr) begin
 
              state_next            = WAIT_EOP;
              eth_done_next         = 1;
           end
        end
 
        WAIT_EOP: begin
           if(in_wr && in_ctrl!=0) begin
              eth_done_next   = 0;
              state_next      = READ_WORD_1;
           end
        end
      endcase // case(state)
   end // always @ (*)
 
   always @(posedge clk) begin
      if(reset) begin
 
         eth_done     <= 0;
         state        <= READ_WORD_1;
         src_port     <= 0;
      end
      else begin
 
         eth_done     <= eth_done_next;
         state        <= state_next;
         src_port     <= src_port_next;
      end // else: !if(reset)
   end // always @ (posedge clk)
 
endmodule // ethernet_parser_64bit

Line No.	Rev	Author	Line
1	2	atalla	`///////////////////////////////////////////////////////////////////////////////`
2			`// $Id: ethernet_parser_64bit.v 2201 2007-08-21 06:52:51Z jnaous $`
3			`//`
4			`// Module: ethernet_parser_64bit.v`
5			`// Project: NF2.1`
6			`// Description: parses the Ethernet header for a 64 bit datapath`
7			`//`
8			`///////////////////////////////////////////////////////////////////////////////`
9			`timescale 1ns/1ps
10			`module ethernet_parser_64bit`
11			`#(parameter DATA_WIDTH = 64,`
12			`parameter CTRL_WIDTH=DATA_WIDTH/8,`
13			`parameter NUM_IQ_BITS = 3,`
14			`parameter INPUT_ARBITER_STAGE_NUM = 2`
15			`)`
16			`(// --- Interface to the previous stage`
17			`input [DATA_WIDTH-1:0] in_data,`
18			`input [CTRL_WIDTH-1:0] in_ctrl,`
19			`input in_wr,`
20
21			`// --- Interface to output_port_lookup`
22
23			`output reg eth_done,`
24			`output reg [NUM_IQ_BITS-1:0] src_port,`
25
26			`// --- Misc`
27
28			`input reset,`
29			`input clk`
30			`);`
31
32
33			`// ------------ Internal Params --------`
34
35			`parameter NUM_STATES = 3;`
36			`parameter READ_WORD_1 = 1;`
37			`parameter READ_WORD_2 = 2;`
38			`parameter WAIT_EOP = 4;`
39
40			`// ------------- Regs/ wires -----------`
41
42			`reg [NUM_STATES-1:0] state;`
43			`reg [NUM_STATES-1:0] state_next;`
44
45
46			`reg eth_done_next;`
47			`reg [NUM_IQ_BITS-1:0] src_port_next;`
48
49			`// ------------ Logic ----------------`
50
51			`always @(*) begin`
52
53			`eth_done_next = eth_done;`
54			`src_port_next = src_port;`
55			`state_next = state;`
56			`case(state)`
57			`/* read the input source header and get the first word */`
58			`READ_WORD_1: begin`
59			`if(in_wr && in_ctrl==2'hFF) begin`
60			`src_port_next = in_data[15 :0];`
61			`end`
62			`else if(in_wr && in_ctrl==0) begin`
63
64			`state_next = READ_WORD_2;`
65			`end`
66			`end // case: READ_WORD_1`
67
68			`READ_WORD_2: begin`
69			`if(in_wr) begin`
70
71			`state_next = WAIT_EOP;`
72			`eth_done_next = 1;`
73			`end`
74			`end`
75
76			`WAIT_EOP: begin`
77			`if(in_wr && in_ctrl!=0) begin`
78			`eth_done_next = 0;`
79			`state_next = READ_WORD_1;`
80			`end`
81			`end`
82			`endcase // case(state)`
83			`end // always @ (*)`
84
85			`always @(posedge clk) begin`
86			`if(reset) begin`
87
88			`eth_done <= 0;`
89			`state <= READ_WORD_1;`
90			`src_port <= 0;`
91			`end`
92			`else begin`
93
94			`eth_done <= eth_done_next;`
95			`state <= state_next;`
96			`src_port <= src_port_next;`
97			`end // else: !if(reset)`
98			`end // always @ (posedge clk)`
99
100			`endmodule // ethernet_parser_64bit`

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[/] [loadbalancer/] [trunk/] [ethernet_parser_64bit.v.bak] - Blame information for rev 2