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[/] [loadbalancer/] [trunk/] [int2ext/] [int2ext.vhd.bak] - Blame information for rev 2

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--------------------------------------------------------
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use ieee.numeric_std.all;
        use IEEE.STD_LOGIC_ARITH.ALL;
        use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------
        ENTITY int2ext IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
                SIGNAL          in_data                            :    IN      STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
                SIGNAL          in_ctrl                            :    IN      STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                SIGNAL          in_wr                           :       IN              STD_LOGIC       ;
                SIGNAL          in_rdy                          :       OUT     STD_LOGIC       ;
 
                SIGNAL          out_data                        :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
                SIGNAL          out_ctrl                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                SIGNAL          out_wr                          :       OUT     STD_LOGIC       ;
                SIGNAL          out_rdy                            :    IN              STD_LOGIC       ;
--              SIGNAL          fifo_data_out                   :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
--              SIGNAL          latch_word_out                  :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
--              SIGNAL          fifo_ctrl_out                   :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                SIGNAL          reset                           :       IN              STD_LOGIC       ;
                SIGNAL          clk                             :       IN              STD_LOGIC
        );
        END ENTITY int2ext;
 
 ------------------------------------------------------
        ARCHITECTURE behavior OF int2ext IS
-------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
                                GENERIC(WIDTH :INTEGER := 72;
                                                MAX_DEPTH_BITS :INTEGER := 3);
                                PORT(
                                         SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         SIGNAL wr_en : IN STD_LOGIC;
                                         SIGNAL rd_en : IN STD_LOGIC;
                                         SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         SIGNAL full : OUT STD_LOGIC;
                                         SIGNAL nearly_full : OUT STD_LOGIC;
                                         SIGNAL empty : OUT STD_LOGIC;
                                         SIGNAL reset :IN STD_LOGIC;
                                         SIGNAL clk   :IN STD_LOGIC
                                );
                END COMPONENT;
-------COMPONENET SMALL FIFO
------COMPONENT vlan2ext
        COMPONENT vlan2ext IS
                GENERIC(DATA_WIDTH :INTEGER := 64;
                                CTRL_WIDTH :INTEGER := 8);
                                PORT(
                                        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
                                        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                                        SIGNAL          in_wr                           :       IN              STD_LOGIC       ;
                                        SIGNAL          exit_port                       :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                                        SIGNAL          done                            :       OUT     STD_LOGIC       ;
                                         --- Misc
                                        SIGNAL          reset                           :       IN              STD_LOGIC       ;
                                        SIGNAL          clk                             :       IN              STD_LOGIC
                                        );
        END COMPONENT;
------COMPONENT vlan2ext
------------ one hot encoding state definition
 
        TYPE state_type IS (IDLE, START, IN_MODULE_HDRS, WORD_1, WORD_2,WORD_3, IN_PACKET,LAST);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_NEXT : state_type;
 
------------end state machine definition
 
----------------------FIFO
          SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
          SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_rd_en : STD_LOGIC;
          SIGNAL in_fifo_go : STD_LOGIC;
          SIGNAL in_fifo_rd_en_p : STD_LOGIC;
      SIGNAL in_fifo_dout  : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_full : STD_LOGIC;
      SIGNAL in_fifo_nearly_full : STD_LOGIC;
      SIGNAL in_fifo_empty : STD_LOGIC;
------------------------------
          SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL ctrl_fifo_rd : STD_LOGIC;
      SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
      SIGNAL ctrl_fifo_full : STD_LOGIC;
      SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;
      SIGNAL ctrl_fifo_empty : STD_LOGIC;
--        SIGNAL cnt : INTEGER;
 
          SIGNAL                out_data_i                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
          SIGNAL                out_ctrl_i                      :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                out_wr_i                        :               STD_LOGIC       ;
          SIGNAL                exit_port                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                done                            :               STD_LOGIC       ;
          SIGNAL                words_cnt                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                words_cnt_ch            :               STD_LOGIC;
          SIGNAL                bytes_cnt                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                cnt                                     :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                last_ctrl                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                cnt_en                          :               STD_LOGIC       ;
          SIGNAL                cnt_rst                         :               STD_LOGIC       ;
          SIGNAL                header_rdy                      :               STD_LOGIC       ;
          SIGNAL                latch                           :               STD_LOGIC       ;
          SIGNAL                latch_word                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
          SIGNAL                latch_word_p                    :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
         SIGNAL                 fifo_data_p                     :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
 
---------------------------------------------------
        BEGIN
 
 
        ------PORT MAP open_header
        vlan2extr_Inst : vlan2ext
        GENERIC MAP (DATA_WIDTH  => 64,
                        CTRL_WIDTH => 8)
        PORT MAP(
                        in_data                         =>      in_data,
                        in_ctrl                         =>      in_ctrl ,
                in_wr                           =>      in_wr,
                        exit_port                       =>  exit_port,
                        done                            =>  done,
                reset                           =>      reset,
                clk                             =>      clk
        );
 
        ------PORT MAP open_header
 
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst1 :  small_fifo
                GENERIC MAP(WIDTH  => 72,
                                MAX_DEPTH_BITS  => 5)
                        PORT MAP(
                                  din =>in_fifo_in,
                                  wr_en =>in_wr,
                                  rd_en => in_fifo_rd_en,
                                  dout =>in_fifo_dout,
                                  full =>in_fifo_full,
                                  nearly_full =>in_fifo_nearly_full,
                                  empty => in_fifo_empty,
                                  reset => reset ,
                                  clk  => clk
                        );
 
 
 
-------PORT MAP SMALL FIFO
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst_ctrl :  small_fifo
        GENERIC MAP(WIDTH  => 8,
                        MAX_DEPTH_BITS  => 5)
                                PORT MAP(
                                  din =>exit_port,
                                  wr_en =>'0',--done,
                                  rd_en => ctrl_fifo_rd,
                                  dout =>ctrl_fifo_dout,
                                  full =>ctrl_fifo_full,
                                  nearly_full =>ctrl_fifo_nearly_full,
                                  empty => ctrl_fifo_empty,
                                  reset => reset ,
                                  clk  => clk
                                );
 
 
-----------------------
        in_fifo_in      <=         in_data & in_ctrl ;
                fifo_data       <=           in_fifo_dout(71 DOWNTO 8)    ;
                fifo_ctrl       <=         in_fifo_dout(7 DOWNTO 0)        ;
--              in_fifo_rd_en <=out_rdy AND (NOT in_fifo_empty) AND in_fifo_go;
--           fifo_rd <= ctrl_fifo_empty OR in_fifo_go;
                 in_rdy         <=        (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full)       ;
 
                PROCESS(clk,reset)
                BEGIN
                        IF (reset ='1') THEN
                                state <=IDLE;
                                ELSIF clk'EVENT AND clk ='1' THEN
                                state<=state_next;
                        END IF;
                END PROCESS;
 
--              out_cnt <= cnt;
PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)
        BEGIN
                                                        state_next                              <=         state;
                                                        out_data_i                              <=  	(OTHERS=>'0') ;
                                                        out_ctrl_i                              <=  	(OTHERS=>'0') ;
                                                        out_wr_i                                   <=   '0'     ;
                                                        ctrl_fifo_rd                    <=                '0'     ;
                                                        in_fifo_rd_en                   <=                '0'     ;
                                                        header_rdy                              <=                '0'     ;
 
                CASE state IS
                        WHEN IDLE =>
                           IF(ctrl_fifo_empty = '0' AND in_fifo_empty ='0' ) THEN
                                                   ctrl_fifo_rd                         <=        '1'     ;
                                                   in_fifo_rd_en                                <=        '1'     ;
                                                   state_next                             <=  START;
                                END IF;
                        WHEN START                      =>
 
                                                        header_rdy                              <=        '1'     ;
                                                        state_next                              <=  IN_MODULE_HDRS;
                        WHEN IN_MODULE_HDRS =>
 
                                                        IF ( out_rdy ='1'  ) THEN
                                                        out_data_i(55 downto 48)<=       ctrl_fifo_dout ;
                                                        out_data_i(39 downto 32)<=  words_cnt;
                                                        out_data_i(31 downto 16)<=      fifo_data(31 downto 16);
                                                        out_data_i(7 downto 0) <=  bytes_cnt;
                                                        out_ctrl_i                                 <=  X"FF" ;
                                                        out_wr_i                                    <=  '1' ;
                                                        cnt_en                                     <=  '1' ;
                                                        in_fifo_rd_en                           <=        '1'     ;
                                                        state_next              <=  WORD_1;
                                                        END IF;
 
 
                        WHEN WORD_1             =>
 
                                                        IF ( out_rdy ='1' AND in_fifo_empty ='0' ) THEN
                                                                        out_data_i                              <=  fifo_data;
                                                                        out_ctrl_i                              <=  X"00" ;
                                                                        out_wr_i                                <=  '1' ;
                                                                        in_fifo_rd_en                   <=        '1'     ;
                                                        state_next              <=  WORD_2;
                                                        END IF;
                        WHEN WORD_2             =>
                                                        IF (in_fifo_empty ='0' ) THEN
                                                        in_fifo_rd_en                   <=        '1'     ;
                                                        state_next              <=   WORD_3;
                                                        END IF;
 
                        WHEN WORD_3             =>
                                                        out_data_i(63 downto 32)<=   latch_word(63 downto 32);
                                                        out_data_i(31 downto 0) <=   fifo_data(63 downto 32);
                                                        IF ( out_rdy ='1' and in_fifo_empty ='0' ) THEN
                                                        latch                                   <=        '1'     ;
                                                        in_fifo_rd_en                   <=        '1'     ;
                                                        cnt_en                                  <=  '0' ;
                                                        out_wr_i                                <=        '1' ;
                                                        state_next              <=   IN_PACKET;
 
                                                    END IF;
--                      WHEN LATCH_P    =>
 
--                                                      IF (  in_fifo_empty ='0' ) THEN
--                                                      in_fifo_rd_en                   <=        '1'     ;
--                                                      state_next              <=   IN_PACKET;
--                                                  END IF;
 
 
                        WHEN IN_PACKET  =>
                                                                        out_data_i(63 downto 32)<=   latch_word(31 downto 0);
                                                                        out_data_i(31 downto 0) <=   fifo_data(63 downto 32);
 
                                                        IF out_rdy ='1' THEN
                                                                IF ( fifo_ctrl /= X"00" ) THEN
                                                                                        out_wr_i                                <=        '1' ;
                                                                                        IF (   words_cnt_ch='1') THEN
                                                                                                out_ctrl_i                              <=   last_ctrl ;
                                                                                                state_next               <= IDLE;
                                                                                        ELSE
                                                                                                state_next               <= LAST;
                                                                                        END IF;
                                                                ELSIF( in_fifo_empty = '0' )THEN
                                                                        out_wr_i                        <=  '1' ;
                                                                        in_fifo_rd_en           <=        '1'     ;
                                                                END IF;
                                                        END IF;
 
                        WHEN LAST =>            out_data_i(63 downto 32)<=   latch_word(31 downto 0);
                                                                out_data_i(31 downto 0) <=   fifo_data(63 downto 32);
                                                                out_ctrl_i                              <=   last_ctrl ;
                                                                out_wr_i                                <=        '1' ;
                                                                state_next               <= IDLE;
 
                        END CASE;
        END PROCESS;
---------------Register output
 
                PROCESS(clk,reset)
                BEGIN
 
                        IF clk'EVENT AND clk ='1' THEN
                                        IF header_rdy = '1' THEN
                                                        bytes_cnt <= fifo_data(7 downto 0)- X"04";
                                        IF (fifo_data(15 downto 0)-X"0004") > (fifo_data(45 downto 32)&"000" - X"0008") THEN
                                                                        words_cnt       <=        fifo_data(39 downto 32)  ;
                                                                        words_cnt_ch <= '0';
                                                        ELSE
                                                                        words_cnt       <=        fifo_data(39 downto 32) - '1' ;
                                                                        words_cnt_ch <= '1';
                                                        END IF;
                                        END IF;
                                                IF in_fifo_rd_en='1' THEN
                                                latch_word <= fifo_data;
                                                END IF;
                                           fifo_data_p<= fifo_data;
                                   latch_word_p <=latch_word;
                        END IF;
                END PROCESS;
        WITH bytes_cnt(2 DOWNTO 0)SELECT
                        last_ctrl <= "00000010" WHEN "111",
                                                 "00000100" WHEN "110",
                                                 "00001000" WHEN "101",
                                                 "00010000" WHEN "100",
                                                 "00100000" WHEN "011",
                                                 "01000000" WHEN "010",
                                                 "10000000" WHEN "001",
                                                 "00000001" WHEN others;
 
 
 
                PROCESS(clk,reset)
                BEGIN
--
                        IF clk'EVENT AND clk ='1' THEN
                                                                        out_data                                <=        out_data_i;
                                                                        out_ctrl                                <=        out_ctrl_i;
                                                                        out_wr                          <=        out_wr_i;
                        END IF;
                END PROCESS;
--              fifo_ctrl_out <=fifo_ctrl;
--              fifo_data_out <=fifo_data;
--              latch_word_out <= latch_word;
END behavior;
 

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Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [int2ext/] [int2ext.vhd.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2			`LIBRARY IEEE;`
3			`USE IEEE.STD_LOGIC_1164.ALL;`
4			`use ieee.numeric_std.all;`
5			`use IEEE.STD_LOGIC_ARITH.ALL;`
6			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
7
8			`-------------------------------`
9			`ENTITY int2ext IS`
10			`GENERIC(DATA_WIDTH :INTEGER := 64;`
11			`CTRL_WIDTH :INTEGER := 8);`
12			`PORT(`
13			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
14			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
15			`SIGNAL in_wr : IN STD_LOGIC ;`
16			`SIGNAL in_rdy : OUT STD_LOGIC ;`
17
18			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
19			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
20			`SIGNAL out_wr : OUT STD_LOGIC ;`
21			`SIGNAL out_rdy : IN STD_LOGIC ;`
22			`-- SIGNAL fifo_data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
23			`-- SIGNAL latch_word_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
24			`-- SIGNAL fifo_ctrl_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
25			`SIGNAL reset : IN STD_LOGIC ;`
26			`SIGNAL clk : IN STD_LOGIC`
27			`);`
28			`END ENTITY int2ext;`
29
30			`------------------------------------------------------`
31			`ARCHITECTURE behavior OF int2ext IS`
32			`-------COMPONENET SMALL FIFO`
33			`COMPONENT small_fifo IS`
34			`GENERIC(WIDTH :INTEGER := 72;`
35			`MAX_DEPTH_BITS :INTEGER := 3);`
36			`PORT(`
37			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);`
38			`SIGNAL wr_en : IN STD_LOGIC;`
39			`SIGNAL rd_en : IN STD_LOGIC;`
40			`SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);`
41			`SIGNAL full : OUT STD_LOGIC;`
42			`SIGNAL nearly_full : OUT STD_LOGIC;`
43			`SIGNAL empty : OUT STD_LOGIC;`
44			`SIGNAL reset :IN STD_LOGIC;`
45			`SIGNAL clk :IN STD_LOGIC`
46			`);`
47			`END COMPONENT;`
48			`-------COMPONENET SMALL FIFO`
49			`------COMPONENT vlan2ext`
50			`COMPONENT vlan2ext IS`
51			`GENERIC(DATA_WIDTH :INTEGER := 64;`
52			`CTRL_WIDTH :INTEGER := 8);`
53			`PORT(`
54			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
55			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
56			`SIGNAL in_wr : IN STD_LOGIC ;`
57			`SIGNAL exit_port : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
58			`SIGNAL done : OUT STD_LOGIC ;`
59			`--- Misc`
60			`SIGNAL reset : IN STD_LOGIC ;`
61			`SIGNAL clk : IN STD_LOGIC`
62			`);`
63			`END COMPONENT;`
64			`------COMPONENT vlan2ext`
65			`------------ one hot encoding state definition`
66
67			`TYPE state_type IS (IDLE, START, IN_MODULE_HDRS, WORD_1, WORD_2,WORD_3, IN_PACKET,LAST);`
68			`ATTRIBUTE enum_encoding: STRING;`
69			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
70
71			`SIGNAL state, state_NEXT : state_type;`
72
73			`------------end state machine definition`
74
75			`----------------------FIFO`
76			`SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);`
77			`SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);`
78			`SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
79			`SIGNAL in_fifo_rd_en : STD_LOGIC;`
80			`SIGNAL in_fifo_go : STD_LOGIC;`
81			`SIGNAL in_fifo_rd_en_p : STD_LOGIC;`
82			`SIGNAL in_fifo_dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
83			`SIGNAL in_fifo_full : STD_LOGIC;`
84			`SIGNAL in_fifo_nearly_full : STD_LOGIC;`
85			`SIGNAL in_fifo_empty : STD_LOGIC;`
86			`------------------------------`
87			`SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
88			`SIGNAL ctrl_fifo_rd : STD_LOGIC;`
89			`SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);`
90			`SIGNAL ctrl_fifo_full : STD_LOGIC;`
91			`SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;`
92			`SIGNAL ctrl_fifo_empty : STD_LOGIC;`
93			`-- SIGNAL cnt : INTEGER;`
94
95			`SIGNAL out_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
96			`SIGNAL out_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
97			`SIGNAL out_wr_i : STD_LOGIC ;`
98			`SIGNAL exit_port : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
99			`SIGNAL done : STD_LOGIC ;`
100			`SIGNAL words_cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
101			`SIGNAL words_cnt_ch : STD_LOGIC;`
102			`SIGNAL bytes_cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
103			`SIGNAL cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
104			`SIGNAL last_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
105			`SIGNAL cnt_en : STD_LOGIC ;`
106			`SIGNAL cnt_rst : STD_LOGIC ;`
107			`SIGNAL header_rdy : STD_LOGIC ;`
108			`SIGNAL latch : STD_LOGIC ;`
109			`SIGNAL latch_word : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
110			`SIGNAL latch_word_p : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
111			`SIGNAL fifo_data_p : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
112
113			`---------------------------------------------------`
114			`BEGIN`
115
116
117			`------PORT MAP open_header`
118			`vlan2extr_Inst : vlan2ext`
119			`GENERIC MAP (DATA_WIDTH => 64,`
120			`CTRL_WIDTH => 8)`
121			`PORT MAP(`
122			`in_data => in_data,`
123			`in_ctrl => in_ctrl ,`
124			`in_wr => in_wr,`
125			`exit_port => exit_port,`
126			`done => done,`
127			`reset => reset,`
128			`clk => clk`
129			`);`
130
131			`------PORT MAP open_header`
132
133			`-------PORT MAP SMALL FIFO DATA`
134			`small_fifo_Inst1 : small_fifo`
135			`GENERIC MAP(WIDTH => 72,`
136			`MAX_DEPTH_BITS => 5)`
137			`PORT MAP(`
138			`din =>in_fifo_in,`
139			`wr_en =>in_wr,`
140			`rd_en => in_fifo_rd_en,`
141			`dout =>in_fifo_dout,`
142			`full =>in_fifo_full,`
143			`nearly_full =>in_fifo_nearly_full,`
144			`empty => in_fifo_empty,`
145			`reset => reset ,`
146			`clk => clk`
147			`);`
148
149
150
151			`-------PORT MAP SMALL FIFO`
152			`-------PORT MAP SMALL FIFO DATA`
153			`small_fifo_Inst_ctrl : small_fifo`
154			`GENERIC MAP(WIDTH => 8,`
155			`MAX_DEPTH_BITS => 5)`
156			`PORT MAP(`
157			`din =>exit_port,`
158			`wr_en =>'0',--done,`
159			`rd_en => ctrl_fifo_rd,`
160			`dout =>ctrl_fifo_dout,`
161			`full =>ctrl_fifo_full,`
162			`nearly_full =>ctrl_fifo_nearly_full,`
163			`empty => ctrl_fifo_empty,`
164			`reset => reset ,`
165			`clk => clk`
166			`);`
167
168
169			`-----------------------`
170			`in_fifo_in <= in_data & in_ctrl ;`
171			`fifo_data <= in_fifo_dout(71 DOWNTO 8) ;`
172			`fifo_ctrl <= in_fifo_dout(7 DOWNTO 0) ;`
173			`-- in_fifo_rd_en <=out_rdy AND (NOT in_fifo_empty) AND in_fifo_go;`
174			`-- fifo_rd <= ctrl_fifo_empty OR in_fifo_go;`
175			`in_rdy <= (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full) ;`
176
177			`PROCESS(clk,reset)`
178			`BEGIN`
179			`IF (reset ='1') THEN`
180			`state <=IDLE;`
181			`ELSIF clk'EVENT AND clk ='1' THEN`
182			`state<=state_next;`
183			`END IF;`
184			`END PROCESS;`
185
186			`-- out_cnt <= cnt;`
187			`PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)`
188			`BEGIN`
189			`state_next <= state;`
190			`out_data_i <= (OTHERS=>'0') ;`
191			`out_ctrl_i <= (OTHERS=>'0') ;`
192			`out_wr_i <= '0' ;`
193			`ctrl_fifo_rd <= '0' ;`
194			`in_fifo_rd_en <= '0' ;`
195			`header_rdy <= '0' ;`
196
197			`CASE state IS`
198			`WHEN IDLE =>`
199			`IF(ctrl_fifo_empty = '0' AND in_fifo_empty ='0' ) THEN`
200			`ctrl_fifo_rd <= '1' ;`
201			`in_fifo_rd_en <= '1' ;`
202			`state_next <= START;`
203			`END IF;`
204			`WHEN START =>`
205
206			`header_rdy <= '1' ;`
207			`state_next <= IN_MODULE_HDRS;`
208			`WHEN IN_MODULE_HDRS =>`
209
210			`IF ( out_rdy ='1' ) THEN`
211			`out_data_i(55 downto 48)<= ctrl_fifo_dout ;`
212			`out_data_i(39 downto 32)<= words_cnt;`
213			`out_data_i(31 downto 16)<= fifo_data(31 downto 16);`
214			`out_data_i(7 downto 0) <= bytes_cnt;`
215			`out_ctrl_i <= X"FF" ;`
216			`out_wr_i <= '1' ;`
217			`cnt_en <= '1' ;`
218			`in_fifo_rd_en <= '1' ;`
219			`state_next <= WORD_1;`
220			`END IF;`
221
222
223			`WHEN WORD_1 =>`
224
225			`IF ( out_rdy ='1' AND in_fifo_empty ='0' ) THEN`
226			`out_data_i <= fifo_data;`
227			`out_ctrl_i <= X"00" ;`
228			`out_wr_i <= '1' ;`
229			`in_fifo_rd_en <= '1' ;`
230			`state_next <= WORD_2;`
231			`END IF;`
232			`WHEN WORD_2 =>`
233			`IF (in_fifo_empty ='0' ) THEN`
234			`in_fifo_rd_en <= '1' ;`
235			`state_next <= WORD_3;`
236			`END IF;`
237
238			`WHEN WORD_3 =>`
239			`out_data_i(63 downto 32)<= latch_word(63 downto 32);`
240			`out_data_i(31 downto 0) <= fifo_data(63 downto 32);`
241			`IF ( out_rdy ='1' and in_fifo_empty ='0' ) THEN`
242			`latch <= '1' ;`
243			`in_fifo_rd_en <= '1' ;`
244			`cnt_en <= '0' ;`
245			`out_wr_i <= '1' ;`
246			`state_next <= IN_PACKET;`
247
248			`END IF;`
249			`-- WHEN LATCH_P =>`
250
251			`-- IF ( in_fifo_empty ='0' ) THEN`
252			`-- in_fifo_rd_en <= '1' ;`
253			`-- state_next <= IN_PACKET;`
254			`-- END IF;`
255
256
257			`WHEN IN_PACKET =>`
258			`out_data_i(63 downto 32)<= latch_word(31 downto 0);`
259			`out_data_i(31 downto 0) <= fifo_data(63 downto 32);`
260
261			`IF out_rdy ='1' THEN`
262			`IF ( fifo_ctrl /= X"00" ) THEN`
263			`out_wr_i <= '1' ;`
264			`IF ( words_cnt_ch='1') THEN`
265			`out_ctrl_i <= last_ctrl ;`
266			`state_next <= IDLE;`
267			`ELSE`
268			`state_next <= LAST;`
269			`END IF;`
270			`ELSIF( in_fifo_empty = '0' )THEN`
271			`out_wr_i <= '1' ;`
272			`in_fifo_rd_en <= '1' ;`
273			`END IF;`
274			`END IF;`
275
276			`WHEN LAST => out_data_i(63 downto 32)<= latch_word(31 downto 0);`
277			`out_data_i(31 downto 0) <= fifo_data(63 downto 32);`
278			`out_ctrl_i <= last_ctrl ;`
279			`out_wr_i <= '1' ;`
280			`state_next <= IDLE;`
281
282			`END CASE;`
283			`END PROCESS;`
284			`---------------Register output`
285
286			`PROCESS(clk,reset)`
287			`BEGIN`
288
289			`IF clk'EVENT AND clk ='1' THEN`
290			`IF header_rdy = '1' THEN`
291			`bytes_cnt <= fifo_data(7 downto 0)- X"04";`
292			`IF (fifo_data(15 downto 0)-X"0004") > (fifo_data(45 downto 32)&"000" - X"0008") THEN`
293			`words_cnt <= fifo_data(39 downto 32) ;`
294			`words_cnt_ch <= '0';`
295			`ELSE`
296			`words_cnt <= fifo_data(39 downto 32) - '1' ;`
297			`words_cnt_ch <= '1';`
298			`END IF;`
299			`END IF;`
300			`IF in_fifo_rd_en='1' THEN`
301			`latch_word <= fifo_data;`
302			`END IF;`
303			`fifo_data_p<= fifo_data;`
304			`latch_word_p <=latch_word;`
305			`END IF;`
306			`END PROCESS;`
307			`WITH bytes_cnt(2 DOWNTO 0)SELECT`
308			`last_ctrl <= "00000010" WHEN "111",`
309			`"00000100" WHEN "110",`
310			`"00001000" WHEN "101",`
311			`"00010000" WHEN "100",`
312			`"00100000" WHEN "011",`
313			`"01000000" WHEN "010",`
314			`"10000000" WHEN "001",`
315			`"00000001" WHEN others;`
316
317
318
319			`PROCESS(clk,reset)`
320			`BEGIN`
321			`--`
322			`IF clk'EVENT AND clk ='1' THEN`
323			`out_data <= out_data_i;`
324			`out_ctrl <= out_ctrl_i;`
325			`out_wr <= out_wr_i;`
326			`END IF;`
327			`END PROCESS;`
328			`-- fifo_ctrl_out <=fifo_ctrl;`
329			`-- fifo_data_out <=fifo_data;`
330			`-- latch_word_out <= latch_word;`
331			`END behavior;`
332