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[/] [loadbalancer/] [trunk/] [int2ext/] [int2ext_top.vhd.bak] - Blame information for rev 2

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--------------------------------------------------------
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use ieee.numeric_std.all;
        use IEEE.STD_LOGIC_ARITH.ALL;
        use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------
        ENTITY int2ext_top IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
                SIGNAL          in_data                            :    IN      STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
                SIGNAL          in_ctrl                            :    IN      STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                SIGNAL          in_wr                           :       IN              STD_LOGIC       ;
                SIGNAL          in_rdy                          :       OUT     STD_LOGIC       ;
 
                SIGNAL          out_data                        :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
                SIGNAL          out_ctrl                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                SIGNAL          out_wr                          :       OUT     STD_LOGIC       ;
                SIGNAL          out_rdy                            :    IN              STD_LOGIC       ;
--              SIGNAL          fifo_data_out                   :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
--              SIGNAL          latch_word_out                  :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
--              SIGNAL          fifo_ctrl_out                   :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                SIGNAL      en                                  : IN STD_LOGIC;
                SIGNAL          reset                           :       IN              STD_LOGIC       ;
                SIGNAL          clk                             :       IN              STD_LOGIC
        );
        END ENTITY int2ext_top;
 
 ------------------------------------------------------
        ARCHITECTURE behavior OF int2ext_top IS
-------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
                                GENERIC(WIDTH :INTEGER := 72;
                                                MAX_DEPTH_BITS :INTEGER := 3);
                                PORT(
                                         SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         SIGNAL wr_en : IN STD_LOGIC;
                                         SIGNAL rd_en : IN STD_LOGIC;
                                         SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         SIGNAL full : OUT STD_LOGIC;
                                         SIGNAL nearly_full : OUT STD_LOGIC;
                                         SIGNAL empty : OUT STD_LOGIC;
                                         SIGNAL reset :IN STD_LOGIC;
                                         SIGNAL clk   :IN STD_LOGIC
                                );
                END COMPONENT;
-------COMPONENET SMALL FIFO
------COMPONENT vlan2ext
        COMPONENT vlan2ext IS
                GENERIC(DATA_WIDTH :INTEGER := 64;
                                CTRL_WIDTH :INTEGER := 8);
                                PORT(
                                        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
                                        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                                        SIGNAL          in_wr                           :       IN              STD_LOGIC       ;
                                        SIGNAL          exit_port                       :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                                        SIGNAL          done                            :       OUT     STD_LOGIC       ;
                                         --- Misc
                                        SIGNAL          reset                           :       IN              STD_LOGIC       ;
                                        SIGNAL          clk                             :       IN              STD_LOGIC
                                        );
        END COMPONENT;
------COMPONENT vlan2ext
------------ one hot encoding state definition
 
        TYPE state_type IS (IDLE, START, IN_MODULE_HDRS, WORD_1, WORD_2,WORD_3, IN_PACKET,LAST);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_NEXT : state_type;
 
------------end state machine definition
 
----------------------FIFO
          SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
          SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_rd_en : STD_LOGIC;
          SIGNAL in_fifo_go : STD_LOGIC;
          SIGNAL in_fifo_rd_en_p : STD_LOGIC;
      SIGNAL in_fifo_dout  : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_full : STD_LOGIC;
      SIGNAL in_fifo_nearly_full : STD_LOGIC;
      SIGNAL in_fifo_empty : STD_LOGIC;
------------------------------
          SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL ctrl_fifo_rd : STD_LOGIC;
      SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
      SIGNAL ctrl_fifo_full : STD_LOGIC;
      SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;
      SIGNAL ctrl_fifo_empty : STD_LOGIC;
--        SIGNAL cnt : INTEGER;
 
          SIGNAL                out_data_i                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
          SIGNAL                out_ctrl_i                      :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                out_wr_i                        :               STD_LOGIC       ;
          SIGNAL                in_data_i                       :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
          SIGNAL                in_ctrl_i                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                in_fifo_in_i            :               STD_LOGIC_VECTOR(71 DOWNTO 0)   ;
          SIGNAL                wr_en_i                         :               STD_LOGIC       ;
          SIGNAL                exit_port                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                done                            :               STD_LOGIC       ;
          SIGNAL                words_cnt                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                words_cnt_ch            :               STD_LOGIC;
          SIGNAL                bytes_cnt                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                cnt                                     :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                last_ctrl                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
          SIGNAL                cnt_en                          :               STD_LOGIC       ;
          SIGNAL                cnt_rst                         :               STD_LOGIC       ;
          SIGNAL                header_rdy                      :               STD_LOGIC       ;
          SIGNAL                latch                           :               STD_LOGIC       ;
          SIGNAL                latch_word                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
          SIGNAL                latch_word_p                    :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
          SIGNAL                fifo_data_p                     :               STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
          SIGNAL                wr_en                           : STD_LOGIC;
         SIGNAL                 out_wr_t_i                              : STD_LOGIC;
---------------------------------------------------
        BEGIN
 
 
        ------PORT MAP open_header
        vlan2extr_Inst : vlan2ext
        GENERIC MAP (DATA_WIDTH  => 64,
                        CTRL_WIDTH => 8)
        PORT MAP(
                        in_data                            =>   in_data_i,
                        in_ctrl                            => in_ctrl_i ,
                in_wr                           =>      wr_en_i,
                        exit_port                       =>  exit_port,
                        done                               =>  done,
                reset                           =>      reset,
                clk                             =>      clk
        );
 
        ------PORT MAP open_header
 
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst1 :  small_fifo
                GENERIC MAP(WIDTH  => 72,
                                MAX_DEPTH_BITS  => 5)
                        PORT MAP(
                                  din =>in_fifo_in_i,
                                  wr_en =>wr_en_i,
                                  rd_en => in_fifo_rd_en,
                                  dout =>in_fifo_dout,
                                  full =>in_fifo_full,
                                  nearly_full =>in_fifo_nearly_full,
                                  empty => in_fifo_empty,
                                  reset => reset ,
                                  clk  => clk
                        );
 
 
 
-------PORT MAP SMALL FIFO
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst_ctrl :  small_fifo
        GENERIC MAP(WIDTH  => 8,
                        MAX_DEPTH_BITS  => 5)
                                PORT MAP(
                                  din =>exit_port,
                                  wr_en => done,
                                  rd_en => ctrl_fifo_rd,
                                  dout =>ctrl_fifo_dout,
                                  full =>ctrl_fifo_full,
                                  nearly_full =>ctrl_fifo_nearly_full,
                                  empty => ctrl_fifo_empty,
                                  reset => reset ,
                                  clk  => clk
                                );
 
 
-----------------------
 
                PROCESS(clk,reset)
                BEGIN
                                IF clk'EVENT AND clk ='1' THEN
                                in_fifo_in_i    <=                 in_fifo_in;
                                wr_en_i                 <=          wr_en;
                                in_data_i               <=                 in_data;
                                in_ctrl_i               <=                in_ctrl;
                        END IF;
                END PROCESS;
        in_fifo_in      <=         in_data & in_ctrl ;
                fifo_data        <=        in_fifo_dout(71 DOWNTO 8)    ;
                fifo_ctrl       <=         in_fifo_dout(7 DOWNTO 0)        ;
--              in_fifo_rd_en <=out_rdy AND (NOT in_fifo_empty) AND in_fifo_go;
--           fifo_rd <= ctrl_fifo_empty OR in_fifo_go;
                 in_rdy         <=        (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full)       ;
                wr_en  <= en  AND in_wr;
                PROCESS(clk,reset)
                BEGIN
                        IF (reset ='1') THEN
                                state <=IDLE;
                                ELSIF clk'EVENT AND clk ='1' THEN
                                state<=state_next;
                                in_fifo_rd_en_p <= in_fifo_rd_en;
                        END IF;
                END PROCESS;
 
--              out_cnt <= cnt;
PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)
        BEGIN
                                                        state_next                              <=         state;
                                                        out_wr_i                                <=                '0';
                                                        ctrl_fifo_rd                    <=                '0'     ;
                                                        in_fifo_rd_en                   <=                '0'     ;
                                                        header_rdy                              <=                '0'     ;
 
                CASE state IS
                        WHEN IDLE =>
                           IF(ctrl_fifo_empty = '0'  ) THEN
                                                   ctrl_fifo_rd                         <=        '1'     ;
                                                   in_fifo_rd_en                        <=        '1'     ;
                                                   state_next                            <=  START;
                                END IF;
                        WHEN START                      =>
 
                                                        header_rdy                              <=        '1'     ;
                                                        state_next                              <=  IN_MODULE_HDRS;
                        WHEN IN_MODULE_HDRS =>
 
                                                        IF(out_rdy = '1'  ) THEN
                                                                IF (fifo_ctrl=X"FF")    THEN
                                                                        out_data_i                      <= fifo_data        ;
                                                                        out_ctrl_i                      <= fifo_ctrl;
                                                                END IF;
                                                        out_wr_i                                <=        '1';
                                                        in_fifo_rd_en                   <=        '1'     ;
                                                        state_next              <=      WORD_1;
                                                        END IF;
 
 
                        WHEN WORD_1             =>
 
                                                IF(out_rdy = '1'  AND   in_fifo_empty ='0') THEN
 
                                                        out_wr_i                                <=        '1';
                                                        in_fifo_rd_en                   <=        '1'     ;
                                                        out_data_i                              <= fifo_data        ;
                                                        out_ctrl_i                              <= fifo_ctrl;
                                                        state_next              <=  WORD_2;
                                                        END IF;
                        WHEN WORD_2             =>IF(out_rdy = '1'  AND   in_fifo_empty ='0') THEN
 
                                                        out_wr_i                                <=        '1';
                                                        in_fifo_rd_en                   <=        '1'     ;
                                                        out_data_i                              <= fifo_data        ;
                                                        out_ctrl_i                              <= fifo_ctrl;
                                                        state_next              <=  WORD_3;
                                                        END IF;
 
                        WHEN WORD_3             =>
                                                        IF(out_rdy = '1'  AND   in_fifo_empty ='0') THEN
                                                        out_wr_i                                <=        '1';
                                                        in_fifo_rd_en                   <=        '1'     ;
                                                        out_data_i                              <= fifo_data        ;
                                                        out_ctrl_i                              <= fifo_ctrl;
                                                        state_next              <=  IN_PACKET;
                                                        END IF;
 
 
                        WHEN IN_PACKET  =>
 
 
                                                        IF ( fifo_ctrl /= X"00" ) THEN
 
                                                                                IF (   out_rdy = '1' ) THEN
                                                                                        state_next               <= IDLE;
--                                                                                      ELSE
--                                                                                              state_next               <= LAST;
                                                                                END IF;
                                                        ELSIF(out_rdy = '1'  AND   in_fifo_empty ='0') THEN
                                                                out_wr_i                                <=        '1';
                                                                in_fifo_rd_en                   <=        '1'     ;
                                                                out_data_i                              <= fifo_data        ;
                                                                out_ctrl_i                              <= fifo_ctrl;
                                                                state_next              <=  IN_PACKET;
                                                        END IF;
 
                        WHEN LAST =>
                                                                state_next               <= IDLE;
 
                        END CASE;
        END PROCESS;
---------------Register output
--
--
--      WITH state SELECT
--              out_data_i <=
--              X"00" & ctrl_fifo_dout & X"00"& words_cnt & fifo_data(31 downto 16) & X"00"& bytes_cnt WHEN  IN_MODULE_HDRS,
--              fifo_data WHEN WORD_1,
--              latch_word(63 downto 32) &  fifo_data(63 downto 32)WHEN WORD_3,
--              latch_word(31 downto 0)  &  fifo_data(63 downto 32) WHEN  IN_PACKET | LAST,
--              (OTHERS=>'0') WHEN OTHERS;
--
--
--      out_ctrl_i <= X"FF" when state = IN_MODULE_HDRS else
--                                last_ctrl  when state = IN_PACKET AND fifo_ctrl /= X"00" AND words_cnt_ch='1' else
--                                last_ctrl  when state = LAST else
--                                X"00" ;
--      WITH state SELECT
--              out_wr_i <=
--              out_rdy  WHEN  IN_MODULE_HDRS,
--              in_fifo_rd_en_p WHEN WORD_1,
--              in_fifo_rd_en_p WHEN WORD_3,
--              in_fifo_rd_en_p   WHEN  IN_PACKET ,
--               '1'  WHEN LAST,
--              '0' WHEN OTHERS;
----    out_wr_t_i      <=     word_cnt_up when word_cnt >= 1  AND word_cnt <= 21 else
----                                                             '0';
--              PROCESS(clk,reset)
--              BEGIN
--
--                      IF clk'EVENT AND clk ='1' THEN
--                                      IF header_rdy = '1' THEN
--                                                      bytes_cnt <= fifo_data(7 downto 0)- X"04";
--                                      IF (fifo_data(15 downto 0)-X"0004") > (fifo_data(45 downto 32)&"000" - X"0008") THEN
--                                                                      words_cnt       <=        fifo_data(39 downto 32)  ;
--                                                                      words_cnt_ch <= '0';
--                                                      ELSE
--                                                                      words_cnt       <=        fifo_data(39 downto 32) - '1' ;
--                                                                      words_cnt_ch <= '1';
--                                                      END IF;
--                                      END IF;
--                                              IF in_fifo_rd_en='1' THEN
--                                              latch_word <= fifo_data;
--                                              END IF;
--
--                      END IF;
--              END PROCESS;
--      WITH bytes_cnt(2 DOWNTO 0)SELECT
--                      last_ctrl <= "00000010" WHEN "111",
--                                               "00000100" WHEN "110",
--                                               "00001000" WHEN "101",
--                                               "00010000" WHEN "100",
--                                               "00100000" WHEN "011",
--                                               "01000000" WHEN "010",
--                                               "10000000" WHEN "001",
--                                               "00000001" WHEN others;
--
--
--
                PROCESS(clk,reset)
                BEGIN
--
                        IF clk'EVENT AND clk ='1' THEN
                                                                        out_data                                <=        out_data_i;
                                                                        out_ctrl                                <=        out_ctrl_i;
                                                                        out_wr                                  <=        out_wr_i;
                        END IF;
                END PROCESS;
--              fifo_ctrl_out <=fifo_ctrl;
--              fifo_data_out <=fifo_data;
--              latch_word_out <= latch_word;
END behavior;
 

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Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [int2ext/] [int2ext_top.vhd.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2			`LIBRARY IEEE;`
3			`USE IEEE.STD_LOGIC_1164.ALL;`
4			`use ieee.numeric_std.all;`
5			`use IEEE.STD_LOGIC_ARITH.ALL;`
6			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
7
8			`-------------------------------`
9			`ENTITY int2ext_top IS`
10			`GENERIC(DATA_WIDTH :INTEGER := 64;`
11			`CTRL_WIDTH :INTEGER := 8);`
12			`PORT(`
13			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
14			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
15			`SIGNAL in_wr : IN STD_LOGIC ;`
16			`SIGNAL in_rdy : OUT STD_LOGIC ;`
17
18			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
19			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
20			`SIGNAL out_wr : OUT STD_LOGIC ;`
21			`SIGNAL out_rdy : IN STD_LOGIC ;`
22			`-- SIGNAL fifo_data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
23			`-- SIGNAL latch_word_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
24			`-- SIGNAL fifo_ctrl_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
25			`SIGNAL en : IN STD_LOGIC;`
26			`SIGNAL reset : IN STD_LOGIC ;`
27			`SIGNAL clk : IN STD_LOGIC`
28			`);`
29			`END ENTITY int2ext_top;`
30
31			`------------------------------------------------------`
32			`ARCHITECTURE behavior OF int2ext_top IS`
33			`-------COMPONENET SMALL FIFO`
34			`COMPONENT small_fifo IS`
35			`GENERIC(WIDTH :INTEGER := 72;`
36			`MAX_DEPTH_BITS :INTEGER := 3);`
37			`PORT(`
38			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);`
39			`SIGNAL wr_en : IN STD_LOGIC;`
40			`SIGNAL rd_en : IN STD_LOGIC;`
41			`SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);`
42			`SIGNAL full : OUT STD_LOGIC;`
43			`SIGNAL nearly_full : OUT STD_LOGIC;`
44			`SIGNAL empty : OUT STD_LOGIC;`
45			`SIGNAL reset :IN STD_LOGIC;`
46			`SIGNAL clk :IN STD_LOGIC`
47			`);`
48			`END COMPONENT;`
49			`-------COMPONENET SMALL FIFO`
50			`------COMPONENT vlan2ext`
51			`COMPONENT vlan2ext IS`
52			`GENERIC(DATA_WIDTH :INTEGER := 64;`
53			`CTRL_WIDTH :INTEGER := 8);`
54			`PORT(`
55			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
56			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
57			`SIGNAL in_wr : IN STD_LOGIC ;`
58			`SIGNAL exit_port : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
59			`SIGNAL done : OUT STD_LOGIC ;`
60			`--- Misc`
61			`SIGNAL reset : IN STD_LOGIC ;`
62			`SIGNAL clk : IN STD_LOGIC`
63			`);`
64			`END COMPONENT;`
65			`------COMPONENT vlan2ext`
66			`------------ one hot encoding state definition`
67
68			`TYPE state_type IS (IDLE, START, IN_MODULE_HDRS, WORD_1, WORD_2,WORD_3, IN_PACKET,LAST);`
69			`ATTRIBUTE enum_encoding: STRING;`
70			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
71
72			`SIGNAL state, state_NEXT : state_type;`
73
74			`------------end state machine definition`
75
76			`----------------------FIFO`
77			`SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);`
78			`SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);`
79			`SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
80			`SIGNAL in_fifo_rd_en : STD_LOGIC;`
81			`SIGNAL in_fifo_go : STD_LOGIC;`
82			`SIGNAL in_fifo_rd_en_p : STD_LOGIC;`
83			`SIGNAL in_fifo_dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
84			`SIGNAL in_fifo_full : STD_LOGIC;`
85			`SIGNAL in_fifo_nearly_full : STD_LOGIC;`
86			`SIGNAL in_fifo_empty : STD_LOGIC;`
87			`------------------------------`
88			`SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
89			`SIGNAL ctrl_fifo_rd : STD_LOGIC;`
90			`SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);`
91			`SIGNAL ctrl_fifo_full : STD_LOGIC;`
92			`SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;`
93			`SIGNAL ctrl_fifo_empty : STD_LOGIC;`
94			`-- SIGNAL cnt : INTEGER;`
95
96			`SIGNAL out_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
97			`SIGNAL out_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
98			`SIGNAL out_wr_i : STD_LOGIC ;`
99			`SIGNAL in_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
100			`SIGNAL in_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
101			`SIGNAL in_fifo_in_i : STD_LOGIC_VECTOR(71 DOWNTO 0) ;`
102			`SIGNAL wr_en_i : STD_LOGIC ;`
103			`SIGNAL exit_port : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
104			`SIGNAL done : STD_LOGIC ;`
105			`SIGNAL words_cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
106			`SIGNAL words_cnt_ch : STD_LOGIC;`
107			`SIGNAL bytes_cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
108			`SIGNAL cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
109			`SIGNAL last_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
110			`SIGNAL cnt_en : STD_LOGIC ;`
111			`SIGNAL cnt_rst : STD_LOGIC ;`
112			`SIGNAL header_rdy : STD_LOGIC ;`
113			`SIGNAL latch : STD_LOGIC ;`
114			`SIGNAL latch_word : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
115			`SIGNAL latch_word_p : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
116			`SIGNAL fifo_data_p : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
117			`SIGNAL wr_en : STD_LOGIC;`
118			`SIGNAL out_wr_t_i : STD_LOGIC;`
119			`---------------------------------------------------`
120			`BEGIN`
121
122
123			`------PORT MAP open_header`
124			`vlan2extr_Inst : vlan2ext`
125			`GENERIC MAP (DATA_WIDTH => 64,`
126			`CTRL_WIDTH => 8)`
127			`PORT MAP(`
128			`in_data => in_data_i,`
129			`in_ctrl => in_ctrl_i ,`
130			`in_wr => wr_en_i,`
131			`exit_port => exit_port,`
132			`done => done,`
133			`reset => reset,`
134			`clk => clk`
135			`);`
136
137			`------PORT MAP open_header`
138
139			`-------PORT MAP SMALL FIFO DATA`
140			`small_fifo_Inst1 : small_fifo`
141			`GENERIC MAP(WIDTH => 72,`
142			`MAX_DEPTH_BITS => 5)`
143			`PORT MAP(`
144			`din =>in_fifo_in_i,`
145			`wr_en =>wr_en_i,`
146			`rd_en => in_fifo_rd_en,`
147			`dout =>in_fifo_dout,`
148			`full =>in_fifo_full,`
149			`nearly_full =>in_fifo_nearly_full,`
150			`empty => in_fifo_empty,`
151			`reset => reset ,`
152			`clk => clk`
153			`);`
154
155
156
157			`-------PORT MAP SMALL FIFO`
158			`-------PORT MAP SMALL FIFO DATA`
159			`small_fifo_Inst_ctrl : small_fifo`
160			`GENERIC MAP(WIDTH => 8,`
161			`MAX_DEPTH_BITS => 5)`
162			`PORT MAP(`
163			`din =>exit_port,`
164			`wr_en => done,`
165			`rd_en => ctrl_fifo_rd,`
166			`dout =>ctrl_fifo_dout,`
167			`full =>ctrl_fifo_full,`
168			`nearly_full =>ctrl_fifo_nearly_full,`
169			`empty => ctrl_fifo_empty,`
170			`reset => reset ,`
171			`clk => clk`
172			`);`
173
174
175			`-----------------------`
176
177			`PROCESS(clk,reset)`
178			`BEGIN`
179			`IF clk'EVENT AND clk ='1' THEN`
180			`in_fifo_in_i <= in_fifo_in;`
181			`wr_en_i <= wr_en;`
182			`in_data_i <= in_data;`
183			`in_ctrl_i <= in_ctrl;`
184			`END IF;`
185			`END PROCESS;`
186			`in_fifo_in <= in_data & in_ctrl ;`
187			`fifo_data <= in_fifo_dout(71 DOWNTO 8) ;`
188			`fifo_ctrl <= in_fifo_dout(7 DOWNTO 0) ;`
189			`-- in_fifo_rd_en <=out_rdy AND (NOT in_fifo_empty) AND in_fifo_go;`
190			`-- fifo_rd <= ctrl_fifo_empty OR in_fifo_go;`
191			`in_rdy <= (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full) ;`
192			`wr_en <= en AND in_wr;`
193			`PROCESS(clk,reset)`
194			`BEGIN`
195			`IF (reset ='1') THEN`
196			`state <=IDLE;`
197			`ELSIF clk'EVENT AND clk ='1' THEN`
198			`state<=state_next;`
199			`in_fifo_rd_en_p <= in_fifo_rd_en;`
200			`END IF;`
201			`END PROCESS;`
202
203			`-- out_cnt <= cnt;`
204			`PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)`
205			`BEGIN`
206			`state_next <= state;`
207			`out_wr_i <= '0';`
208			`ctrl_fifo_rd <= '0' ;`
209			`in_fifo_rd_en <= '0' ;`
210			`header_rdy <= '0' ;`
211
212			`CASE state IS`
213			`WHEN IDLE =>`
214			`IF(ctrl_fifo_empty = '0' ) THEN`
215			`ctrl_fifo_rd <= '1' ;`
216			`in_fifo_rd_en <= '1' ;`
217			`state_next <= START;`
218			`END IF;`
219			`WHEN START =>`
220
221			`header_rdy <= '1' ;`
222			`state_next <= IN_MODULE_HDRS;`
223			`WHEN IN_MODULE_HDRS =>`
224
225			`IF(out_rdy = '1' ) THEN`
226			`IF (fifo_ctrl=X"FF") THEN`
227			`out_data_i <= fifo_data ;`
228			`out_ctrl_i <= fifo_ctrl;`
229			`END IF;`
230			`out_wr_i <= '1';`
231			`in_fifo_rd_en <= '1' ;`
232			`state_next <= WORD_1;`
233			`END IF;`
234
235
236			`WHEN WORD_1 =>`
237
238			`IF(out_rdy = '1' AND in_fifo_empty ='0') THEN`
239
240			`out_wr_i <= '1';`
241			`in_fifo_rd_en <= '1' ;`
242			`out_data_i <= fifo_data ;`
243			`out_ctrl_i <= fifo_ctrl;`
244			`state_next <= WORD_2;`
245			`END IF;`
246			`WHEN WORD_2 =>IF(out_rdy = '1' AND in_fifo_empty ='0') THEN`
247
248			`out_wr_i <= '1';`
249			`in_fifo_rd_en <= '1' ;`
250			`out_data_i <= fifo_data ;`
251			`out_ctrl_i <= fifo_ctrl;`
252			`state_next <= WORD_3;`
253			`END IF;`
254
255			`WHEN WORD_3 =>`
256			`IF(out_rdy = '1' AND in_fifo_empty ='0') THEN`
257			`out_wr_i <= '1';`
258			`in_fifo_rd_en <= '1' ;`
259			`out_data_i <= fifo_data ;`
260			`out_ctrl_i <= fifo_ctrl;`
261			`state_next <= IN_PACKET;`
262			`END IF;`
263
264
265			`WHEN IN_PACKET =>`
266
267
268			`IF ( fifo_ctrl /= X"00" ) THEN`
269
270			`IF ( out_rdy = '1' ) THEN`
271			`state_next <= IDLE;`
272			`-- ELSE`
273			`-- state_next <= LAST;`
274			`END IF;`
275			`ELSIF(out_rdy = '1' AND in_fifo_empty ='0') THEN`
276			`out_wr_i <= '1';`
277			`in_fifo_rd_en <= '1' ;`
278			`out_data_i <= fifo_data ;`
279			`out_ctrl_i <= fifo_ctrl;`
280			`state_next <= IN_PACKET;`
281			`END IF;`
282
283			`WHEN LAST =>`
284			`state_next <= IDLE;`
285
286			`END CASE;`
287			`END PROCESS;`
288			`---------------Register output`
289			`--`
290			`--`
291			`-- WITH state SELECT`
292			`-- out_data_i <=`
293			`-- X"00" & ctrl_fifo_dout & X"00"& words_cnt & fifo_data(31 downto 16) & X"00"& bytes_cnt WHEN IN_MODULE_HDRS,`
294			`-- fifo_data WHEN WORD_1,`
295			`-- latch_word(63 downto 32) & fifo_data(63 downto 32)WHEN WORD_3,`
296			`-- latch_word(31 downto 0) & fifo_data(63 downto 32) WHEN IN_PACKET \| LAST,`
297			`-- (OTHERS=>'0') WHEN OTHERS;`
298			`--`
299			`--`
300			`-- out_ctrl_i <= X"FF" when state = IN_MODULE_HDRS else`
301			`-- last_ctrl when state = IN_PACKET AND fifo_ctrl /= X"00" AND words_cnt_ch='1' else`
302			`-- last_ctrl when state = LAST else`
303			`-- X"00" ;`
304			`-- WITH state SELECT`
305			`-- out_wr_i <=`
306			`-- out_rdy WHEN IN_MODULE_HDRS,`
307			`-- in_fifo_rd_en_p WHEN WORD_1,`
308			`-- in_fifo_rd_en_p WHEN WORD_3,`
309			`-- in_fifo_rd_en_p WHEN IN_PACKET ,`
310			`-- '1' WHEN LAST,`
311			`-- '0' WHEN OTHERS;`
312			`---- out_wr_t_i <= word_cnt_up when word_cnt >= 1 AND word_cnt <= 21 else`
313			`---- '0';`
314			`-- PROCESS(clk,reset)`
315			`-- BEGIN`
316			`--`
317			`-- IF clk'EVENT AND clk ='1' THEN`
318			`-- IF header_rdy = '1' THEN`
319			`-- bytes_cnt <= fifo_data(7 downto 0)- X"04";`
320			`-- IF (fifo_data(15 downto 0)-X"0004") > (fifo_data(45 downto 32)&"000" - X"0008") THEN`
321			`-- words_cnt <= fifo_data(39 downto 32) ;`
322			`-- words_cnt_ch <= '0';`
323			`-- ELSE`
324			`-- words_cnt <= fifo_data(39 downto 32) - '1' ;`
325			`-- words_cnt_ch <= '1';`
326			`-- END IF;`
327			`-- END IF;`
328			`-- IF in_fifo_rd_en='1' THEN`
329			`-- latch_word <= fifo_data;`
330			`-- END IF;`
331			`--`
332			`-- END IF;`
333			`-- END PROCESS;`
334			`-- WITH bytes_cnt(2 DOWNTO 0)SELECT`
335			`-- last_ctrl <= "00000010" WHEN "111",`
336			`-- "00000100" WHEN "110",`
337			`-- "00001000" WHEN "101",`
338			`-- "00010000" WHEN "100",`
339			`-- "00100000" WHEN "011",`
340			`-- "01000000" WHEN "010",`
341			`-- "10000000" WHEN "001",`
342			`-- "00000001" WHEN others;`
343			`--`
344			`--`
345			`--`
346			`PROCESS(clk,reset)`
347			`BEGIN`
348			`--`
349			`IF clk'EVENT AND clk ='1' THEN`
350			`out_data <= out_data_i;`
351			`out_ctrl <= out_ctrl_i;`
352			`out_wr <= out_wr_i;`
353			`END IF;`
354			`END PROCESS;`
355			`-- fifo_ctrl_out <=fifo_ctrl;`
356			`-- fifo_data_out <=fifo_data;`
357			`-- latch_word_out <= latch_word;`
358			`END behavior;`
359