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[/] [loadbalancer/] [trunk/] [int2ext/] [int2ext_topq.vhd] - Blame information for rev 2

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--------------------------------------------------------
 
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use IEEE.std_logic_arith.all;
-------------------------------
        ENTITY int2ext_top IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
    SIGNAL              in_wr                           :       IN              STD_LOGIC       ;
        SIGNAL          in_rdy                          :       OUT     STD_LOGIC       ;
 
        SIGNAL          out_data                        :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          out_ctrl                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
        SIGNAL          out_wr                          :       OUT     STD_LOGIC       ;
        SIGNAL          out_rdy                         :       IN              STD_LOGIC       ;
 
    --- Misc
    SIGNAL     en : IN STD_LOGIC;
    SIGNAL              reset                           :       IN              STD_LOGIC       ;
    SIGNAL              clk                             :       IN              STD_LOGIC
        );
        END ENTITY;
 
 ------------------------------------------------------
        ARCHITECTURE behavior OF int2ext_top IS
-------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
        GENERIC(WIDTH :INTEGER := 72;
                        MAX_DEPTH_BITS :INTEGER := 3);
        PORT(
 
 
     SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
     SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
 
     SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word 
 
     SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
     SIGNAL full : OUT STD_LOGIC;--output         full,
     SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
     SIGNAL empty : OUT STD_LOGIC;--output         empty,
 
 
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT;
-------COMPONENET SMALL FIFO
        COMPONENT int2ext IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
                SIGNAL          in_data                            :    IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
                SIGNAL          in_ctrl                            :    IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
                SIGNAL          in_wr                           :       IN              STD_LOGIC       ;
                SIGNAL          in_rdy                          :       OUT     STD_LOGIC       ;
 
                SIGNAL          out_data                        :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
                SIGNAL          out_ctrl                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
                SIGNAL          out_wr                          :       OUT     STD_LOGIC       ;
                SIGNAL          out_rdy                            :    IN              STD_LOGIC       ;
                SIGNAL          reset                           :       IN              STD_LOGIC       ;
                SIGNAL          clk                             :       IN              STD_LOGIC
        );
        END COMPONENT int2ext;
 
----------------------FIFO        
          SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
          SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_rd_en : STD_LOGIC;
          SIGNAL in_fifo_rd_en_p : STD_LOGIC;
          SIGNAL in_fifo_go : STD_LOGIC;
          SIGNAL in_fifo_go_i : STD_LOGIC;
      SIGNAL in_fifo_dout  : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_full : STD_LOGIC;
      SIGNAL in_fifo_nearly_full : STD_LOGIC;
      SIGNAL in_fifo_empty : STD_LOGIC;
                 SIGNAL wr_en : STD_LOGIC;
          SIGNAL                out_data_i                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                out_ctrl_i                      :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                out_wr_i                        :               STD_LOGIC       ;
           SIGNAL               out_data_ii                     :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                out_ctrl_ii                     :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                out_wr_ii                       :               STD_LOGIC       ;
          SIGNAL                out_rdy_int                     :               STD_LOGIC       ;
---------------------------------------------------
        BEGIN
 
        ------PORT MAP open_header
 
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst :  small_fifo
        GENERIC MAP(WIDTH  => 72,
                        MAX_DEPTH_BITS  => 5)
        PORT MAP(
 
 
      din =>(in_fifo_in),
      wr_en =>wr_en,
 
      rd_en => in_fifo_rd_en,
 
      dout =>in_fifo_dout,
      full =>in_fifo_full,
      nearly_full =>in_fifo_nearly_full,
      empty => in_fifo_empty,
 
 
     reset => reset ,
     clk  => clk
 
        );
 
 
        int2ext_inst :  int2ext
        GENERIC MAP(DATA_WIDTH => 64,
                        CTRL_WIDTH => 8)
        PORT MAP(
                                in_data                            => out_data_ii,
                                in_ctrl                            => out_ctrl_ii,
                                in_wr                           => out_wr_ii,
                                in_rdy                          => out_rdy_int,
 
                                out_data                        => out_data,
                                out_ctrl                        => out_ctrl,
                                out_wr                          => out_wr,
                                out_rdy                            => out_rdy,
                                reset                           => reset,
                                clk                             => clk
        );
 
 
-----------------------
      in_fifo_in <=     in_data & in_ctrl ;
                wr_en <=  en and in_wr;
                fifo_data       <=         in_fifo_dout(71 DOWNTO 8)    ;
                fifo_ctrl       <=      in_fifo_dout(7 DOWNTO 0) ;
                in_fifo_rd_en <=  out_rdy_int and(not in_fifo_empty) ;
 
 
 
                 in_rdy         <=      (NOT in_fifo_nearly_full);-- or (not en)        ;
 
 
 
 
 
PROCESS(clk,reset)
BEGIN
        IF (reset ='1') THEN
                ELSIF clk'EVENT AND clk ='1' THEN
                in_fifo_rd_en_p <= in_fifo_rd_en;
        END IF;
END PROCESS;
                                                                        out_data_i                              <=      fifo_data;
                                                                        out_ctrl_i                              <=      fifo_ctrl;
                                                                        out_wr_i                                   <=   in_fifo_rd_en_p ;
 
---------------Register output
--              PROCESS(clk,reset)
--              BEGIN
--                      
--                      IF clk'EVENT AND clk ='1' THEN
                                                                        out_data_ii                     <=      out_data_i;
                                                                        out_ctrl_ii                 <=  out_ctrl_i;
                                                                        out_wr_ii                                   <=  out_wr_i;
 
--                      END IF;
--              END PROCESS;    
END behavior;
 

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2
3			`LIBRARY IEEE;`
4			`USE IEEE.STD_LOGIC_1164.ALL;`
5			`use IEEE.std_logic_arith.all;`
6			`-------------------------------`
7			`ENTITY int2ext_top IS`
8			`GENERIC(DATA_WIDTH :INTEGER := 64;`
9			`CTRL_WIDTH :INTEGER := 8);`
10			`PORT(`
11			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
12			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
13			`SIGNAL in_wr : IN STD_LOGIC ;`
14			`SIGNAL in_rdy : OUT STD_LOGIC ;`
15
16			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
17			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
18			`SIGNAL out_wr : OUT STD_LOGIC ;`
19			`SIGNAL out_rdy : IN STD_LOGIC ;`
20
21			`--- Misc`
22			`SIGNAL en : IN STD_LOGIC;`
23			`SIGNAL reset : IN STD_LOGIC ;`
24			`SIGNAL clk : IN STD_LOGIC`
25			`);`
26			`END ENTITY;`
27
28			`------------------------------------------------------`
29			`ARCHITECTURE behavior OF int2ext_top IS`
30			`-------COMPONENET SMALL FIFO`
31			`COMPONENT small_fifo IS`
32			`GENERIC(WIDTH :INTEGER := 72;`
33			`MAX_DEPTH_BITS :INTEGER := 3);`
34			`PORT(`
35
36
37			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din, // Data in`
38			`SIGNAL wr_en : IN STD_LOGIC;--input wr_en, // Write enable`
39
40			`SIGNAL rd_en : IN STD_LOGIC;--input rd_en, // Read the next word`
41
42			`SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out`
43			`SIGNAL full : OUT STD_LOGIC;--output full,`
44			`SIGNAL nearly_full : OUT STD_LOGIC;--output nearly_full,`
45			`SIGNAL empty : OUT STD_LOGIC;--output empty,`
46
47
48			`SIGNAL reset :IN STD_LOGIC;`
49			`SIGNAL clk :IN STD_LOGIC`
50
51			`);`
52			`END COMPONENT;`
53			`-------COMPONENET SMALL FIFO`
54			`COMPONENT int2ext IS`
55			`GENERIC(DATA_WIDTH :INTEGER := 64;`
56			`CTRL_WIDTH :INTEGER := 8);`
57			`PORT(`
58			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
59			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
60			`SIGNAL in_wr : IN STD_LOGIC ;`
61			`SIGNAL in_rdy : OUT STD_LOGIC ;`
62
63			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
64			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
65			`SIGNAL out_wr : OUT STD_LOGIC ;`
66			`SIGNAL out_rdy : IN STD_LOGIC ;`
67			`SIGNAL reset : IN STD_LOGIC ;`
68			`SIGNAL clk : IN STD_LOGIC`
69			`);`
70			`END COMPONENT int2ext;`
71
72			`----------------------FIFO`
73			`SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);`
74			`SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);`
75			`SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
76			`SIGNAL in_fifo_rd_en : STD_LOGIC;`
77			`SIGNAL in_fifo_rd_en_p : STD_LOGIC;`
78			`SIGNAL in_fifo_go : STD_LOGIC;`
79			`SIGNAL in_fifo_go_i : STD_LOGIC;`
80			`SIGNAL in_fifo_dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
81			`SIGNAL in_fifo_full : STD_LOGIC;`
82			`SIGNAL in_fifo_nearly_full : STD_LOGIC;`
83			`SIGNAL in_fifo_empty : STD_LOGIC;`
84			`SIGNAL wr_en : STD_LOGIC;`
85			`SIGNAL out_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
86			`SIGNAL out_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
87			`SIGNAL out_wr_i : STD_LOGIC ;`
88			`SIGNAL out_data_ii : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
89			`SIGNAL out_ctrl_ii : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
90			`SIGNAL out_wr_ii : STD_LOGIC ;`
91			`SIGNAL out_rdy_int : STD_LOGIC ;`
92			`---------------------------------------------------`
93			`BEGIN`
94
95			`------PORT MAP open_header`
96
97			`-------PORT MAP SMALL FIFO DATA`
98			`small_fifo_Inst : small_fifo`
99			`GENERIC MAP(WIDTH => 72,`
100			`MAX_DEPTH_BITS => 5)`
101			`PORT MAP(`
102
103
104			`din =>(in_fifo_in),`
105			`wr_en =>wr_en,`
106
107			`rd_en => in_fifo_rd_en,`
108
109			`dout =>in_fifo_dout,`
110			`full =>in_fifo_full,`
111			`nearly_full =>in_fifo_nearly_full,`
112			`empty => in_fifo_empty,`
113
114
115			`reset => reset ,`
116			`clk => clk`
117
118			`);`
119
120
121			`int2ext_inst : int2ext`
122			`GENERIC MAP(DATA_WIDTH => 64,`
123			`CTRL_WIDTH => 8)`
124			`PORT MAP(`
125			`in_data => out_data_ii,`
126			`in_ctrl => out_ctrl_ii,`
127			`in_wr => out_wr_ii,`
128			`in_rdy => out_rdy_int,`
129
130			`out_data => out_data,`
131			`out_ctrl => out_ctrl,`
132			`out_wr => out_wr,`
133			`out_rdy => out_rdy,`
134			`reset => reset,`
135			`clk => clk`
136			`);`
137
138
139			`-----------------------`
140			`in_fifo_in <= in_data & in_ctrl ;`
141			`wr_en <= en and in_wr;`
142			`fifo_data <= in_fifo_dout(71 DOWNTO 8) ;`
143			`fifo_ctrl <= in_fifo_dout(7 DOWNTO 0) ;`
144			`in_fifo_rd_en <= out_rdy_int and(not in_fifo_empty) ;`
145
146
147
148			`in_rdy <= (NOT in_fifo_nearly_full);-- or (not en) ;`
149
150
151
152
153
154			`PROCESS(clk,reset)`
155			`BEGIN`
156			`IF (reset ='1') THEN`
157			`ELSIF clk'EVENT AND clk ='1' THEN`
158			`in_fifo_rd_en_p <= in_fifo_rd_en;`
159			`END IF;`
160			`END PROCESS;`
161			`out_data_i <= fifo_data;`
162			`out_ctrl_i <= fifo_ctrl;`
163			`out_wr_i <= in_fifo_rd_en_p ;`
164
165			`---------------Register output`
166			`-- PROCESS(clk,reset)`
167			`-- BEGIN`
168			`--`
169			`-- IF clk'EVENT AND clk ='1' THEN`
170			`out_data_ii <= out_data_i;`
171			`out_ctrl_ii <= out_ctrl_i;`
172			`out_wr_ii <= out_wr_i;`
173
174			`-- END IF;`
175			`-- END PROCESS;`
176			`END behavior;`
177

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[/] [loadbalancer/] [trunk/] [int2ext/] [int2ext_topq.vhd] - Blame information for rev 2