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[/] [loadbalancer/] [trunk/] [small_fifo.v] - Blame information for rev 2

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///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 1998 2007-07-21 01:22:57Z grg $
//
// Module: small_fifo.v
// Project: UNET
// Description: small fifo with no fallthrough i.e. data valid after rd is high
//
// Change history: 
//   7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it 
//              goes high a clock cycle early.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
 
  module small_fifo
    #(parameter WIDTH = 72,
      parameter MAX_DEPTH_BITS = 3,
      parameter NEARLY_FULL = 2**MAX_DEPTH_BITS - 1)
    (
 
     input [WIDTH-1:0] din,     // Data in
     input          wr_en,   // Write enable
 
     input          rd_en,   // Read the next word 
 
     output reg [WIDTH-1:0]  dout,    // Data out
     output         full,
     output         nearly_full,
     output         empty,
 
     input          reset,
     input          clk
     );
 
 
parameter MAX_DEPTH        = 2 ** MAX_DEPTH_BITS;
 
reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
 
// Sample the data
always @(posedge clk)
begin
   if (wr_en)
      queue[wr_ptr] <= din;
   if (rd_en)
      dout <=
              // synthesis translate_off
              #1
              // synthesis translate_on
              queue[rd_ptr];
end
 
always @(posedge clk)
begin
   if (reset) begin
      rd_ptr <= 'h0;
      wr_ptr <= 'h0;
      depth  <= 'h0;
   end
   else begin
      if (wr_en) wr_ptr <= wr_ptr + 'h1;
      if (rd_en) rd_ptr <= rd_ptr + 'h1;
      if (wr_en & ~rd_en) depth <=
                                   // synthesis translate_off
                                   #1
                                   // synthesis translate_on
                                   depth + 'h1;
      else if (~wr_en & rd_en) depth <=
                                   // synthesis translate_off
                                   #1
                                   // synthesis translate_on
                                   depth - 'h1;
   end
end
 
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign nearly_full = depth >= NEARLY_FULL;
assign empty = depth == 'h0;
 
// synthesis translate_off
always @(posedge clk)
begin
   if (wr_en && depth == MAX_DEPTH && !rd_en)
      $display($time, " ERROR: Attempt to write to full FIFO: %m");
   if (rd_en && depth == 'h0)
      $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
 
endmodule // small_fifo
 
 
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */

Line No.	Rev	Author	Line
1	2	atalla	`///////////////////////////////////////////////////////////////////////////////`
2			`// $Id: small_fifo.v 1998 2007-07-21 01:22:57Z grg $`
3			`//`
4			`// Module: small_fifo.v`
5			`// Project: UNET`
6			`// Description: small fifo with no fallthrough i.e. data valid after rd is high`
7			`//`
8			`// Change history:`
9			`// 7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it`
10			`// goes high a clock cycle early.`
11			`//`
12			`///////////////////////////////////////////////////////////////////////////////`
13			`timescale 1ns/1ps
14
15			`module small_fifo`
16			`#(parameter WIDTH = 72,`
17			`parameter MAX_DEPTH_BITS = 3,`
18			`parameter NEARLY_FULL = 2**MAX_DEPTH_BITS - 1)`
19			`(`
20
21			`input [WIDTH-1:0] din, // Data in`
22			`input wr_en, // Write enable`
23
24			`input rd_en, // Read the next word`
25
26			`output reg [WIDTH-1:0] dout, // Data out`
27			`output full,`
28			`output nearly_full,`
29			`output empty,`
30
31			`input reset,`
32			`input clk`
33			`);`
34
35
36			`parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;`
37
38			`reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];`
39			`reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;`
40			`reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;`
41			`reg [MAX_DEPTH_BITS : 0] depth;`
42
43			`// Sample the data`
44			`always @(posedge clk)`
45			`begin`
46			`if (wr_en)`
47			`queue[wr_ptr] <= din;`
48			`if (rd_en)`
49			`dout <=`
50			`// synthesis translate_off`
51			`#1`
52			`// synthesis translate_on`
53			`queue[rd_ptr];`
54			`end`
55
56			`always @(posedge clk)`
57			`begin`
58			`if (reset) begin`
59			`rd_ptr <= 'h0;`
60			`wr_ptr <= 'h0;`
61			`depth <= 'h0;`
62			`end`
63			`else begin`
64			`if (wr_en) wr_ptr <= wr_ptr + 'h1;`
65			`if (rd_en) rd_ptr <= rd_ptr + 'h1;`
66			`if (wr_en & ~rd_en) depth <=`
67			`// synthesis translate_off`
68			`#1`
69			`// synthesis translate_on`
70			`depth + 'h1;`
71			`else if (~wr_en & rd_en) depth <=`
72			`// synthesis translate_off`
73			`#1`
74			`// synthesis translate_on`
75			`depth - 'h1;`
76			`end`
77			`end`
78
79			`//assign dout = queue[rd_ptr];`
80			`assign full = depth == MAX_DEPTH;`
81			`assign nearly_full = depth >= NEARLY_FULL;`
82			`assign empty = depth == 'h0;`
83
84			`// synthesis translate_off`
85			`always @(posedge clk)`
86			`begin`
87			`if (wr_en && depth == MAX_DEPTH && !rd_en)`
88			`$display($time, " ERROR: Attempt to write to full FIFO: %m");`
89			`if (rd_en && depth == 'h0)`
90			`$display($time, " ERROR: Attempt to read an empty FIFO: %m");`
91			`end`
92			`// synthesis translate_on`
93
94			`endmodule // small_fifo`
95
96
97			`/* vim:set shiftwidth=3 softtabstop=3 expandtab: */`

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[/] [loadbalancer/] [trunk/] [small_fifo.v] - Blame information for rev 2