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jamro |
-- logic analyser trigger -- ver 1.0
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-- Author: Ernest Jamro
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--//////////////////////////////////////////////////////////////////////
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--//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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--//// ////
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--//// This source file may be used and distributed without ////
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--/// restriction provided that this copyright statement is not ////
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--//// removed from the file and that any derivative work contains ////
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--//// the original copyright notice and the associated disclaimer. ////
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--//// ////
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--//// This source file is free software; you can redistribute it ////
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--//// and/or modify it under the terms of the GNU Lesser General ////
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--//// Public License as published by the Free Software Foundation; ////
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--//// either version 2.1 of the License, or (at your option) any ////
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--//// later version. ////
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--//// ////
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--//// This source is distributed in the hope that it will be ////
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--//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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--//// PURPOSE. See the GNU Lesser General Public License for more ////
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--//// details. ////
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--//// ////
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--//// You should have received a copy of the GNU Lesser General ////
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--//// Public License along with this source; if not, download it ////
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--//// from <http://www.opencores.org/lgpl.shtml> ////
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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-- TRIGGER LOGIC (input trig_data when satisfies the trigger condition causes that the data recording starts)
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_misc.all; -- for AND gate
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entity la_trigger is
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generic (trig_width: integer:= 8); -- width of the trig data 1<=trig_width<=32
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port (clk, arst: in std_logic;
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-- LA interface
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trig_data: in std_logic_vector(trig_width-1 downto 0); -- data that are alasysed for triger
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trig_now: out std_logic; -- triger data is now presented on the trig_data bus
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-- Control interface (to set and read triger values)
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wr: in std_logic; -- when 1 writes din to triger configuration registers
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adr: in std_logic_vector(3 downto 0);
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dout: out std_logic_vector(7 downto 0);
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din: in std_logic_vector(7 downto 0) );
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end la_trigger;
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architecture la_trigger_arch of la_trigger is
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signal trig_value: std_logic_vector(trig_width-1 downto 0); -- sets lewel for which reiger should be active
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signal trig_care: std_logic_vector(trig_width-1 downto 0); -- care / or do not care about the input value presented on trig_data
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signal trig_and: std_logic_vector(trig_width-1 downto 0); -- temporal value that goes to trig_width and gate
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signal trig_result: std_logic_vector(trig_width downto 0); -- result of the and gate
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signal dout32value, dout32care: std_logic_vector(31 downto 0); -- dout value extended with zeros
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begin
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-- trig_value and care registers
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t8: if trig_width<=8 generate
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process(clk, arst) begin
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if arst='1' then trig_value<= (others=>'0'); trig_care<= (others=>'0');
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elsif clk'event and clk='1' then
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if wr='1' then
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if adr="1000" then trig_value(trig_width-1 downto 0)<= din(trig_width-1 downto 0); end if;
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if adr="1100" then trig_care(trig_width-1 downto 0)<= din(trig_width-1 downto 0); end if;
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end if;
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end if;
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end process;
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end generate;
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t16: if trig_width<=16 and trig_width>8 generate
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process(clk, arst) begin
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if arst='1' then trig_value<= (others=>'0'); trig_care<= (others=>'0');
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elsif clk'event and clk='1' then
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if wr='1' then
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if adr="1000" then trig_value(7 downto 0)<= din; end if;
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if adr="1001" then trig_value(trig_width-1 downto 8)<= din(trig_width-8 downto 0); end if;
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if adr="1100" then trig_care(7 downto 0)<= din; end if;
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if adr="1101" then trig_care(trig_width-1 downto 8)<= din(trig_width-8 downto 0); end if;
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end if;
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end if;
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end process;
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end generate;
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t24: if trig_width<=24 and trig_width>16 generate
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process(clk, arst) begin
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if arst='1' then trig_value<= (others=>'0'); trig_care<= (others=>'0');
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elsif clk'event and clk='1' then
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if wr='1' then
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if adr="1000" then trig_value(7 downto 0)<= din; end if;
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if adr="1001" then trig_value(15 downto 8)<= din; end if;
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if adr="1010" then trig_value(trig_width-1 downto 16)<= din(trig_width-16 downto 0); end if;
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if adr="1100" then trig_care(7 downto 0)<= din; end if;
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if adr="1101" then trig_care(15 downto 8)<= din; end if;
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if adr="1110" then trig_care(trig_width-1 downto 16)<= din(trig_width-16 downto 0); end if;
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end if;
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end if;
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end process;
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end generate;
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t32: if trig_width>24 generate
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process(clk, arst) begin
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if arst='1' then trig_value<= (others=>'0'); trig_care<= (others=>'0');
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elsif clk'event and clk='1' then
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if wr='1' then
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if adr="1000" then trig_value(7 downto 0)<= din; end if;
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if adr="1001" then trig_value(15 downto 8)<= din; end if;
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if adr="1010" then trig_value(23 downto 16)<= din; end if;
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if adr="1011" then trig_value(trig_width-1 downto 24)<= din(trig_width-24 downto 0); end if;
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if adr="1100" then trig_care(7 downto 0)<= din; end if;
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if adr="1101" then trig_care(15 downto 8)<= din; end if;
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if adr="1110" then trig_care(23 downto 16)<= din; end if;
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if adr="1111" then trig_care(trig_width-1 downto 24)<= din(trig_width-24 downto 0); end if;
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end if;
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end if;
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end process;
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end generate;
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-- trig_now logic
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gi: for i in 0 to trig_width-1 generate
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-- trig_and flip-flop (introduces pipelining to speed up the ciruit frequency)
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process(clk, arst) begin
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if arst='1' then trig_and(i)<= '0';
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elsif clk'event and clk='1' then
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trig_and(i)<= not trig_care(i) or not( trig_data(i) xor trig_value(i));
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end if;
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end process;
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end generate;
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-- and gate and flip-flop
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process(clk, arst) begin
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if arst='1' then trig_now<= '0';
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elsif clk'event and clk='1' then
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trig_now<= AND_REDUCE(trig_and); -- correct trigger;
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end if;
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end process;
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-- dout multiplexer
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-- extend MSBs with zeros
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dout32value(trig_width-1 downto 0)<= trig_value;
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dout32care(trig_width-1 downto 0)<= trig_care;
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g31: if trig_width<32 generate
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dout32value(31 downto trig_width)<= (others=>'0');
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dout32care(31 downto trig_width)<= (others=>'0');
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end generate;
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dout<= dout32value(7 downto 0) when adr(2 downto 0)="000" else
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dout32value(15 downto 8) when adr(2 downto 0)="001" else
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dout32value(23 downto 16) when adr(2 downto 0)="010" else
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dout32value(31 downto 24) when adr(2 downto 0)="011" else
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dout32care(7 downto 0) when adr(2 downto 0)="100" else
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dout32care(15 downto 8) when adr(2 downto 0)="101" else
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dout32care(23 downto 16) when adr(2 downto 0)="110" else
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dout32care(31 downto 24) when adr(2 downto 0)="111" else (others=> '-');
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end la_trigger_arch;
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