Subversion Repositories logicprobe

Welcome to LogicProbe!

1) What is it?

LogicProbe is a very simple logic analyzer which can be run on

an FPGA in parallel with the "device under test". The analyzer

has a width of 128 data channels, and is 512 samples deep. It

has a trigger (i.e., it starts catching the channels when this

signal got active once), and a sample enable (i.e., it does only

sample the channels when this line is 1). It uses the block RAM

on the FPGA to store the samples in real-time. When the sample

buffer is full, it begins to transmit the samples through a UART

(also included in the code) over the serial line to a PC where

the sample values are stored in a file. A simple listing program

allows to view the samples as hexadecimal values.

2) How do I use it?

You simply have to instanciate the module described below and setup

the constraints file so that "serial_out" is connected to the transmit

data line of an RS232 connector (via appropriate level shifters, of

course). The line speed is fixed at 38400 bps; this should certainly

be made a parameter of the design in the next version. Connect a PC

to the other end of the serial line and run the "receive" program,

which stores the transmitted samples into a file. You can then use

the "display" program to examine the samples as hexadecimal numbers.

Here is the interface to the analyzer module:

module LogicProbe(clock, reset, trigger, sample, channels, serial_out);

    input clock;                // master clock, also used for sampling

    input reset;                // master reset

    input trigger;              // start sampling when this line is 1

    input sample;               // enable sampling when this line is 1

    input [127:0] channels;     // the data to be sampled

    output serial_out;          // serial line to the PC

3) What do the directories and files in this package contain?

README              this file

COPYING             BSD license

Makefile            Makefile for building the project

src                 source files

  Makefile          controls the build process on this level

  fpga              synthesizable Verilog (for running on the FPGA)

    LogicProbe.v    the logic analyzer proper

  pc                C source files (for running on the PC)

    Makefile        for building the analyzer programs

    receive.c       RS232 receiver program

    display.c       sample value viewer

tst                 test case, simulated as well as running on FPGAs

  Makefile          controls the build process on this level

  sim-c             simulation program in C

    Makefile        runs the simulation, generates reference data

    lfsr128.c       128 bit LFSR

  sim-v             Verilog source to be simulated with Icarus Verilog

    Makefile        controls the simulation

    top.v           top-level simulation environment

    top.cfg         config file for GTK wave viewer

    lfsr128.v       same LFSR as in C, but now in Verilog

  boards            same LFSR as in sim-v, with LogicProbe attached,

                    configured for different FPGA evaluation boards

4) What else do I need?

If you want to run the tests, you need a Verilog simulator (I used

Icarus Verilog) and a VCD wave viewer (I used GTK-Wave). If you want

to use the analyzer in an FPGA, you must synthesize it (I used Xilinx

ISE 14.5). And you need a C compiler, preferably on a Linux system,

to receive and display the sample values.

5) Has the analyzer been used outside the test case?

Yes, it was instrumental in finding an error in my 32-bit CPU

which prohibited even the first instruction fetch from memory.

Simulation was of no help; the error didn't show up there. As

it turned out, I used initialization statements, which of course

couldn't be synthesized - so the start conditions inside the FPGA

differed from those of the simulation.

If you have any questions, write to

Hellwig.Geisse@mni.thm.de

Enjoy!

Hellwig