Subversion Repositories logicprobe

This board is equipped with a single RS-232 connector. The lines

TXD, RXD, RTS, and CTS are connected (via level shifters) to the

FPGA. Because in another project, two serial lines were required

(and no hardware flow control was necessary), the signals RTS and

CTS were used as TXD and RXD, respectively, in a separate (third)

connector. In this way the single serial line with flow control

has been split into two serial lines without flow control. The

constraints file given here uses the second TXD line as output

for the logic analyzer. This can be changed to the original TXD

line by specifying "j2" instead of "f4" in the constraints file.