URL https://opencores.org/ocsvn/logicprobe/logicprobe/trunk

Subversion Repositories logicprobe

[/] [logicprobe/] [trunk/] [tst/] [sim-v/] [Makefile] - Blame information for rev 5

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#
# Makefile to build a simulation of the test circuit
#
 
all:            dump.vcd
 
show:           dump.vcd
                gtkwave dump.vcd top.cfg
 
dump.vcd:       top
                ./top
 
top:            top.v
                iverilog -Wall -o top top.v
 
clean:
                rm -f *~ top dump.vcd

Line No.	Rev	Author	Line
1	5	hellwig	`#`
2			`# Makefile to build a simulation of the test circuit`
3			`#`
4
5			`all: dump.vcd`
6
7			`show: dump.vcd`
8			`gtkwave dump.vcd top.cfg`
9
10			`dump.vcd: top`
11			`./top`
12
13			`top: top.v`
14			`iverilog -Wall -o top top.v`
15
16			`clean:`
17			`rm -f *~ top dump.vcd`

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Subversion Repositories logicprobe

[/] [logicprobe/] [trunk/] [tst/] [sim-v/] [Makefile] - Blame information for rev 5