1 |
2 |
unicore |
---------------------------------------------------------------------
|
2 |
|
|
---- ----
|
3 |
|
|
---- IIR Filter IP core ----
|
4 |
|
|
---- ----
|
5 |
|
|
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
|
6 |
|
|
---- Company: Unicore Systems http://unicore.co.ua ----
|
7 |
|
|
---- ----
|
8 |
|
|
---- Downloaded from: http://www.opencores.org ----
|
9 |
|
|
---- ----
|
10 |
|
|
---------------------------------------------------------------------
|
11 |
|
|
---- ----
|
12 |
|
|
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
|
13 |
|
|
---- www.unicore.co.ua ----
|
14 |
|
|
---- o.uzenkov@unicore.co.ua ----
|
15 |
|
|
---- ----
|
16 |
|
|
---- This source file may be used and distributed without ----
|
17 |
|
|
---- restriction provided that this copyright statement is not ----
|
18 |
|
|
---- removed from the file and that any derivative work contains ----
|
19 |
|
|
---- the original copyright notice and the associated disclaimer.----
|
20 |
|
|
---- ----
|
21 |
|
|
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
|
22 |
|
|
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
|
23 |
|
|
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
|
24 |
|
|
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
|
25 |
|
|
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
|
26 |
|
|
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
|
27 |
|
|
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
28 |
|
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
|
29 |
|
|
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
|
30 |
|
|
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
|
31 |
|
|
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
|
32 |
|
|
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
|
33 |
|
|
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
34 |
|
|
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
|
35 |
|
|
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
|
36 |
|
|
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
|
37 |
|
|
---- ----
|
38 |
|
|
---------------------------------------------------------------------
|
39 |
|
|
|
40 |
|
|
|
41 |
|
|
library IEEE;
|
42 |
|
|
use IEEE.STD_LOGIC_1164.all;
|
43 |
|
|
use IEEE.STD_LOGIC_ARITH.all;
|
44 |
|
|
use IEEE.STD_LOGIC_SIGNED.all;
|
45 |
|
|
|
46 |
|
|
entity LPF3x8 is
|
47 |
|
|
port(
|
48 |
|
|
CLK : in STD_LOGIC;
|
49 |
|
|
RST : in STD_LOGIC;
|
50 |
|
|
EF : in STD_LOGIC;
|
51 |
|
|
FREQ : in STD_LOGIC_VECTOR(11 downto 0);
|
52 |
|
|
DI : in STD_LOGIC_VECTOR(15 downto 0);
|
53 |
|
|
DO : out STD_LOGIC_VECTOR(15 downto 0)
|
54 |
|
|
);
|
55 |
|
|
end LPF3x8;
|
56 |
|
|
|
57 |
|
|
|
58 |
|
|
architecture WAVE3x8 of LPF3x8 is
|
59 |
|
|
component DELAY is
|
60 |
|
|
generic(nn:natural;--data width
|
61 |
|
|
l:natural:=8); --FIFO length
|
62 |
|
|
port(
|
63 |
|
|
CLK : in STD_LOGIC;
|
64 |
|
|
CE: in STD_LOGIC; --shift enable
|
65 |
|
|
D : in STD_LOGIC_VECTOR(nn-1 downto 0); --Data in
|
66 |
|
|
Q : out STD_LOGIC_VECTOR(nn-1 downto 0) --Data out
|
67 |
|
|
);
|
68 |
|
|
end component;
|
69 |
|
|
component Calculator is
|
70 |
|
|
port(CLK : in STD_LOGIC;
|
71 |
|
|
RST : in STD_LOGIC;
|
72 |
|
|
EF : in STD_LOGIC;
|
73 |
|
|
F : in STD_LOGIC_VECTOR(11 downto 0);
|
74 |
|
|
A0 : out STD_LOGIC_VECTOR(11 downto 0);
|
75 |
|
|
A1 : out STD_LOGIC_VECTOR(11 downto 0);
|
76 |
|
|
B1 : out STD_LOGIC_VECTOR(11 downto 0);
|
77 |
|
|
SH : out STD_LOGIC_VECTOR(3 downto 0));
|
78 |
|
|
end component;
|
79 |
|
|
constant cc:integer:=(3+4)mod 6;
|
80 |
|
|
signal st,st2,st3:natural range 0 to 7;
|
81 |
|
|
signal ce:std_logic;
|
82 |
|
|
signal did:std_logic_vector(15 downto 0);
|
83 |
|
|
signal dd1,dd2,dod:std_logic_vector(18 downto 0);
|
84 |
|
|
signal tt2,tt2d1,tt2d2,t2z2i:std_logic_vector(20 downto 0):=(others=>'0');
|
85 |
|
|
signal t3,t2,t1:std_logic_vector(17+11+1 downto 0):=(others=>'0');
|
86 |
|
|
signal a0,a1,b1, a0d,a1d,b1d:std_logic_vector(11 downto 0):=(others=>'0');
|
87 |
|
|
signal doi:std_logic_vector(18 downto 0);
|
88 |
|
|
signal doii:std_logic_vector(19 downto 0);
|
89 |
|
|
signal d_z2:std_logic_vector(20 downto 0);
|
90 |
|
|
|
91 |
|
|
signal z2,z2i,z2d1,z2d2:std_logic_vector(20 downto 0);
|
92 |
|
|
signal tt2_z1,tt1i:std_logic_vector(21 downto 0);
|
93 |
|
|
signal z1,z1i,z1d1,z1d2,t1z1,tt1,d1_3,d1_4,d56_1,d78_1:std_logic_vector(21 downto 0);
|
94 |
|
|
signal z3,z3i,z3d1,z3d2,t3z3:std_logic_vector(19 downto 0);
|
95 |
|
|
signal d2_3,d2_4:std_logic_vector(20 downto 0);
|
96 |
|
|
signal t2z2,t2z2d1,t2z2d2,t2z2_z3,tt3: std_logic_vector(19 downto 0);
|
97 |
|
|
signal z4,z4i:std_logic_vector(18 downto 0);
|
98 |
|
|
signal d3_3,d3_4:std_logic_vector(19 downto 0);
|
99 |
|
|
signal d56_2:std_logic_vector(20 downto 0);
|
100 |
|
|
signal d56_3:std_logic_vector(19 downto 0);
|
101 |
|
|
signal d78_2:std_logic_vector(20 downto 0);
|
102 |
|
|
signal d78_3:std_logic_vector(19 downto 0);
|
103 |
|
|
signal d4_30,d4_40, d4_3,d4_4,d56_4,d78_4:std_logic_vector(18 downto 0);
|
104 |
|
|
signal sel56_1,sel56_2,sel78_1,sel78_2:std_logic;
|
105 |
|
|
signal f: STD_LOGIC_VECTOR(11 downto 0);
|
106 |
|
|
signal fn: STD_LOGIC_VECTOR(8 downto 0);
|
107 |
|
|
signal sh: STD_LOGIC_VECTOR(3 downto 0);
|
108 |
|
|
signal prob,prob2,prob3,prob4:integer:=0;
|
109 |
|
|
|
110 |
|
|
constant zy:std_logic_vector(1 downto 0):="00";
|
111 |
|
|
--коэффициенты фильтров
|
112 |
|
|
-- signal b1_3,a1_3,a0_3, b1_4,a1_4,a0_4:std_logic_vector(15 downto 0);
|
113 |
|
|
|
114 |
|
|
--bez rassota koefficientow
|
115 |
|
|
constant b1_1:std_logic_vector(11 downto 0):=
|
116 |
|
|
CONV_STD_LOGIC_VECTOR(integer(0.5317*2048.0),12);
|
117 |
|
|
constant a1_1:std_logic_vector(11 downto 0):=
|
118 |
|
|
CONV_STD_LOGIC_VECTOR(integer(-0.440918*2048.0),12);
|
119 |
|
|
constant a0_1:std_logic_vector(11 downto 0):=
|
120 |
|
|
CONV_STD_LOGIC_VECTOR(integer(0.2462*2048.0),12);
|
121 |
|
|
-- constant b1_2:std_logic_vector(11 downto 0):=
|
122 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.405*2048.0),12);
|
123 |
|
|
-- constant a1_2:std_logic_vector(11 downto 0):=
|
124 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(-0.1807*2048.0),12);
|
125 |
|
|
-- constant a0_2:std_logic_vector(11 downto 0):=
|
126 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.1041*2048.0),12);
|
127 |
|
|
-- constant b1_3:std_logic_vector(11 downto 0):=
|
128 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.427*2048.0),12);
|
129 |
|
|
-- constant a1_3:std_logic_vector(11 downto 0):=
|
130 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(-0.1922*2048.0),12);
|
131 |
|
|
-- constant a0_3:std_logic_vector(11 downto 0):=
|
132 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.1221*2048.0),12);
|
133 |
|
|
-- constant b1_4:std_logic_vector(11 downto 0):=
|
134 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.427*2048.0),12);
|
135 |
|
|
-- constant a1_4:std_logic_vector(11 downto 0):=
|
136 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(-0.1922*2048.0),12);
|
137 |
|
|
-- constant a0_4:std_logic_vector(11 downto 0):=
|
138 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.1221*2048.0),12);
|
139 |
|
|
-- constant b1_5:std_logic_vector(11 downto 0):=
|
140 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.427*2048.0),12);
|
141 |
|
|
-- constant a1_5:std_logic_vector(11 downto 0):=
|
142 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(-0.1922*2048.0),12);
|
143 |
|
|
-- constant a0_5:std_logic_vector(11 downto 0):=
|
144 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.1221*2048.0),12);
|
145 |
|
|
-- constant b1_6:std_logic_vector(11 downto 0):=
|
146 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.427*2048.0),12);
|
147 |
|
|
-- constant a1_6:std_logic_vector(11 downto 0):=
|
148 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(-0.1922*2048.0),12);
|
149 |
|
|
-- constant a0_6:std_logic_vector(11 downto 0):=
|
150 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.1221*2048.0),12);
|
151 |
|
|
-- constant b1_7:std_logic_vector(11 downto 0):=
|
152 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.507*2048.0),12);
|
153 |
|
|
-- constant a1_7:std_logic_vector(11 downto 0):=
|
154 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(-0.662*2048.0),12);
|
155 |
|
|
-- constant a0_7:std_logic_vector(11 downto 0):=
|
156 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.314*2048.0),12);
|
157 |
|
|
-- constant b1_8:std_logic_vector(11 downto 0):=
|
158 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.507*2048.0),12);
|
159 |
|
|
-- constant a1_8:std_logic_vector(11 downto 0):=
|
160 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(-0.662*2048.0),12);
|
161 |
|
|
-- constant a0_8:std_logic_vector(11 downto 0):=
|
162 |
|
|
-- CONV_STD_LOGIC_VECTOR(integer(0.314*2048.0),12);
|
163 |
|
|
|
164 |
|
|
signal a0_x,a1_x,b1_x:std_logic_vector(11 downto 0);
|
165 |
|
|
constant c17: std_logic_vector(11 downto 0):=X"440";
|
166 |
|
|
constant c15: std_logic_vector(9 downto 0):="0011110000"; --уст.f при 0.25
|
167 |
|
|
constant c3: std_logic_vector(11 downto 0):="000000101000";
|
168 |
|
|
constant c150: std_logic_vector(9 downto 0):="0011100010"; --уст.f при 0.25
|
169 |
|
|
|
170 |
|
|
begin
|
171 |
|
|
ce<='1';
|
172 |
|
|
|
173 |
|
|
--sh<="0001" when f(11)='1' or f(10)='1' else
|
174 |
|
|
-- "0010" when f(9)='1' else
|
175 |
|
|
-- "0100" when f(8)='1' else "1000";
|
176 |
|
|
-- with sh select
|
177 |
|
|
-- fn<=f(11 downto 3) when "0001",
|
178 |
|
|
-- f(10 downto 2) when "0010",
|
179 |
|
|
-- f(9 downto 1) when "0100",
|
180 |
|
|
-- f(8 downto 0) when others;
|
181 |
|
|
--
|
182 |
|
|
-- RG_F: process(CLK,RST) --frequency register and coefficient calculator
|
183 |
|
|
-- variable a1n: std_logic_vector(9 downto 0);
|
184 |
|
|
-- variable a0n: std_logic_vector(11 downto 0);
|
185 |
|
|
-- variable a1_xi: std_logic_vector(12 downto 0);
|
186 |
|
|
-- begin
|
187 |
|
|
-- if RST='1' then
|
188 |
|
|
-- f<=(others=>'0');
|
189 |
|
|
-- b1_x<=(others=>'0');
|
190 |
|
|
-- a1_x<=(others=>'0');
|
191 |
|
|
-- a0_x<=(others=>'0');
|
192 |
|
|
--
|
193 |
|
|
-- elsif rising_edge(CLK) then
|
194 |
|
|
-- if EF='1' then
|
195 |
|
|
-- f<=FREQ;
|
196 |
|
|
-- end if;
|
197 |
|
|
-- b1_x<= (signed(c17) - signed("000" & fn));
|
198 |
|
|
-- -- if f(11)='1' then
|
199 |
|
|
---- b1_x<=X"340";
|
200 |
|
|
---- end if;
|
201 |
|
|
--
|
202 |
|
|
-- if f(11)='1' or f(10)='1' then
|
203 |
|
|
-- a1n:=('0'&fn) - c150; --0th mode
|
204 |
|
|
-- else
|
205 |
|
|
-- a1n:=('0'&fn) - c15;
|
206 |
|
|
-- end if;
|
207 |
|
|
-- -- if f(11)='1' or f(10)='1' then
|
208 |
|
|
-- -- a1_x<=SHL(signed( a1n & "000000")+ signed(a1n & "0000")+ signed(a1n & "000"),"01"); --уст.f при 0.125
|
209 |
|
|
-- -- else
|
210 |
|
|
-- -- a1_x<=SHL(signed( a1n & "000000")+ signed(a1n & "0000")+ signed(a1n & "000"),"01"); --уст.f при 0.0625
|
211 |
|
|
-- --
|
212 |
|
|
-- -- end if;
|
213 |
|
|
-- a1_xi:=signed( a1n & "000")+ signed(a1n&'1' )+ signed(a1n); --уст.f при 0.125
|
214 |
|
|
-- a1_x<=a1_xi(11 downto 0);
|
215 |
|
|
-- a0n:= c3 - (a1_x(11)&a1_x(11)&a1_x(11 downto 2) + a1_x(11 downto 3)+
|
216 |
|
|
-- a1_x(11 downto 5));
|
217 |
|
|
-- a0_x<=a0n;
|
218 |
|
|
-- end if;
|
219 |
|
|
-- end process;
|
220 |
|
|
|
221 |
|
|
U_C:Calculator port map(CLK,RST,
|
222 |
|
|
EF =>EF,
|
223 |
|
|
F =>FREQ,
|
224 |
|
|
A0 =>a0_x,
|
225 |
|
|
A1 =>a1_x,
|
226 |
|
|
B1 =>b1_x,
|
227 |
|
|
SH =>sh);
|
228 |
|
|
|
229 |
|
|
--b1_3<=b1_x;
|
230 |
|
|
-- a1_3<=a1_x;
|
231 |
|
|
-- a0_3<=a0_x;
|
232 |
|
|
-- b1_4<=b1_x;
|
233 |
|
|
-- a1_4<=a1_x;
|
234 |
|
|
-- a0_4<=a0_x;
|
235 |
|
|
|
236 |
|
|
CT_ST: process(CLK,RST) --phase counter
|
237 |
|
|
begin
|
238 |
|
|
if RST='1' then
|
239 |
|
|
st<=0;
|
240 |
|
|
elsif rising_edge(CLK) then
|
241 |
|
|
if st=7 then
|
242 |
|
|
st<=0;
|
243 |
|
|
else
|
244 |
|
|
st<=st+1;
|
245 |
|
|
end if;
|
246 |
|
|
end if;
|
247 |
|
|
end process;
|
248 |
|
|
|
249 |
|
|
-- MUX_A0:with st select --uncontrolled filters
|
250 |
|
|
-- a0<=a0_1 when 4,
|
251 |
|
|
-- a0_2 when 5,
|
252 |
|
|
-- a0_3 when 6,
|
253 |
|
|
-- a0_4 when 7,
|
254 |
|
|
-- a0_5 when 0,
|
255 |
|
|
-- a0_6 when 1,
|
256 |
|
|
-- a0_7 when 2,
|
257 |
|
|
-- a0_8 when others;
|
258 |
|
|
-- MUX_A1:with st select
|
259 |
|
|
-- a1<=a1_1 when 4,
|
260 |
|
|
-- a1_2 when 5,
|
261 |
|
|
-- a1_3 when 6,
|
262 |
|
|
-- a1_4 when 7,
|
263 |
|
|
-- a1_5 when 0,
|
264 |
|
|
-- a1_6 when 1,
|
265 |
|
|
-- a1_7 when 2,
|
266 |
|
|
-- a1_8 when others;
|
267 |
|
|
-- MUX_B:with st select
|
268 |
|
|
-- b1<=b1_1 when 1,
|
269 |
|
|
-- b1_2 when 2,
|
270 |
|
|
-- b1_3 when 3,
|
271 |
|
|
-- b1_4 when 4,
|
272 |
|
|
-- b1_5 when 5,
|
273 |
|
|
-- b1_6 when 6,
|
274 |
|
|
-- b1_7 when 7,
|
275 |
|
|
-- b1_8 when others;
|
276 |
|
|
|
277 |
|
|
MUX_A0: a0<=a0_x when (sh(0)='1') or --and (st=4 or st=5 or st=6 or st=7)
|
278 |
|
|
(sh(1)='1' and ( st=6 or st=7)) or
|
279 |
|
|
(sh(2)='1' and ( st=0 or st=1)) or
|
280 |
|
|
(sh(3)='1' and ( st=2 or st=3)) else a0_1;
|
281 |
|
|
|
282 |
|
|
MUX_A1: a1<=a1_x when (sh(0)='1') or --and (st=4 or st=5 or st=6 or st=7)
|
283 |
|
|
(sh(1)='1' and ( st=6 or st=7)) or
|
284 |
|
|
(sh(2)='1' and ( st=0 or st=1)) or
|
285 |
|
|
(sh(3)='1' and ( st=2 or st=3)) else a1_1;
|
286 |
|
|
|
287 |
|
|
MUX_B1: b1<=b1_x when (sh(0)='1' ) or --and (st=1 or st=2 or st=3 or st=4)
|
288 |
|
|
(sh(1)='1' and ( st=3 or st=4)) or
|
289 |
|
|
(sh(2)='1' and ( st=5 or st=6)) or
|
290 |
|
|
(sh(3)='1' and ( st=7 or st=0)) else b1_1;
|
291 |
|
|
|
292 |
|
|
|
293 |
|
|
Wave2:process(CLK,RST)
|
294 |
|
|
variable dii:std_logic_vector(18 downto 0);
|
295 |
|
|
begin
|
296 |
|
|
if RST='1' then
|
297 |
|
|
a1d <=(others=>'0');
|
298 |
|
|
b1d <=(others=>'0');
|
299 |
|
|
did <=(others=>'0');
|
300 |
|
|
dd1 <=(others=>'0');
|
301 |
|
|
dd2 <=(others=>'0');
|
302 |
|
|
z1d1 <=(others=>'0');
|
303 |
|
|
z1d2 <=(others=>'0');
|
304 |
|
|
z2d1 <=(others=>'0');
|
305 |
|
|
z2d2 <=(others=>'0');
|
306 |
|
|
tt2d1 <=(others=>'0');
|
307 |
|
|
tt2d2 <=(others=>'0');
|
308 |
|
|
-- tt1 <=(others=>'0');
|
309 |
|
|
-- t1z1 <=(others=>'0');
|
310 |
|
|
d_z2<=(others=>'0');
|
311 |
|
|
tt2_z1<=(others=>'0');
|
312 |
|
|
elsif rising_edge(CLK) then
|
313 |
|
|
a1d<=a1;
|
314 |
|
|
b1d<=b1;
|
315 |
|
|
if st=0 then
|
316 |
|
|
did<=DI;
|
317 |
|
|
end if;
|
318 |
|
|
if st=1 then
|
319 |
|
|
dii:=did(15)&did&zy;
|
320 |
|
|
else
|
321 |
|
|
dii:= dod; -- (others=>'0');-- connecting a chain
|
322 |
|
|
end if;
|
323 |
|
|
dd1<=dii;
|
324 |
|
|
dd2<=dd1;
|
325 |
|
|
z1d1<=z1;
|
326 |
|
|
z1d2<=z1d1;
|
327 |
|
|
z2d1<=z2;
|
328 |
|
|
z2d2<=z2d1;
|
329 |
|
|
|
330 |
|
|
d_z2<=dii - z2;
|
331 |
|
|
tt2<=dd2 + t2(28 downto 8);
|
332 |
|
|
tt2d1<=tt2;
|
333 |
|
|
tt2d2<=tt2d1;
|
334 |
|
|
|
335 |
|
|
tt2_z1<=tt2(20)&tt2 - z1;
|
336 |
|
|
|
337 |
|
|
end if;
|
338 |
|
|
end process;
|
339 |
|
|
tt1i<=tt2d2(20)&tt2d2+ t1(28 downto 7);
|
340 |
|
|
tt1<=tt1i(21 downto 0);
|
341 |
|
|
t1z1<=z1d2+ t1(27 downto 7);
|
342 |
|
|
|
343 |
|
|
|
344 |
|
|
MULR: process(CLK) -- multiplier registers
|
345 |
|
|
begin
|
346 |
|
|
if rising_edge(CLK) then
|
347 |
|
|
t1<=tt2_z1(21 downto 4)*a1d;
|
348 |
|
|
t2<=d_z2(20 downto 3)*b1d;
|
349 |
|
|
t3<=a0d*t2z2_z3(19 downto 2);
|
350 |
|
|
end if;
|
351 |
|
|
end process;
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
|
357 |
|
|
Wave1: process(CLK,RST) -- wave stage of 1st order
|
358 |
|
|
begin
|
359 |
|
|
if RST='1' then
|
360 |
|
|
a0d<=(others=>'0');
|
361 |
|
|
t2z2 <=(others=>'0');
|
362 |
|
|
t2z2d1 <=(others=>'0');
|
363 |
|
|
t2z2d2 <=(others=>'0');
|
364 |
|
|
t2z2_z3 <=(others=>'0');
|
365 |
|
|
--tt3 <=(others=>'0');
|
366 |
|
|
z3d1 <=(others=>'0');
|
367 |
|
|
z3d2 <=(others=>'0');
|
368 |
|
|
t3z3 <=(others=>'0');
|
369 |
|
|
-- doi <=(others=>'0');
|
370 |
|
|
DO <=(others=>'0');
|
371 |
|
|
elsif rising_edge(CLK) then
|
372 |
|
|
t2z2<=t2z2i(19 downto 0);
|
373 |
|
|
t2z2d1<=t2z2;
|
374 |
|
|
t2z2d2<=t2z2d1;
|
375 |
|
|
t2z2_z3<=t2z2 - z3;
|
376 |
|
|
a0d<=a0;
|
377 |
|
|
z3d1<=z3;
|
378 |
|
|
z3d2<=z3d1;
|
379 |
|
|
t3z3<=z3d2 + t3(28 downto 9);
|
380 |
|
|
|
381 |
|
|
if st=6 then -- st=7
|
382 |
|
|
DO<=doi(17 downto 2); --result st=7- 1st stage
|
383 |
|
|
end if; -- st=0 - 2nd stage...
|
384 |
|
|
|
385 |
|
|
end if;
|
386 |
|
|
end process;
|
387 |
|
|
t2z2i<=z2d2 + t2(28 downto 8);--+1;
|
388 |
|
|
|
389 |
|
|
tt3<=t3(28 downto 9)+t2z2d2;--+1;
|
390 |
|
|
|
391 |
|
|
doii<=SXT(z4,20) when ((sh(0)='1' or sh(1)='1') and (st=3 or st=4 or st=5 or st=6)) or
|
392 |
|
|
(sh(2)='1' and (st=5 or st=6)) else --пропуск каскада
|
393 |
|
|
SHR((z4+t3z3+1),"01"); --результат округленный --+ LPF, - HPF
|
394 |
|
|
-- doi<=SHR((z4+t3z3),"01"); --+ LPF, - HPF
|
395 |
|
|
doi<=doii(18 downto 0);
|
396 |
|
|
RG_DEL:process(CLK,RST) -- доп.задержки для 3 и 4 каскадов
|
397 |
|
|
begin
|
398 |
|
|
if RST='1' then
|
399 |
|
|
d1_4 <=(others=>'0');
|
400 |
|
|
d2_4 <=(others=>'0');
|
401 |
|
|
d3_4 <=(others=>'0');
|
402 |
|
|
d4_4 <=(others=>'0');
|
403 |
|
|
d4_40 <=(others=>'0');
|
404 |
|
|
d1_3 <=(others=>'0');
|
405 |
|
|
d2_3 <=(others=>'0');
|
406 |
|
|
d3_3 <=(others=>'0');
|
407 |
|
|
d4_30 <=(others=>'0');
|
408 |
|
|
d4_3 <=(others=>'0');
|
409 |
|
|
elsif rising_edge(CLK) then
|
410 |
|
|
if st=(6+2)mod 8 or st=(6+3) mod 8 then --+2 - 3й каскад
|
411 |
|
|
d1_3<=tt1; --4 th stage
|
412 |
|
|
d2_3<=t1z1(20 downto 0);
|
413 |
|
|
d3_3<=tt3;
|
414 |
|
|
d1_4<=d1_3;
|
415 |
|
|
d2_4<=d2_3;
|
416 |
|
|
d3_4<=d3_3;
|
417 |
|
|
elsif st=3+2 or st=(3+3) mod 8 then
|
418 |
|
|
d4_30<=dd2;
|
419 |
|
|
d4_3<=d4_30; --4 registers in chain
|
420 |
|
|
d4_40<=d4_3;
|
421 |
|
|
d4_4<=d4_40;
|
422 |
|
|
end if;
|
423 |
|
|
|
424 |
|
|
end if;
|
425 |
|
|
end process;
|
426 |
|
|
|
427 |
|
|
sel56_1<='1' when st=((6+4) mod 8) or (st=((6+5) mod 8)) else '0';
|
428 |
|
|
sel56_2<='1' when st=((3+4) mod 8) or (st=((3+5) mod 8)) else '0';
|
429 |
|
|
sel78_1<='1' when st=((6+6) mod 8) or (st=((6+7) mod 8)) else '0';
|
430 |
|
|
sel78_2<='1' when st=((3+6) mod 8) or (st=((3+7) mod 8)) else '0';
|
431 |
|
|
DZ1_56:DELAY generic map(nn=>22,l=>6) --FIFO stages 5,6
|
432 |
|
|
port map(CLK,sel56_1,
|
433 |
|
|
D => tt1,
|
434 |
|
|
Q => d56_1);
|
435 |
|
|
DZ2_56:DELAY generic map(nn=>21,l=>6) --FIFO stages 5,6
|
436 |
|
|
port map(CLK,sel56_1,
|
437 |
|
|
D => t1z1(20 downto 0),
|
438 |
|
|
Q => d56_2);
|
439 |
|
|
DZ3_56:DELAY generic map(nn=>20,l=>6) --FIFO stages 5,6
|
440 |
|
|
port map(CLK,sel56_1,
|
441 |
|
|
D => tt3,
|
442 |
|
|
Q => d56_3);
|
443 |
|
|
DZ4_56:DELAY generic map(nn=>19,l=>12) --FIFO stages 5,6
|
444 |
|
|
port map(CLK,sel56_2,
|
445 |
|
|
D => dd2,
|
446 |
|
|
Q => d56_4);
|
447 |
|
|
|
448 |
|
|
DZ1_78:DELAY generic map(nn=>22,l=>14) --FIFO stages 7,8
|
449 |
|
|
port map(CLK,sel78_1,
|
450 |
|
|
D => tt1,
|
451 |
|
|
Q => d78_1);
|
452 |
|
|
DZ2_78:DELAY generic map(nn=>21,l=>14) --FIFO stages 7,8
|
453 |
|
|
port map(CLK,sel78_1,
|
454 |
|
|
D => t1z1(20 downto 0),
|
455 |
|
|
Q => d78_2);
|
456 |
|
|
DZ3_78:DELAY generic map(nn=>20,l=>14) --FIFO stages 7,8
|
457 |
|
|
port map(CLK,sel78_1,
|
458 |
|
|
D => tt3,
|
459 |
|
|
Q => d78_3);
|
460 |
|
|
DZ4_78:DELAY generic map(nn=>19,l=>28) --FIFO stages 7,8
|
461 |
|
|
port map(CLK,sel78_2,
|
462 |
|
|
D => dd2,
|
463 |
|
|
Q => d78_4);
|
464 |
|
|
|
465 |
|
|
--in sh=0 delays of 3,4st are detached
|
466 |
|
|
st2<=7 when sh(0)='1' and ((st=(6+2) mod 8) or (st= (6+3)mod 8)) else st;
|
467 |
|
|
st3<=4 when sh(0)='1' and ((st=(3+2)) or (st= (3+3)mod 8)) else st;
|
468 |
|
|
|
469 |
|
|
|
470 |
|
|
MXZ1:with st2 select
|
471 |
|
|
z1i<=d1_4 when (6+2) mod 8|(6+3) mod 8,
|
472 |
|
|
d56_1 when ((6+4) mod 8)|((6+5) mod 8),
|
473 |
|
|
d78_1 when ((6+6) mod 8)|((6+7) mod 8),
|
474 |
|
|
tt1 when others;
|
475 |
|
|
MXZ2:with st2 select
|
476 |
|
|
z2i<=d2_4 when (6+2) mod 8|(6+3) mod 8,
|
477 |
|
|
d56_2 when ((6+4) mod 8)|((6+5) mod 8),
|
478 |
|
|
d78_2 when ((6+6) mod 8)|((6+7) mod 8),
|
479 |
|
|
t1z1(20 downto 0) when others;
|
480 |
|
|
MXZ3:with st2 select
|
481 |
|
|
z3i<=d3_4 when (6+2) mod 8|(6+3) mod 8,
|
482 |
|
|
d56_3 when ((6+4) mod 8)|((6+5) mod 8),
|
483 |
|
|
d78_3 when ((6+6) mod 8)|((6+7) mod 8),
|
484 |
|
|
tt3 when others;
|
485 |
|
|
MXZ4:with st3 select
|
486 |
|
|
z4i<=d4_4 when 3+2|(3+3) mod 8,
|
487 |
|
|
d56_4 when ((3+4) mod 8)|((3+5) mod 8),
|
488 |
|
|
d78_4 when ((3+6) mod 8)|((3+7) mod 8),
|
489 |
|
|
dd2 when others;
|
490 |
|
|
|
491 |
|
|
DZ1:DELAY generic map(nn=>22,l=>4+2) --FIFO length=i+(period-6)
|
492 |
|
|
port map(CLK,CE,
|
493 |
|
|
D => z1i, --Data in
|
494 |
|
|
Q => z1);
|
495 |
|
|
DZ2:DELAY generic map(nn=>21,l=>1+2) --FIFO length
|
496 |
|
|
port map(CLK,CE, --shift enable
|
497 |
|
|
D => z2i, --Data in
|
498 |
|
|
Q => z2);
|
499 |
|
|
DZ3:DELAY generic map(nn=>20,l=>4+2) --FIFO length
|
500 |
|
|
port map(CLK,CE, --shift enable
|
501 |
|
|
D => z3i, --Data in
|
502 |
|
|
Q => z3);
|
503 |
|
|
DZ4:DELAY generic map(nn=>19,l=>16+4) --FIFO length
|
504 |
|
|
port map(CLK,CE, --shift enable
|
505 |
|
|
D => z4i, --Data in
|
506 |
|
|
Q => z4);
|
507 |
|
|
DD:DELAY generic map(nn=>19,l=>1+2) --FIFO length
|
508 |
|
|
port map(CLK,CE, --shift enable
|
509 |
|
|
D => doi(18 downto 0), --Data in
|
510 |
|
|
Q => dod);
|
511 |
|
|
|
512 |
|
|
prob<=conv_integer(signed(tt2));
|
513 |
|
|
prob2<=conv_integer(signed(tt1));
|
514 |
|
|
prob3<=conv_integer(signed(d_z2));
|
515 |
|
|
prob4<=conv_integer(signed(tt2_z1));
|
516 |
|
|
|
517 |
|
|
end WAVE3x8;
|