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[/] [lpc/] [trunk/] [gpio/] [rtl/] [lpc_gpio.v] - Blame information for rev 6

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  LPC(Low Pin Count) GPIO(General Purpose Input Output)      ////
////                                                             ////
////                                                             ////
////  Author: Junbing Liang                                      ////
////          Junbing.Liang@googlemail.com                       ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2007 Junbing Liang                            ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
 
module lpc_gpio(LAD,LFRAME,LRESET,LCLK, gpio_addr_i,gpio_i,gpio_o);
 
output   [7:0]  gpio_o;
input    [7:0]  gpio_i;
input   [15:0]  gpio_addr_i;
 
//bus interface
inout   [3:0]   LAD;
input           LFRAME;   //low active
input           LRESET;   //low activate
input           LCLK;      //
 
 
reg      [7:0]   gpio_out_reg;     //output register
reg      [7:0]   gpio_out_reg1;    //use second reg to control the output time
reg      [7:0]   gpio_in_reg;      //input register
reg      [3:0]   lpc_state;
reg      [3:0]   lpc_state_next;
reg      [15:0]  gpio_addr_reg;    //address register
 
reg               write_flag;
 
 
 
//lpc_state_next
always @(LFRAME or lpc_state or LAD)
begin
    if (!LFRAME)
       if (LAD == 4'b0000)
          lpc_state_next <= 1;
       else
          lpc_state_next <= 0;
    else
    begin
       //if address is not match, state will be set to 0
       if (  ((lpc_state == 2) && (LAD != gpio_addr_i[15:12]) )
          || ((lpc_state == 3) && (LAD != gpio_addr_i[11:8]) )
          || ((lpc_state == 4) && (LAD != gpio_addr_i[7:4]) )
          || ((lpc_state == 5) && (LAD != gpio_addr_i[3:0]) )
          || (lpc_state ==4'hc)   //last state
          || (lpc_state ==4'b0000)
          )
          lpc_state_next <= 0;
       else
          lpc_state_next <= lpc_state+4'b0001;
    end
 
end
 
//lpc_state
always @(posedge LCLK)
begin
    if (!LRESET)
       lpc_state <= 0;
    else
      lpc_state <= lpc_state_next;
 
end
 
//write_flag
always @(negedge LCLK)
begin
    if ( (!LRESET)||(!LFRAME)|| (lpc_state==0) )
       write_flag <= 0;   //default is read
    else
    begin
       if (lpc_state ==1)
       begin
           if (LAD==4'b0010)
              write_flag <=1;
           else
              write_flag <=0;   //read for all others
       end
       else
          write_flag <= write_flag;
    end
  end
 
//gpio_addr_reg
always @(negedge LCLK)
begin
    if ( (!LRESET)||(!LFRAME) )
       gpio_addr_reg <= 0;
    else
    begin
        case (lpc_state)
            2: gpio_addr_reg[15:12] <= LAD;
            3: gpio_addr_reg[11:8]  <= LAD;
            4: gpio_addr_reg[7:4]   <= LAD;
            5: gpio_addr_reg[3:0]   <= LAD;
            default:
               gpio_addr_reg <= gpio_addr_reg;
       endcase;
    end
end
 
//gpio_out_reg
always @(negedge LCLK)
begin
    if (!LRESET)
       gpio_out_reg <= 0;
    else
    begin
       if ((write_flag) && (gpio_addr_reg == gpio_addr_i))
            case (lpc_state)
               6:gpio_out_reg[7:4] <= LAD;
               7:gpio_out_reg[3:0] <= LAD;
               default:
                  gpio_out_reg <= gpio_out_reg;
            endcase
       else
          gpio_out_reg <= gpio_out_reg;
    end
end
 
 
 
//gpio_out_reg1
//use second output register to control the output time
always @ (posedge LCLK)
begin
   if (!LRESET)
      gpio_out_reg1 <= 0;
   else
      if (lpc_state == 4'hc)
         gpio_out_reg1 <= gpio_out_reg;
      else
         gpio_out_reg1 <= gpio_out_reg1;
end
 
 
 
 
 
assign gpio_o = LRESET?gpio_out_reg1:8'hzz;
assign LAD[3:0] = //bus read data from gpio input
                  (!write_flag && lpc_state==8)  ? 4'b1111 :      //sync
                  (!write_flag && lpc_state==9)  ? gpio_i[7:4] :
                  (!write_flag && lpc_state==10) ? gpio_i[3:0] :
                  (!write_flag && lpc_state==11) ? 4'b1111:       //first TAR
 
                  //bus write to gpio output
                  (write_flag && lpc_state==10)  ?  4'b0000:     //sync
                  (write_flag && lpc_state==11)  ?  4'b1111:     //first TAR
                  4'bzzzz;
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	4	junbing	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// LPC(Low Pin Count) GPIO(General Purpose Input Output) ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Junbing Liang ////`
7			`//// Junbing.Liang@googlemail.com ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2007 Junbing Liang ////`
15			`//// ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38
39			`module lpc_gpio(LAD,LFRAME,LRESET,LCLK, gpio_addr_i,gpio_i,gpio_o);`
40
41			`output [7:0] gpio_o;`
42			`input [7:0] gpio_i;`
43			`input [15:0] gpio_addr_i;`
44
45			`//bus interface`
46			`inout [3:0] LAD;`
47			`input LFRAME; //low active`
48			`input LRESET; //low activate`
49			`input LCLK; //`
50
51
52			`reg [7:0] gpio_out_reg; //output register`
53			`reg [7:0] gpio_out_reg1; //use second reg to control the output time`
54			`reg [7:0] gpio_in_reg; //input register`
55			`reg [3:0] lpc_state;`
56			`reg [3:0] lpc_state_next;`
57			`reg [15:0] gpio_addr_reg; //address register`
58
59			`reg write_flag;`
60
61
62
63			`//lpc_state_next`
64			`always @(LFRAME or lpc_state or LAD)`
65			`begin`
66			`if (!LFRAME)`
67			`if (LAD == 4'b0000)`
68			`lpc_state_next <= 1;`
69			`else`
70			`lpc_state_next <= 0;`
71			`else`
72			`begin`
73			`//if address is not match, state will be set to 0`
74			`if ( ((lpc_state == 2) && (LAD != gpio_addr_i[15:12]) )`
75			`\|\| ((lpc_state == 3) && (LAD != gpio_addr_i[11:8]) )`
76			`\|\| ((lpc_state == 4) && (LAD != gpio_addr_i[7:4]) )`
77			`\|\| ((lpc_state == 5) && (LAD != gpio_addr_i[3:0]) )`
78			`\|\| (lpc_state ==4'hc) //last state`
79			`\|\| (lpc_state ==4'b0000)`
80			`)`
81			`lpc_state_next <= 0;`
82			`else`
83			`lpc_state_next <= lpc_state+4'b0001;`
84			`end`
85
86			`end`
87
88			`//lpc_state`
89			`always @(posedge LCLK)`
90			`begin`
91			`if (!LRESET)`
92			`lpc_state <= 0;`
93			`else`
94			`lpc_state <= lpc_state_next;`
95
96			`end`
97
98			`//write_flag`
99			`always @(negedge LCLK)`
100			`begin`
101			`if ( (!LRESET)\|\|(!LFRAME)\|\| (lpc_state==0) )`
102			`write_flag <= 0; //default is read`
103			`else`
104			`begin`
105			`if (lpc_state ==1)`
106			`begin`
107			`if (LAD==4'b0010)`
108			`write_flag <=1;`
109			`else`
110			`write_flag <=0; //read for all others`
111			`end`
112			`else`
113			`write_flag <= write_flag;`
114			`end`
115			`end`
116
117			`//gpio_addr_reg`
118			`always @(negedge LCLK)`
119			`begin`
120			`if ( (!LRESET)\|\|(!LFRAME) )`
121			`gpio_addr_reg <= 0;`
122			`else`
123			`begin`
124			`case (lpc_state)`
125			`2: gpio_addr_reg[15:12] <= LAD;`
126			`3: gpio_addr_reg[11:8] <= LAD;`
127			`4: gpio_addr_reg[7:4] <= LAD;`
128			`5: gpio_addr_reg[3:0] <= LAD;`
129			`default:`
130			`gpio_addr_reg <= gpio_addr_reg;`
131			`endcase;`
132			`end`
133			`end`
134
135			`//gpio_out_reg`
136			`always @(negedge LCLK)`
137			`begin`
138			`if (!LRESET)`
139			`gpio_out_reg <= 0;`
140			`else`
141			`begin`
142			`if ((write_flag) && (gpio_addr_reg == gpio_addr_i))`
143			`case (lpc_state)`
144			`6:gpio_out_reg[7:4] <= LAD;`
145			`7:gpio_out_reg[3:0] <= LAD;`
146			`default:`
147			`gpio_out_reg <= gpio_out_reg;`
148			`endcase`
149			`else`
150			`gpio_out_reg <= gpio_out_reg;`
151			`end`
152			`end`
153
154
155
156			`//gpio_out_reg1`
157			`//use second output register to control the output time`
158			`always @ (posedge LCLK)`
159			`begin`
160			`if (!LRESET)`
161			`gpio_out_reg1 <= 0;`
162			`else`
163			`if (lpc_state == 4'hc)`
164			`gpio_out_reg1 <= gpio_out_reg;`
165			`else`
166			`gpio_out_reg1 <= gpio_out_reg1;`
167			`end`
168
169
170
171
172
173			`assign gpio_o = LRESET?gpio_out_reg1:8'hzz;`
174			`assign LAD[3:0] = //bus read data from gpio input`
175			`(!write_flag && lpc_state==8) ? 4'b1111 : //sync`
176			`(!write_flag && lpc_state==9) ? gpio_i[7:4] :`
177			`(!write_flag && lpc_state==10) ? gpio_i[3:0] :`
178			`(!write_flag && lpc_state==11) ? 4'b1111: //first TAR`
179
180			`//bus write to gpio output`
181			`(write_flag && lpc_state==10) ? 4'b0000: //sync`
182			`(write_flag && lpc_state==11) ? 4'b1111: //first TAR`
183			`4'bzzzz;`
184
185
186
187
188
189			`endmodule`

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[/] [lpc/] [trunk/] [gpio/] [rtl/] [lpc_gpio.v] - Blame information for rev 6