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[/] [lpffir/] [trunk/] [doc/] [src/] [axis_timing.tim] - Blame information for rev 6

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Timing Analyzer Settings
     Version:           0.991
     Time_Scale:        1.0E-9
     Time_Per_Division: 64
     Number_Divisions:  160
     Start_Time:        0
     End_Time:          750
Part_Constraint
     Name:               thold
     Min_Constraint:     4.0
     Max_Constraint:     4.0
     Description:        Example hold constraint
Part_Constraint_End
Part_Constraint
     Name:               tsetup
     Min_Constraint:     10.0
     Max_Constraint:     10.0
     Description:        Example setup constraint
Part_Constraint_End
Jitter_Margin
     Name:               p1jitter
     Plus_Margin:        1.0
     Minus_Margin:       1.0
     Description:        Example part jitter
Jitter_Margin_End
Jitter_Margin
     Name:               p2jitter
     Plus_Margin:        0.5
     Minus_Margin:       0.5
     Description:        Example part jitter
Jitter_Margin_End
Digital_Clock
     Position:          1
     Name:              aclk_i
     Frequency:         1.0E7
     Duty_Cycle:        50
     Start_Delay:       0.0
     Start_State:       L
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Input
Digital_Clock_End
Digital_Signal
     Position:          2
     Name:              rx_tlast_i
     Start_State:       L
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Input
     Sync_Clock:        aclk_i
          Edge
              Min:             556.211
              Max:             556.211
              State:            H
          Edge_End
          Edge
              Min:             656.211
              Max:             656.211
              State:            L
          Edge_End
Digital_Signal_End
Digital_Signal
     Position:          3
     Name:              rx_tvalid_i
     Start_State:       L
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Input
     Sync_Clock:        aclk_i
          Edge
              Min:             53.311
              Max:             172.471
              State:            H
          Edge_End
          Edge
              Min:             453.981
              Max:             453.981
              State:            L
          Edge_End
          Edge
              Min:             557.201
              Max:             557.201
              State:            H
          Edge_End
          Edge
              Min:             657.201
              Max:             657.201
              State:            L
          Edge_End
Digital_Signal_End
Digital_Signal
     Position:          4
     Name:              rx_tready_o
     Start_State:       L
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Output
     Sync_Clock:        aclk_i
          Edge
              Min:             98.781
              Max:             98.781
              State:            H
          Edge_End
          Edge
              Min:             157.201
              Max:             157.201
              State:            L
          Edge_End
          Edge
              Min:             257.201
              Max:             257.201
              State:            H
          Edge_End
          Edge
              Min:             868.401
              Max:             868.401
              State:            L
          Edge_End
Digital_Signal_End
Digital_Bus
     Position:          5
     Name:              rx_tdate_i[7:0]
     Start_State:       X
     State_Format:      Text
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Input
     Sync_Clock:        aclk_i
          Edge
              Min:             53.151
              Max:             53.151
              State:            DI1
          Edge_End
          Edge
              Min:             156.031
              Max:             156.031
              State:            DI2
          Edge_End
          Edge
              Min:             357.731
              Max:             357.731
              State:            DI3
          Edge_End
          Edge
              Min:             453.121
              Max:             453.121
              State:            X
          Edge_End
          Edge
              Min:             557.731
              Max:             557.731
              State:            DI4
          Edge_End
          Edge
              Min:             657.731
              Max:             657.731
              State:            X
          Edge_End
          Edge
              Min:             880.091
              Max:             880.091
              State:            Z
          Edge_End
Digital_Bus_End
Digital_Signal
     Position:          6
     Name:              tx_tlast_o
     Start_State:       L
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Output
          Edge
              Min:             556.211
              Max:             556.211
              State:            H
          Edge_End
          Edge
              Min:             656.211
              Max:             656.211
              State:            L
          Edge_End
Digital_Signal_End
Digital_Signal
     Position:          7
     Name:              tx_tvalid_o
     Start_State:       L
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Output
          Edge
              Min:             53.311
              Max:             53.311
              State:            H
          Edge_End
          Edge
              Min:             453.981
              Max:             453.981
              State:            L
          Edge_End
          Edge
              Min:             557.201
              Max:             557.201
              State:            H
          Edge_End
          Edge
              Min:             657.201
              Max:             657.201
              State:            L
          Edge_End
Digital_Signal_End
Digital_Signal
     Position:          8
     Name:              tx_tready_i
     Start_State:       L
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Input
          Edge
              Min:             98.781
              Max:             98.781
              State:            H
          Edge_End
          Edge
              Min:             157.201
              Max:             157.201
              State:            L
          Edge_End
          Edge
              Min:             257.201
              Max:             257.201
              State:            H
          Edge_End
          Edge
              Min:             868.401
              Max:             868.401
              State:            L
          Edge_End
Digital_Signal_End
Digital_Bus
     Position:          9
     Name:              tx_tdate_o[7:0]
     Start_State:       X
     State_Format:      Text
     Rise_Time:         5.0
     Fall_Time:         5.0
     IO_Type:           Output
          Edge
              Min:             53.151
              Max:             53.151
              State:            DO1
          Edge_End
          Edge
              Min:             156.031
              Max:             156.031
              State:            DO2
          Edge_End
          Edge
              Min:             357.731
              Max:             357.731
              State:            DO3
          Edge_End
          Edge
              Min:             453.121
              Max:             453.121
              State:            X
          Edge_End
          Edge
              Min:             557.731
              Max:             557.731
              State:            DO4
          Edge_End
          Edge
              Min:             657.731
              Max:             657.731
              State:            X
          Edge_End
          Edge
              Min:             880.091
              Max:             880.091
              State:            Z
          Edge_End
Digital_Bus_End
StateBar
     State_Name:        C2
     Line_Type:         Dashed
     Edge_Position:     50
     State_Color:       #000000
     Font_Name:         Dialog
     Font_Style:        0
     Font_Size:         12
     Signal_Type:       DigitalClock
     Signal_Name:       aclk_i
     Edge_At:           5
     OffsetX:           0
     OffsetY:           0
StateBar_End
StateBar
     State_Name:        C3
     Line_Type:         Dashed
     Edge_Position:     50
     State_Color:       #000000
     Font_Name:         Dialog
     Font_Style:        0
     Font_Size:         12
     Signal_Type:       DigitalClock
     Signal_Name:       aclk_i
     Edge_At:           7
     OffsetX:           0
     OffsetY:           0
StateBar_End
StateBar
     State_Name:        C1
     Line_Type:         Dashed
     Edge_Position:     50
     State_Color:       #000000
     Font_Name:         Dialog
     Font_Style:        0
     Font_Size:         12
     Signal_Type:       DigitalClock
     Signal_Name:       aclk_i
     Edge_At:           3
     OffsetX:           0
     OffsetY:           0
StateBar_End
StateBar
     State_Name:        C4
     Line_Type:         Dashed
     Edge_Position:     50
     State_Color:       #000000
     Font_Name:         Dialog
     Font_Style:        0
     Font_Size:         12
     Signal_Type:       DigitalClock
     Signal_Name:       aclk_i
     Edge_At:           9
     OffsetX:           0
     OffsetY:           0
StateBar_End
StateBar
     State_Name:        C5
     Line_Type:         Dashed
     Edge_Position:     50
     State_Color:       #000000
     Font_Name:         Dialog
     Font_Style:        0
     Font_Size:         12
     Signal_Type:       DigitalClock
     Signal_Name:       aclk_i
     Edge_At:           11
     OffsetX:           0
     OffsetY:           0
StateBar_End
StateBar
     State_Name:        C6
     Line_Type:         Dashed
     Edge_Position:     50
     State_Color:       #000000
     Font_Name:         Dialog
     Font_Style:        0
     Font_Size:         12
     Signal_Type:       DigitalClock
     Signal_Name:       aclk_i
     Edge_At:           13
     OffsetX:           0
     OffsetY:           0
StateBar_End
StateBar
     State_Name:        C7
     Line_Type:         Dashed
     Edge_Position:     50
     State_Color:       #000000
     Font_Name:         Dialog
     Font_Style:        0
     Font_Size:         12
     Signal_Type:       DigitalClock
     Signal_Name:       aclk_i
     Edge_At:           15
     OffsetX:           0
     OffsetY:           0
StateBar_End
StateBar
     State_Name:        C0
     Line_Type:         Dashed
     Edge_Position:     50
     State_Color:       #000000
     Font_Name:         Dialog
     Font_Style:        0
     Font_Size:         12
     Signal_Type:       DigitalClock
     Signal_Name:       aclk_i
     Edge_At:           1
     OffsetX:           0
     OffsetY:           0
StateBar_End

Line No.	Rev	Author	Line
1	6	vladimirar	`Timing Analyzer Settings`
2			`Version: 0.991`
3			`Time_Scale: 1.0E-9`
4			`Time_Per_Division: 64`
5			`Number_Divisions: 160`
6			`Start_Time: 0`
7			`End_Time: 750`
8			`Part_Constraint`
9			`Name: thold`
10			`Min_Constraint: 4.0`
11			`Max_Constraint: 4.0`
12			`Description: Example hold constraint`
13			`Part_Constraint_End`
14			`Part_Constraint`
15			`Name: tsetup`
16			`Min_Constraint: 10.0`
17			`Max_Constraint: 10.0`
18			`Description: Example setup constraint`
19			`Part_Constraint_End`
20			`Jitter_Margin`
21			`Name: p1jitter`
22			`Plus_Margin: 1.0`
23			`Minus_Margin: 1.0`
24			`Description: Example part jitter`
25			`Jitter_Margin_End`
26			`Jitter_Margin`
27			`Name: p2jitter`
28			`Plus_Margin: 0.5`
29			`Minus_Margin: 0.5`
30			`Description: Example part jitter`
31			`Jitter_Margin_End`
32			`Digital_Clock`
33			`Position: 1`
34			`Name: aclk_i`
35			`Frequency: 1.0E7`
36			`Duty_Cycle: 50`
37			`Start_Delay: 0.0`
38			`Start_State: L`
39			`Rise_Time: 5.0`
40			`Fall_Time: 5.0`
41			`IO_Type: Input`
42			`Digital_Clock_End`
43			`Digital_Signal`
44			`Position: 2`
45			`Name: rx_tlast_i`
46			`Start_State: L`
47			`Rise_Time: 5.0`
48			`Fall_Time: 5.0`
49			`IO_Type: Input`
50			`Sync_Clock: aclk_i`
51			`Edge`
52			`Min: 556.211`
53			`Max: 556.211`
54			`State: H`
55			`Edge_End`
56			`Edge`
57			`Min: 656.211`
58			`Max: 656.211`
59			`State: L`
60			`Edge_End`
61			`Digital_Signal_End`
62			`Digital_Signal`
63			`Position: 3`
64			`Name: rx_tvalid_i`
65			`Start_State: L`
66			`Rise_Time: 5.0`
67			`Fall_Time: 5.0`
68			`IO_Type: Input`
69			`Sync_Clock: aclk_i`
70			`Edge`
71			`Min: 53.311`
72			`Max: 172.471`
73			`State: H`
74			`Edge_End`
75			`Edge`
76			`Min: 453.981`
77			`Max: 453.981`
78			`State: L`
79			`Edge_End`
80			`Edge`
81			`Min: 557.201`
82			`Max: 557.201`
83			`State: H`
84			`Edge_End`
85			`Edge`
86			`Min: 657.201`
87			`Max: 657.201`
88			`State: L`
89			`Edge_End`
90			`Digital_Signal_End`
91			`Digital_Signal`
92			`Position: 4`
93			`Name: rx_tready_o`
94			`Start_State: L`
95			`Rise_Time: 5.0`
96			`Fall_Time: 5.0`
97			`IO_Type: Output`
98			`Sync_Clock: aclk_i`
99			`Edge`
100			`Min: 98.781`
101			`Max: 98.781`
102			`State: H`
103			`Edge_End`
104			`Edge`
105			`Min: 157.201`
106			`Max: 157.201`
107			`State: L`
108			`Edge_End`
109			`Edge`
110			`Min: 257.201`
111			`Max: 257.201`
112			`State: H`
113			`Edge_End`
114			`Edge`
115			`Min: 868.401`
116			`Max: 868.401`
117			`State: L`
118			`Edge_End`
119			`Digital_Signal_End`
120			`Digital_Bus`
121			`Position: 5`
122			`Name: rx_tdate_i[7:0]`
123			`Start_State: X`
124			`State_Format: Text`
125			`Rise_Time: 5.0`
126			`Fall_Time: 5.0`
127			`IO_Type: Input`
128			`Sync_Clock: aclk_i`
129			`Edge`
130			`Min: 53.151`
131			`Max: 53.151`
132			`State: DI1`
133			`Edge_End`
134			`Edge`
135			`Min: 156.031`
136			`Max: 156.031`
137			`State: DI2`
138			`Edge_End`
139			`Edge`
140			`Min: 357.731`
141			`Max: 357.731`
142			`State: DI3`
143			`Edge_End`
144			`Edge`
145			`Min: 453.121`
146			`Max: 453.121`
147			`State: X`
148			`Edge_End`
149			`Edge`
150			`Min: 557.731`
151			`Max: 557.731`
152			`State: DI4`
153			`Edge_End`
154			`Edge`
155			`Min: 657.731`
156			`Max: 657.731`
157			`State: X`
158			`Edge_End`
159			`Edge`
160			`Min: 880.091`
161			`Max: 880.091`
162			`State: Z`
163			`Edge_End`
164			`Digital_Bus_End`
165			`Digital_Signal`
166			`Position: 6`
167			`Name: tx_tlast_o`
168			`Start_State: L`
169			`Rise_Time: 5.0`
170			`Fall_Time: 5.0`
171			`IO_Type: Output`
172			`Edge`
173			`Min: 556.211`
174			`Max: 556.211`
175			`State: H`
176			`Edge_End`
177			`Edge`
178			`Min: 656.211`
179			`Max: 656.211`
180			`State: L`
181			`Edge_End`
182			`Digital_Signal_End`
183			`Digital_Signal`
184			`Position: 7`
185			`Name: tx_tvalid_o`
186			`Start_State: L`
187			`Rise_Time: 5.0`
188			`Fall_Time: 5.0`
189			`IO_Type: Output`
190			`Edge`
191			`Min: 53.311`
192			`Max: 53.311`
193			`State: H`
194			`Edge_End`
195			`Edge`
196			`Min: 453.981`
197			`Max: 453.981`
198			`State: L`
199			`Edge_End`
200			`Edge`
201			`Min: 557.201`
202			`Max: 557.201`
203			`State: H`
204			`Edge_End`
205			`Edge`
206			`Min: 657.201`
207			`Max: 657.201`
208			`State: L`
209			`Edge_End`
210			`Digital_Signal_End`
211			`Digital_Signal`
212			`Position: 8`
213			`Name: tx_tready_i`
214			`Start_State: L`
215			`Rise_Time: 5.0`
216			`Fall_Time: 5.0`
217			`IO_Type: Input`
218			`Edge`
219			`Min: 98.781`
220			`Max: 98.781`
221			`State: H`
222			`Edge_End`
223			`Edge`
224			`Min: 157.201`
225			`Max: 157.201`
226			`State: L`
227			`Edge_End`
228			`Edge`
229			`Min: 257.201`
230			`Max: 257.201`
231			`State: H`
232			`Edge_End`
233			`Edge`
234			`Min: 868.401`
235			`Max: 868.401`
236			`State: L`
237			`Edge_End`
238			`Digital_Signal_End`
239			`Digital_Bus`
240			`Position: 9`
241			`Name: tx_tdate_o[7:0]`
242			`Start_State: X`
243			`State_Format: Text`
244			`Rise_Time: 5.0`
245			`Fall_Time: 5.0`
246			`IO_Type: Output`
247			`Edge`
248			`Min: 53.151`
249			`Max: 53.151`
250			`State: DO1`
251			`Edge_End`
252			`Edge`
253			`Min: 156.031`
254			`Max: 156.031`
255			`State: DO2`
256			`Edge_End`
257			`Edge`
258			`Min: 357.731`
259			`Max: 357.731`
260			`State: DO3`
261			`Edge_End`
262			`Edge`
263			`Min: 453.121`
264			`Max: 453.121`
265			`State: X`
266			`Edge_End`
267			`Edge`
268			`Min: 557.731`
269			`Max: 557.731`
270			`State: DO4`
271			`Edge_End`
272			`Edge`
273			`Min: 657.731`
274			`Max: 657.731`
275			`State: X`
276			`Edge_End`
277			`Edge`
278			`Min: 880.091`
279			`Max: 880.091`
280			`State: Z`
281			`Edge_End`
282			`Digital_Bus_End`
283			`StateBar`
284			`State_Name: C2`
285			`Line_Type: Dashed`
286			`Edge_Position: 50`
287			`State_Color: #000000`
288			`Font_Name: Dialog`
289			`Font_Style: 0`
290			`Font_Size: 12`
291			`Signal_Type: DigitalClock`
292			`Signal_Name: aclk_i`
293			`Edge_At: 5`
294			`OffsetX: 0`
295			`OffsetY: 0`
296			`StateBar_End`
297			`StateBar`
298			`State_Name: C3`
299			`Line_Type: Dashed`
300			`Edge_Position: 50`
301			`State_Color: #000000`
302			`Font_Name: Dialog`
303			`Font_Style: 0`
304			`Font_Size: 12`
305			`Signal_Type: DigitalClock`
306			`Signal_Name: aclk_i`
307			`Edge_At: 7`
308			`OffsetX: 0`
309			`OffsetY: 0`
310			`StateBar_End`
311			`StateBar`
312			`State_Name: C1`
313			`Line_Type: Dashed`
314			`Edge_Position: 50`
315			`State_Color: #000000`
316			`Font_Name: Dialog`
317			`Font_Style: 0`
318			`Font_Size: 12`
319			`Signal_Type: DigitalClock`
320			`Signal_Name: aclk_i`
321			`Edge_At: 3`
322			`OffsetX: 0`
323			`OffsetY: 0`
324			`StateBar_End`
325			`StateBar`
326			`State_Name: C4`
327			`Line_Type: Dashed`
328			`Edge_Position: 50`
329			`State_Color: #000000`
330			`Font_Name: Dialog`
331			`Font_Style: 0`
332			`Font_Size: 12`
333			`Signal_Type: DigitalClock`
334			`Signal_Name: aclk_i`
335			`Edge_At: 9`
336			`OffsetX: 0`
337			`OffsetY: 0`
338			`StateBar_End`
339			`StateBar`
340			`State_Name: C5`
341			`Line_Type: Dashed`
342			`Edge_Position: 50`
343			`State_Color: #000000`
344			`Font_Name: Dialog`
345			`Font_Style: 0`
346			`Font_Size: 12`
347			`Signal_Type: DigitalClock`
348			`Signal_Name: aclk_i`
349			`Edge_At: 11`
350			`OffsetX: 0`
351			`OffsetY: 0`
352			`StateBar_End`
353			`StateBar`
354			`State_Name: C6`
355			`Line_Type: Dashed`
356			`Edge_Position: 50`
357			`State_Color: #000000`
358			`Font_Name: Dialog`
359			`Font_Style: 0`
360			`Font_Size: 12`
361			`Signal_Type: DigitalClock`
362			`Signal_Name: aclk_i`
363			`Edge_At: 13`
364			`OffsetX: 0`
365			`OffsetY: 0`
366			`StateBar_End`
367			`StateBar`
368			`State_Name: C7`
369			`Line_Type: Dashed`
370			`Edge_Position: 50`
371			`State_Color: #000000`
372			`Font_Name: Dialog`
373			`Font_Style: 0`
374			`Font_Size: 12`
375			`Signal_Type: DigitalClock`
376			`Signal_Name: aclk_i`
377			`Edge_At: 15`
378			`OffsetX: 0`
379			`OffsetY: 0`
380			`StateBar_End`
381			`StateBar`
382			`State_Name: C0`
383			`Line_Type: Dashed`
384			`Edge_Position: 50`
385			`State_Color: #000000`
386			`Font_Name: Dialog`
387			`Font_Style: 0`
388			`Font_Size: 12`
389			`Signal_Type: DigitalClock`
390			`Signal_Name: aclk_i`
391			`Edge_At: 1`
392			`OffsetX: 0`
393			`OffsetY: 0`
394			`StateBar_End`

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[/] [lpffir/] [trunk/] [doc/] [src/] [axis_timing.tim] - Blame information for rev 6