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[/] [lpffir/] [trunk/] [uvm/] [tools/] [easier_uvm_gen/] [examples/] [minimal_split_txor/] [dut/] [mydut.sv] - Blame information for rev 4

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module mydut (
  input logic bus_clk,
  input bit   bus_cmd,
  input byte  bus_data,
  input byte  bus_addr
);
 
always @(posedge bus_clk)
  $display("@%4d mydut bus_cmd = %s, bus_addr = %h, bus_data = %h", $time, (bus_cmd ? "W" : "R"), bus_addr, bus_data);
 
endmodule

Line No.	Rev	Author	Line
1	4	vladimirar	`module mydut (`
2			`input logic bus_clk,`
3			`input bit bus_cmd,`
4			`input byte bus_data,`
5			`input byte bus_addr`
6			`);`
7
8			`always @(posedge bus_clk)`
9			`$display("@%4d mydut bus_cmd = %s, bus_addr = %h, bus_data = %h", $time, (bus_cmd ? "W" : "R"), bus_addr, bus_data);`
10
11			`endmodule`

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[/] [lpffir/] [trunk/] [uvm/] [tools/] [easier_uvm_gen/] [examples/] [minimal_split_txor/] [dut/] [mydut.sv] - Blame information for rev 4