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[/] [lpffir/] [trunk/] [uvm/] [tools/] [easier_uvm_gen/] [examples/] [multi_if/] [include/] [bus1_do_mon.sv] - Blame information for rev 4

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task bus1_monitor::do_mon;
  forever @(posedge vif.clk)
  begin
    m_trans = bus_tx::type_id::create("m_trans");
    m_trans.cmd  = vif.cmd;
    m_trans.addr = vif.addr;
    m_trans.data = vif.data;
    analysis_port.write(m_trans);
  end
endtask

Line No.	Rev	Author	Line
1	4	vladimirar	`task bus1_monitor::do_mon;`
2			`forever @(posedge vif.clk)`
3			`begin`
4			`m_trans = bus_tx::type_id::create("m_trans");`
5			`m_trans.cmd = vif.cmd;`
6			`m_trans.addr = vif.addr;`
7			`m_trans.data = vif.data;`
8			`analysis_port.write(m_trans);`
9			`end`
10			`endtask`

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[/] [lpffir/] [trunk/] [uvm/] [tools/] [easier_uvm_gen/] [examples/] [multi_if/] [include/] [bus1_do_mon.sv] - Blame information for rev 4