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<h1><a class="anchor" id="pGettingStarted">Getting started </a></h1><p>This software package also provides some simple examples beside the source code for the UVM scoreboard.</p>
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<p>Before starting to integrate the UVM scoreboard into your own code then it might be beneficial to look at the provided examples. An example testbench is placed in the <b>tb</b> directory and the tests are in the <b>tb/test</b> directory.</p>
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<p>To run the examples you need to select a Vendor since the examples can be run with all of the three major SystemVerilog simulator vendors: Mentor Graphics, Cadence and Synopsys. See <b>README.txt</b> for a description of how to select the vendor.</p>
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<p>Once the vendor has been selected then the available Make targets for that vendor can be listed by typing: "make". Typically, you run the simulation with: <b>make sim</b>.</p>
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<p>In general you can type: <b>make help</b> to get information about what Make options are available. </p>
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Project: SyoSil ApS UVM Scoreboard, Revision: 1.0.2.5<br>
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<br>
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Copyright 2014-2015 SyoSil ApS<br>
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