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1 4 vladimirar
//----------------------------------------------------------------------
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//   Copyright 2014-2015 SyoSil ApS
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//   All Rights Reserved Worldwide
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//
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//   Licensed under the Apache License, Version 2.0 (the
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//   "License"); you may not use this file except in
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//   compliance with the License.  You may obtain a copy of
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//   the License at
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//
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//       http://www.apache.org/licenses/LICENSE-2.0
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//
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//   Unless required by applicable law or agreed to in
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//   writing, software distributed under the License is
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//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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//   CONDITIONS OF ANY KIND, either express or implied.  See
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//   the License for the specific language governing
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//   permissions and limitations under the License.
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//----------------------------------------------------------------------
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// *NOTES*:
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// Simple OOO compare test using the TLM based API
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class cl_scbtest_par_seq_item #(int unsigned WIDTH=32) extends uvm_sequence_item;
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  //-------------------------------------
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  // Randomizable variables
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  //-------------------------------------
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  rand bit [WIDTH-1:0] a;
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  //-------------------------------------
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  // UVM Macros
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  //-------------------------------------
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  `uvm_object_utils_begin(cl_scbtest_par_seq_item)
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    `uvm_field_int(a, UVM_ALL_ON)
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  `uvm_object_utils_end
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  //-------------------------------------
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  // Constructor
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  //-------------------------------------
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  function new(string name = "cl_scbtest_par_seq_item");
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    super.new(name);
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  endfunction
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endclass: cl_scbtest_par_seq_item
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/*
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class cl_tlmpar_subscriber #(int unsigned WIDTH) extends cl_syoscb_subscriber
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  `uvm_component_param_utils(cl_tlmpar_subscriber#(WIDTH))
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  //-------------------------------------
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  // Constructor
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  //-------------------------------------
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  function new(string name = "cl_tlmpar_subscriber");
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    super.new(name);
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  endfunction
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endclass: cl_tlmpar_subscriber
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*/
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// This class implements a monitor which does a sequence of
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// writes on it's analysis port with random waits in between
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class cl_tlmpar_monitor extends uvm_monitor;
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  //-------------------------------------
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  // Non randomizable variables
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  //-------------------------------------
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  uvm_analysis_port #(cl_scbtest_par_seq_item#(.WIDTH(64))) anls_port;
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  //-------------------------------------
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  // UVM Macros
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  //-------------------------------------
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  `uvm_component_utils(cl_tlmpar_monitor)
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  //-------------------------------------
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  // Constructor
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  //-------------------------------------
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  extern function new(string name, uvm_component p = null);
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  //-------------------------------------
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  // UVM Phase methods
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  //-------------------------------------
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  extern function void build_phase(uvm_phase phase);
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  extern task run_phase(uvm_phase phase);
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endclass: cl_tlmpar_monitor
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function cl_tlmpar_monitor::new(string name, uvm_component p = null);
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  super.new(name,p);
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endfunction
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function void cl_tlmpar_monitor::build_phase(uvm_phase phase);
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  super.build_phase(phase);
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  this.anls_port = new("anls_port", this);
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endfunction: build_phase
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task cl_tlmpar_monitor::run_phase(uvm_phase phase);
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  cl_scbtest_par_seq_item#(.WIDTH(64)) a;
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  // Raise objection
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  phase.raise_objection(this);
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  super.run_phase(phase);
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  // Create UVM sequence item
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  a = new();
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  // Produce 100 writes
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  for(int i=0; i<100; i++) begin
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    int unsigned ws;
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    // Generate random wait
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    ws = $urandom_range(100, 10);
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    `uvm_info("TLMPAR_MON", $sformatf("[%0d]: Waiting %0d time units", i, ws), UVM_NONE);
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    // Do the wait
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    #(ws);
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    `uvm_info("TLMPAR_MON", $sformatf("[%0d]: Wait done", i), UVM_NONE);
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    // Use increasing values. This will work since we have an OOO compare
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    a.a[63:0] = i;
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    // Write to the analysis port. This will mimic e.g. a monitor instantiated inside a UVM agent
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    // which samples transactions and writres them to its subscribers
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    anls_port.write(a);
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  end
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  // Drop objection
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  phase.drop_objection(this);
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endtask: run_phase
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class cl_scbtest_test_tlmpar extends cl_scbtest_test_base;
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  //-------------------------------------
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  // Non randomizable variables
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  //-------------------------------------
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  cl_tlmpar_monitor monQ1P1;
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  cl_tlmpar_monitor monQ2P1;
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  //-------------------------------------
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  // UVM Macros
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  //-------------------------------------
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  `uvm_component_utils(cl_scbtest_test_tlmpar)
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  //-------------------------------------
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  // Constructor
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  //-------------------------------------
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  extern function new(string name = "cl_scbtest_test_tlmpar", uvm_component parent = null);
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  //-------------------------------------
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  // UVM Phase methods
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  //-------------------------------------
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  extern function void build_phase(uvm_phase phase);
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  extern function void connect_phase(uvm_phase phase);
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  extern task run_phase(uvm_phase phase);
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endclass : cl_scbtest_test_tlmpar
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function cl_scbtest_test_tlmpar::new(string name = "cl_scbtest_test_tlmpar", uvm_component parent = null);
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  super.new(name, parent);
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endfunction : new
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function void cl_scbtest_test_tlmpar::build_phase(uvm_phase phase);
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  super.build_phase(phase);
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  this.monQ1P1 = new("monQ1P1", this);
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  this.monQ2P1 = new("monQ2P1", this);
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endfunction: build_phase
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function void cl_scbtest_test_tlmpar::connect_phase(uvm_phase phase);
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  super.connect_phase(phase);
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  // *NOTE*: This will hook up the TLM monitors with the TLM API of the
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  //         scoreboard. Normally, this would not be done here but in the
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  //         testbench environment which would have access to all of the
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  //         montors and the scoreboard. However, these monitors only
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  //         exists for this specific test. Thus, it is done here locally.
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  begin
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    cl_syoscb_subscriber#(cl_scbtest_par_seq_item#(.WIDTH(64))) subscriber;
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    // Get the subscriber for Producer: P1 for queue: Q1 and connect it
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    // to the UVM monitor producing transactions for this queue
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    subscriber = this.scbtest_env.syoscb[0].get_subscriber("Q1", "P1");
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    $cast(subscriber, this.scbtest_env.syoscb[0].get_subscriber("Q1", "P1"));
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    this.monQ1P1.anls_port.connect(subscriber.analysis_export);
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    // Get the subscriber for Producer: P1 for queue: Q2 and connect it
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    // to the UVM monitor producing transactions for this queue
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    subscriber = this.scbtest_env.syoscb[0].get_subscriber("Q2", "P1");
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    this.monQ2P1.anls_port.connect(subscriber.analysis_export);
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  end
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endfunction: connect_phase
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task cl_scbtest_test_tlmpar::run_phase(uvm_phase phase);
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  // Raise objection
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  phase.raise_objection(this);
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  super.run_phase(phase);
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  // *NOTE*: This test is intentionally empty since
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  //         All of the stimuli is coming from the TLM monitors
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  // Drop objection
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  phase.drop_objection(this);
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endtask: run_phase

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