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URL https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk

Subversion Repositories lq057q3dc02

[/] [lq057q3dc02/] [trunk/] [coregen/] [coregen.cgp] - Blame information for rev 48

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Line No. Rev Author Line
1 28 jwdonal 
# Date: Thu Nov 06 22:53:43 2008
2 
SET addpads = False
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc2vp30
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SET devicefamily = virtex2p
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SET flowvendor = Foundation_iSE
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ff896
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SET removerpms = False
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SET simulationfiles = Structural
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SET speedgrade = -7
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SET verilogsim = False
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SET vhdlsim = True
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SET workingdirectory = D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp
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