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jwdonal |
##############################################################################
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# Copyright (C) 2007 Jonathon W. Donaldson
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# jwdonal a t opencores DOT org
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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#
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##############################################################################
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#
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jwdonal |
# $Id: lq057q3dc02.tcl,v 1.2 2008-11-07 05:38:36 jwdonal Exp $
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jwdonal |
#
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# Description:
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jwdonal |
# Tcl script to run in the Xilinx Tcl shell or the ISE Tcl Console. This
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# method is DEPRECATED. Simply use the batch scripts found in the
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# 'implement' directory for project management. The GUI is nothing but
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# a memory hog - real men use scripts and plain text editors!!!
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jwdonal |
#
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# Structure:
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# - xupv2p.ucf
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# - components.vhd
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# - lq057q3dc02_tb.vhd
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# - lq057q3dc02.vhd
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# - dcm_sys_to_lcd.xaw
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# - video_controller.vhd
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# - enab_control.vhd
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# - hsyncx_control.vhd
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# - vsyncx_control.vhd
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# - clk_lcd_cyc_cntr.vhd
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# - image_gen_bram.vhd
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# - image_gen_bram_red.xco
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# - image_gen_bram_green.xco
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# - image_gen_bram_blue.xco
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#
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##############################################################################
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# To run this script, `cd' to the directory containg this file
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# using the Tcl shell/console. Type "source <filename>" at Tcl prompt.
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# This script is compatible with ISE 9.1.03i
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#Go to project directory
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cd ../ise_files
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# set up the project
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project new lq057q3dc02.ise
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project set family Virtex2P
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project set device XC2VP30
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project set package FF896
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project set speed -7
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project set synthesis_tool "XST (VHDL/Verilog)"
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project set generated_simulation_language "ModelSim-SE Mixed"
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# Go back to user source directory
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cd ../src
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# Add source files
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xfile add *.vhd *.ucf *.xco *.xaw
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# Set Generate Programming File properties
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project set "Unused IOB Pins" "Pull Up"
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project set "FPGA Start-Up Clock" "JTAG Clock"
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project set "Done (Output Events)" 6
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project set "Enable Outputs (Output Events)" 3
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project set "Release Write Enable (Output Events)" 5
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project set "Release DLL (Output Events)" 4
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