My Tcl file will set up most of the required project options (provided below) for you! Check it out!
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DCM must have "Wait for DCM lock before signal goes high" option set!
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ISE "Generate Programming File" Properties must be set to the following sequence of states:
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3 = GTS (enable outputs)
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4 = Release DLL (lock signal)
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5 = GSR (release write enable)
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6 = Done
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The image_gen_bram_files folder contains the source code that was generated by the CoreGen tool for the XCO files located there. Because a full screen image can take several minutes to generate I thought it reason enough to include pre-built source for at least one full screen image. I may add more in the future.
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In order for these pre-built files to work the project directory structure must be setup as follows:
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|
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|--> "ise_files"
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|--> "src"
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"ise_files" is the ISE project directory
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"src" is where all the source code will be stored
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Copy the pre-built files to the "ise_files" project directory and add the XCO files to your project.
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You can also just edit the XCO files yourself (they are just plain text files) and change the directory names as you see fit. :-)
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Note that if you do not create the directory structure as shown above the project will not simulate properly. More specifically the R,G,B outputs will not toggle as expected (i.e. they will show all 'U's) due to the fact that the XCO files (and all source files that Xilinx generates from them) store the original source file search path inside the XCO file). If you change the source/project directory name you have to regenerate all of the XCO source files manually.
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Remember, you don't need the coefficient (COE) files even though the XCO files reference them. The COE files have already been parsed and the HDL has already been built. It's just Plug and Play - Enjoy!
