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Release 9.2.04i Map J.40
Xilinx Map Application Log File for Design 'lq057q3dc02_top'
 
Design Information
------------------
Command Line   : map -ol high -timing -pr b lq057q3dc02_top.ngd -o
lq057q3dc02_top.ncd lq057q3dc02_top.pcf
Target Device  : xc2vp30
Target Package : ff896
Target Speed   : -7
Mapper Version : virtex2p -- $Revision: 1.3 $
Mapped Date    : Sun Nov 09 22:13:35 2008
 
Mapping design into LUTs...
Writing file lq057q3dc02_top.ngm...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...
 
Phase 1.1
Phase 1.1 (Checksum:98a19b) REAL time: 3 secs
 
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 3 secs
 
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 3 secs
 
Phase 4.2
.
Phase 4.2 (Checksum:26259fc) REAL time: 4 secs
 
Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 4 secs
 
Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 4 secs
 
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 4 secs
 
Phase 8.4
.........
Phase 8.4 (Checksum:4c4b3f8) REAL time: 9 secs
 
Phase 9.28
Phase 9.28 (Checksum:55d4a77) REAL time: 9 secs
 
Phase 10.8
.........
.
...............
...............
...............
...............
Phase 10.8 (Checksum:caed37) REAL time: 11 secs
 
Phase 11.29
Phase 11.29 (Checksum:68e7775) REAL time: 11 secs
 
Phase 12.5
Phase 12.5 (Checksum:7270df4) REAL time: 11 secs
 
Phase 13.18
Phase 13.18 (Checksum:7bfa473) REAL time: 13 secs
 
Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 13 secs
 
Phase 15.27
Phase 15.27 (Checksum:8f0d171) REAL time: 13 secs
 
Phase 16.24
Phase 16.24 (Checksum:98967f0) REAL time: 13 secs
 
REAL time consumed by placer: 13 secs
CPU  time consumed by placer: 12 secs
Inspecting route info ...
Route info done.
 
Design Summary
--------------
 
Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:          66 out of  27,392    1%
  Number of 4 input LUTs:             189 out of  27,392    1%
Logic Distribution:
  Number of occupied Slices:          127 out of  13,696    1%
Total Number of 4 input LUTs:            197 out of  27,392    1%
  Number used as logic:               189
  Number used as a route-thru:          8
 
  Number of bonded IOBs:               27 out of     556    4%
    IOB Flip Flops:                     1
  Number of PPC405s:                   0 out of       2    0%
  Number of Block RAMs:                87 out of     136   63%
  Number of GCLKs:                      2 out of      16   12%
  Number of DCMs:                       1 out of       8   12%
  Number of GTs:                        0 out of       8    0%
  Number of GT10s:                      0 out of       0    0%
 
Total equivalent gate count for design:  5,710,614
Additional JTAG gate count for IOBs:  1,296
Peak Memory Usage:  228 MB
Total REAL time to MAP completion:  24 secs
Total CPU time to MAP completion:   20 secs
 
Mapping completed.
See MAP report file "lq057q3dc02_top.mrp" for details.

Line No.	Rev	Author	Line
1	32	jwdonal	`Release 9.2.04i Map J.40`
2			`Xilinx Map Application Log File for Design 'lq057q3dc02_top'`
3
4			`Design Information`
5			`------------------`
6			`Command Line : map -ol high -timing -pr b lq057q3dc02_top.ngd -o`
7			`lq057q3dc02_top.ncd lq057q3dc02_top.pcf`
8			`Target Device : xc2vp30`
9			`Target Package : ff896`
10			`Target Speed : -7`
11	46	jwdonal	`Mapper Version : virtex2p -- $Revision: 1.3 $`
12			`Mapped Date : Sun Nov 09 22:13:35 2008`
13	32	jwdonal
14			`Mapping design into LUTs...`
15			`Writing file lq057q3dc02_top.ngm...`
16			`Running directed packing...`
17			`Running delay-based LUT packing...`
18			`Running timing-driven packing...`
19
20			`Phase 1.1`
21	38	jwdonal	`Phase 1.1 (Checksum:98a19b) REAL time: 3 secs`
22	32	jwdonal
23			`Phase 2.7`
24	38	jwdonal	`Phase 2.7 (Checksum:1312cfe) REAL time: 3 secs`
25	32	jwdonal
26			`Phase 3.31`
27	38	jwdonal	`Phase 3.31 (Checksum:1c9c37d) REAL time: 3 secs`
28	32	jwdonal
29			`Phase 4.2`
30			`.`
31	46	jwdonal	`Phase 4.2 (Checksum:26259fc) REAL time: 4 secs`
32	32	jwdonal
33			`Phase 5.30`
34	46	jwdonal	`Phase 5.30 (Checksum:2faf07b) REAL time: 4 secs`
35	32	jwdonal
36			`Phase 6.3`
37	38	jwdonal	`Phase 6.3 (Checksum:39386fa) REAL time: 4 secs`
38	32	jwdonal
39			`Phase 7.5`
40	38	jwdonal	`Phase 7.5 (Checksum:42c1d79) REAL time: 4 secs`
41	32	jwdonal
42			`Phase 8.4`
43	38	jwdonal	`.........`
44			`Phase 8.4 (Checksum:4c4b3f8) REAL time: 9 secs`
45	32	jwdonal
46			`Phase 9.28`
47	38	jwdonal	`Phase 9.28 (Checksum:55d4a77) REAL time: 9 secs`
48	32	jwdonal
49			`Phase 10.8`
50	38	jwdonal	`.........`
51			`.`
52	32	jwdonal	`...............`
53			`...............`
54			`...............`
55	38	jwdonal	`...............`
56			`Phase 10.8 (Checksum:caed37) REAL time: 11 secs`
57	32	jwdonal
58			`Phase 11.29`
59			`Phase 11.29 (Checksum:68e7775) REAL time: 11 secs`
60
61			`Phase 12.5`
62			`Phase 12.5 (Checksum:7270df4) REAL time: 11 secs`
63
64			`Phase 13.18`
65			`Phase 13.18 (Checksum:7bfa473) REAL time: 13 secs`
66
67			`Phase 14.5`
68			`Phase 14.5 (Checksum:8583af2) REAL time: 13 secs`
69
70			`Phase 15.27`
71			`Phase 15.27 (Checksum:8f0d171) REAL time: 13 secs`
72
73			`Phase 16.24`
74			`Phase 16.24 (Checksum:98967f0) REAL time: 13 secs`
75
76	38	jwdonal	`REAL time consumed by placer: 13 secs`
77			`CPU time consumed by placer: 12 secs`
78	32	jwdonal	`Inspecting route info ...`
79			`Route info done.`
80
81			`Design Summary`
82			`--------------`
83
84			`Design Summary:`
85			`Number of errors: 0`
86			`Number of warnings: 2`
87			`Logic Utilization:`
88	38	jwdonal	`Number of Slice Flip Flops: 66 out of 27,392 1%`
89			`Number of 4 input LUTs: 189 out of 27,392 1%`
90	32	jwdonal	`Logic Distribution:`
91	38	jwdonal	`Number of occupied Slices: 127 out of 13,696 1%`
92			`Total Number of 4 input LUTs: 197 out of 27,392 1%`
93			`Number used as logic: 189`
94			`Number used as a route-thru: 8`
95	32	jwdonal
96			`Number of bonded IOBs: 27 out of 556 4%`
97			`IOB Flip Flops: 1`
98			`Number of PPC405s: 0 out of 2 0%`
99			`Number of Block RAMs: 87 out of 136 63%`
100			`Number of GCLKs: 2 out of 16 12%`
101			`Number of DCMs: 1 out of 8 12%`
102			`Number of GTs: 0 out of 8 0%`
103			`Number of GT10s: 0 out of 0 0%`
104
105	38	jwdonal	`Total equivalent gate count for design: 5,710,614`
106	32	jwdonal	`Additional JTAG gate count for IOBs: 1,296`
107	38	jwdonal	`Peak Memory Usage: 228 MB`
108			`Total REAL time to MAP completion: 24 secs`
109	46	jwdonal	`Total CPU time to MAP completion: 20 secs`
110	32	jwdonal
111			`Mapping completed.`
112			`See MAP report file "lq057q3dc02_top.mrp" for details.`

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[/] [lq057q3dc02/] [trunk/] [implement/] [results/] [lq057q3dc02_top.map] - Blame information for rev 47