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Release 9.2.04i Map J.40
Xilinx Mapping Report File for Design 'lq057q3dc02_top'
 
Design Information
------------------
Command Line   : map -ol high -timing -pr b lq057q3dc02_top.ngd -o
lq057q3dc02_top.ncd lq057q3dc02_top.pcf
Target Device  : xc2vp30
Target Package : ff896
Target Speed   : -7
Mapper Version : virtex2p -- $Revision: 1.3 $
Mapped Date    : Sun Nov 09 22:13:35 2008
 
Design Summary
--------------
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:          66 out of  27,392    1%
  Number of 4 input LUTs:             189 out of  27,392    1%
Logic Distribution:
  Number of occupied Slices:          127 out of  13,696    1%
Total Number of 4 input LUTs:            197 out of  27,392    1%
  Number used as logic:               189
  Number used as a route-thru:          8
 
  Number of bonded IOBs:               27 out of     556    4%
    IOB Flip Flops:                     1
  Number of PPC405s:                   0 out of       2    0%
  Number of Block RAMs:                87 out of     136   63%
  Number of GCLKs:                      2 out of      16   12%
  Number of DCMs:                       1 out of       8   12%
  Number of GTs:                        0 out of       8    0%
  Number of GT10s:                      0 out of       0    0%
 
Total equivalent gate count for design:  5,710,614
Additional JTAG gate count for IOBs:  1,296
Peak Memory Usage:  228 MB
Total REAL time to MAP completion:  24 secs
Total CPU time to MAP completion:   20 secs
 
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
 
Section 1 - Errors
------------------
 
Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network N1 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 8
   more times for the following (max. 5 shown):
   N2,
   DCM_LCD_CLK/CLKFX_OUT,
   DCM_LCD_CLK/N0,
   IMAGE/N136,
   V_C/VSYNCx_C/N42
   To see the details of these warning messages, please use the -detail switch.
 
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "DCM_LCD_CLK/CLK0_BUFG_INST" (output
   signal=DCM_LCD_CLK/CLK0_OUT),
   BUFG symbol "DCM_LCD_CLK/CLKDV_BUFG_INST" (output signal=CLK_LCD_OBUF),
   BUFG symbol "DCM_LCD_CLK/CLKFX_BUFG_INST" (output
   signal=DCM_LCD_CLK/CLKFX_OUT)
INFO:MapLib:159 - Net Timing constraints on signal CLK_100M_PAD are pushed
   forward through input buffer.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   -40.000 to 100.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.400 Volts. (default - Range: 1.400 to
   1.600 Volts)
INFO:Pack:1650 - Map created a placed design.
 
Section 4 - Removed Logic Summary
---------------------------------
  15 block(s) removed
  14 block(s) optimized away
  10 signal(s) removed
 
Section 5 - Removed Logic
-------------------------
 
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.
 
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
 
The signal "N1" is loadless and has been removed.
 Loadless block "XST_GND" (ZERO) removed.
The signal "N2" is loadless and has been removed.
 Loadless block "XST_VCC" (ONE) removed.
The signal "DCM_LCD_CLK/CLKFX_OUT" is sourceless and has been removed.
The signal "DCM_LCD_CLK/CLKFX_BUF" is sourceless and has been removed.
 Sourceless block "DCM_LCD_CLK/CLKFX_BUFG_INST" (CKBUF) removed.
The signal "DCM_LCD_CLK/N0" is sourceless and has been removed.
The signal "IMAGE/N136" is sourceless and has been removed.
The signal "V_C/VSYNCx_C/N42" is sourceless and has been removed.
The signal "V_C/CLK_LCD_CYCLE_Cntr/N119" is sourceless and has been removed.
The signal "V_C/ENAB_C/N65" is sourceless and has been removed.
The signal "V_C/ENAB_C/N66" is sourceless and has been removed.
Unused block "DCM_LCD_CLK/XST_VCC" (ONE) removed.
Unused block "IMAGE/XST_VCC" (ONE) removed.
Unused block "IMAGE/image_BLUE_data/GND" (ZERO) removed.
Unused block "IMAGE/image_BLUE_data/VCC" (ONE) removed.
Unused block "IMAGE/image_GREEN_data/GND" (ZERO) removed.
Unused block "IMAGE/image_GREEN_data/VCC" (ONE) removed.
Unused block "IMAGE/image_RED_data/GND" (ZERO) removed.
Unused block "IMAGE/image_RED_data/VCC" (ONE) removed.
Unused block "V_C/CLK_LCD_CYCLE_Cntr/XST_VCC" (ONE) removed.
Unused block "V_C/ENAB_C/XST_GND" (ZERO) removed.
Unused block "V_C/ENAB_C/XST_VCC" (ONE) removed.
Unused block "V_C/VSYNCx_C/XST_VCC" (ONE) removed.
 
Optimized Block(s):
TYPE            BLOCK
GND             DCM_LCD_CLK/XST_GND
GND             IMAGE/XST_GND
GND             IMAGE/image_BLUE_data/BU2/XST_GND
VCC             IMAGE/image_BLUE_data/BU2/XST_VCC
GND             IMAGE/image_GREEN_data/BU2/XST_GND
VCC             IMAGE/image_GREEN_data/BU2/XST_VCC
GND             IMAGE/image_RED_data/BU2/XST_GND
VCC             IMAGE/image_RED_data/BU2/XST_VCC
GND             V_C/CLK_LCD_CYCLE_Cntr/XST_GND
GND             V_C/HSYNCx_C/XST_GND
VCC             V_C/HSYNCx_C/XST_VCC
GND             V_C/VSYNCx_C/XST_GND
GND             V_C/XST_GND
VCC             V_C/XST_VCC
 
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
 
Section 6 - IOB Properties
--------------------------
 
+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| B<0>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| B<1>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| B<2>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| B<3>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| B<4>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| B<5>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| CLK_100M_PAD                       | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| CLK_LCD                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| ENAB                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| G<0>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| G<1>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| G<2>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| G<3>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| G<4>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| G<5>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| HSYNCx                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| R<0>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| R<1>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| R<2>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| R<3>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| R<4>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| R<5>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| RL                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| RSTx                               | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| UD                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| VQ                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| VSYNCx                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+
 
Section 7 - RPMs
----------------
 
Section 8 - Guide Report
------------------------
Guide not run on this design.
 
Section 9 - Area Group and Partition Summary
--------------------------------------------
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
Area Group Information
----------------------
 
  No area groups were found in this design.
 
----------------------
 
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
 
Section 11 - Timing Report
--------------------------
INFO:Timing:3284 - This timing report was generated using estimated delay
   information.  For accurate numbers, please refer to the post Place and Route
   timing report.
Number of Timing Constraints that were not applied: 2
 
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.
 
------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing
                                            |         |    Slack   | Achievable | Errors |    Score
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP   |   154.254ns|     5.746ns|       0|           0
  V_BUF" derived from  NET "DCM_LCD_CLK/CLK | HOLD    |     0.608ns|            |       0|           0
  IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%  mu |         |            |            |        |
  ltiplied by 16.00 and duty cycle correcte |         |            |            |        |
  d to 160 nS  HIGH 80 nS                   |         |            |            |        |
------------------------------------------------------------------------------------------------------
  NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD  | N/A     |         N/A|         N/A|     N/A|         N/A
  = 10 ns HIGH 50%                          |         |            |            |        |
------------------------------------------------------------------------------------------------------
  NET "CLK_LCD" PERIOD = 160 ns HIGH 50%    | N/A     |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
 
 
 
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
 
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.

Line No.	Rev	Author	Line
1	32	jwdonal	`Release 9.2.04i Map J.40`
2			`Xilinx Mapping Report File for Design 'lq057q3dc02_top'`
3
4			`Design Information`
5			`------------------`
6			`Command Line : map -ol high -timing -pr b lq057q3dc02_top.ngd -o`
7			`lq057q3dc02_top.ncd lq057q3dc02_top.pcf`
8			`Target Device : xc2vp30`
9			`Target Package : ff896`
10			`Target Speed : -7`
11	46	jwdonal	`Mapper Version : virtex2p -- $Revision: 1.3 $`
12			`Mapped Date : Sun Nov 09 22:13:35 2008`
13	32	jwdonal
14			`Design Summary`
15			`--------------`
16			`Number of errors: 0`
17			`Number of warnings: 2`
18			`Logic Utilization:`
19	38	jwdonal	`Number of Slice Flip Flops: 66 out of 27,392 1%`
20			`Number of 4 input LUTs: 189 out of 27,392 1%`
21	32	jwdonal	`Logic Distribution:`
22	38	jwdonal	`Number of occupied Slices: 127 out of 13,696 1%`
23			`Total Number of 4 input LUTs: 197 out of 27,392 1%`
24			`Number used as logic: 189`
25			`Number used as a route-thru: 8`
26	32	jwdonal
27			`Number of bonded IOBs: 27 out of 556 4%`
28			`IOB Flip Flops: 1`
29			`Number of PPC405s: 0 out of 2 0%`
30			`Number of Block RAMs: 87 out of 136 63%`
31			`Number of GCLKs: 2 out of 16 12%`
32			`Number of DCMs: 1 out of 8 12%`
33			`Number of GTs: 0 out of 8 0%`
34			`Number of GT10s: 0 out of 0 0%`
35
36	38	jwdonal	`Total equivalent gate count for design: 5,710,614`
37	32	jwdonal	`Additional JTAG gate count for IOBs: 1,296`
38	38	jwdonal	`Peak Memory Usage: 228 MB`
39			`Total REAL time to MAP completion: 24 secs`
40	46	jwdonal	`Total CPU time to MAP completion: 20 secs`
41	32	jwdonal
42			`Table of Contents`
43			`-----------------`
44			`Section 1 - Errors`
45			`Section 2 - Warnings`
46			`Section 3 - Informational`
47			`Section 4 - Removed Logic Summary`
48			`Section 5 - Removed Logic`
49			`Section 6 - IOB Properties`
50			`Section 7 - RPMs`
51			`Section 8 - Guide Report`
52			`Section 9 - Area Group and Partition Summary`
53			`Section 10 - Modular Design Summary`
54			`Section 11 - Timing Report`
55			`Section 12 - Configuration String Information`
56			`Section 13 - Control Set Information`
57
58			`Section 1 - Errors`
59			`------------------`
60
61			`Section 2 - Warnings`
62			`--------------------`
63			`WARNING:LIT:243 - Logical network N1 has no load.`
64			`WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 8`
65			`more times for the following (max. 5 shown):`
66			`N2,`
67			`DCM_LCD_CLK/CLKFX_OUT,`
68			`DCM_LCD_CLK/N0,`
69	38	jwdonal	`IMAGE/N136,`
70	32	jwdonal	`V_C/VSYNCx_C/N42`
71			`To see the details of these warning messages, please use the -detail switch.`
72
73			`Section 3 - Informational`
74			`-------------------------`
75			`INFO:MapLib:562 - No environment variables are currently set.`
76			`INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to`
77			`Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:`
78			`BUFG symbol "DCM_LCD_CLK/CLK0_BUFG_INST" (output`
79			`signal=DCM_LCD_CLK/CLK0_OUT),`
80			`BUFG symbol "DCM_LCD_CLK/CLKDV_BUFG_INST" (output signal=CLK_LCD_OBUF),`
81			`BUFG symbol "DCM_LCD_CLK/CLKFX_BUFG_INST" (output`
82			`signal=DCM_LCD_CLK/CLKFX_OUT)`
83			`INFO:MapLib:159 - Net Timing constraints on signal CLK_100M_PAD are pushed`
84			`forward through input buffer.`
85			`INFO:LIT:244 - All of the single ended outputs in this design are using slew`
86			`rate limited output drivers. The delay on speed critical single ended outputs`
87			`can be dramatically reduced by designating them as fast outputs in the`
88			`schematic.`
89			`INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:`
90			`-40.000 to 100.000 Celsius)`
91			`INFO:Pack:1720 - Initializing voltage to 1.400 Volts. (default - Range: 1.400 to`
92			`1.600 Volts)`
93			`INFO:Pack:1650 - Map created a placed design.`
94
95			`Section 4 - Removed Logic Summary`
96			`---------------------------------`
97	38	jwdonal	`15 block(s) removed`
98	32	jwdonal	`14 block(s) optimized away`
99			`10 signal(s) removed`
100
101			`Section 5 - Removed Logic`
102			`-------------------------`
103
104			`The trimmed logic report below shows the logic removed from your design due to`
105			`sourceless or loadless signals, and VCC or ground connections. If the removal`
106			`of a signal or symbol results in the subsequent removal of an additional signal`
107			`or symbol, the message explaining that second removal will be indented. This`
108			`indentation will be repeated as a chain of related logic is removed.`
109
110			`To quickly locate the original cause for the removal of a chain of logic, look`
111			`above the place where that logic is listed in the trimming report, then locate`
112			`the lines that are least indented (begin at the leftmost edge).`
113
114			`The signal "N1" is loadless and has been removed.`
115			`Loadless block "XST_GND" (ZERO) removed.`
116			`The signal "N2" is loadless and has been removed.`
117			`Loadless block "XST_VCC" (ONE) removed.`
118			`The signal "DCM_LCD_CLK/CLKFX_OUT" is sourceless and has been removed.`
119			`The signal "DCM_LCD_CLK/CLKFX_BUF" is sourceless and has been removed.`
120			`Sourceless block "DCM_LCD_CLK/CLKFX_BUFG_INST" (CKBUF) removed.`
121			`The signal "DCM_LCD_CLK/N0" is sourceless and has been removed.`
122	38	jwdonal	`The signal "IMAGE/N136" is sourceless and has been removed.`
123	32	jwdonal	`The signal "V_C/VSYNCx_C/N42" is sourceless and has been removed.`
124			`The signal "V_C/CLK_LCD_CYCLE_Cntr/N119" is sourceless and has been removed.`
125			`The signal "V_C/ENAB_C/N65" is sourceless and has been removed.`
126			`The signal "V_C/ENAB_C/N66" is sourceless and has been removed.`
127			`Unused block "DCM_LCD_CLK/XST_VCC" (ONE) removed.`
128			`Unused block "IMAGE/XST_VCC" (ONE) removed.`
129	38	jwdonal	`Unused block "IMAGE/image_BLUE_data/GND" (ZERO) removed.`
130			`Unused block "IMAGE/image_BLUE_data/VCC" (ONE) removed.`
131			`Unused block "IMAGE/image_GREEN_data/GND" (ZERO) removed.`
132			`Unused block "IMAGE/image_GREEN_data/VCC" (ONE) removed.`
133			`Unused block "IMAGE/image_RED_data/GND" (ZERO) removed.`
134			`Unused block "IMAGE/image_RED_data/VCC" (ONE) removed.`
135	32	jwdonal	`Unused block "V_C/CLK_LCD_CYCLE_Cntr/XST_VCC" (ONE) removed.`
136			`Unused block "V_C/ENAB_C/XST_GND" (ZERO) removed.`
137			`Unused block "V_C/ENAB_C/XST_VCC" (ONE) removed.`
138			`Unused block "V_C/VSYNCx_C/XST_VCC" (ONE) removed.`
139
140			`Optimized Block(s):`
141			`TYPE BLOCK`
142			`GND DCM_LCD_CLK/XST_GND`
143			`GND IMAGE/XST_GND`
144	38	jwdonal	`GND IMAGE/image_BLUE_data/BU2/XST_GND`
145			`VCC IMAGE/image_BLUE_data/BU2/XST_VCC`
146			`GND IMAGE/image_GREEN_data/BU2/XST_GND`
147			`VCC IMAGE/image_GREEN_data/BU2/XST_VCC`
148			`GND IMAGE/image_RED_data/BU2/XST_GND`
149			`VCC IMAGE/image_RED_data/BU2/XST_VCC`
150	32	jwdonal	`GND V_C/CLK_LCD_CYCLE_Cntr/XST_GND`
151			`GND V_C/HSYNCx_C/XST_GND`
152			`VCC V_C/HSYNCx_C/XST_VCC`
153			`GND V_C/VSYNCx_C/XST_GND`
154			`GND V_C/XST_GND`
155			`VCC V_C/XST_VCC`
156
157			`To enable printing of redundant blocks removed and signals merged, set the`
158			`detailed map report option and rerun map.`
159
160			`Section 6 - IOB Properties`
161			`--------------------------`
162
163			`+------------------------------------------------------------------------------------------------------------------------+`
164			`\| IOB Name \| Type \| Direction \| IO Standard \| Drive \| Slew \| Reg (s) \| Resistor \| IOB \|`
165			`\| \| \| \| \| Strength \| Rate \| \| \| Delay \|`
166			`+------------------------------------------------------------------------------------------------------------------------+`
167			`\| B<0> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
168			`\| B<1> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
169			`\| B<2> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
170			`\| B<3> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
171			`\| B<4> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
172			`\| B<5> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
173			`\| CLK_100M_PAD \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \|`
174			`\| CLK_LCD \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
175			`\| ENAB \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| OFF1 \| \| \|`
176			`\| G<0> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
177			`\| G<1> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
178			`\| G<2> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
179			`\| G<3> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
180			`\| G<4> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
181			`\| G<5> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
182			`\| HSYNCx \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
183			`\| R<0> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
184			`\| R<1> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
185			`\| R<2> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
186			`\| R<3> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
187			`\| R<4> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
188			`\| R<5> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
189			`\| RL \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
190			`\| RSTx \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \|`
191			`\| UD \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
192			`\| VQ \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
193			`\| VSYNCx \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
194			`+------------------------------------------------------------------------------------------------------------------------+`
195
196			`Section 7 - RPMs`
197			`----------------`
198
199			`Section 8 - Guide Report`
200			`------------------------`
201			`Guide not run on this design.`
202
203			`Section 9 - Area Group and Partition Summary`
204			`--------------------------------------------`
205
206			`Partition Implementation Status`
207			`-------------------------------`
208
209			`No Partitions were found in this design.`
210
211			`-------------------------------`
212
213			`Area Group Information`
214			`----------------------`
215
216			`No area groups were found in this design.`
217
218			`----------------------`
219
220			`Section 10 - Modular Design Summary`
221			`-----------------------------------`
222			`Modular Design not used for this design.`
223
224			`Section 11 - Timing Report`
225			`--------------------------`
226			`INFO:Timing:3284 - This timing report was generated using estimated delay`
227			`information. For accurate numbers, please refer to the post Place and Route`
228			`timing report.`
229			`Number of Timing Constraints that were not applied: 2`
230
231			`Asterisk (*) preceding a constraint indicates it was not met.`
232			`This may be due to a setup or hold violation.`
233
234			`------------------------------------------------------------------------------------------------------`
235			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
236			`\| \| Slack \| Achievable \| Errors \| Score`
237			`------------------------------------------------------------------------------------------------------`
238	38	jwdonal	`PERIOD analysis for net "DCM_LCD_CLK/CLKD \| SETUP \| 154.254ns\| 5.746ns\| 0\| 0`
239			`V_BUF" derived from NET "DCM_LCD_CLK/CLK \| HOLD \| 0.608ns\| \| 0\| 0`
240	32	jwdonal	`IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50% mu \| \| \| \| \|`
241			`ltiplied by 16.00 and duty cycle correcte \| \| \| \| \|`
242			`d to 160 nS HIGH 80 nS \| \| \| \| \|`
243			`------------------------------------------------------------------------------------------------------`
244			`NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD \| N/A \| N/A\| N/A\| N/A\| N/A`
245			`= 10 ns HIGH 50% \| \| \| \| \|`
246			`------------------------------------------------------------------------------------------------------`
247			`NET "CLK_LCD" PERIOD = 160 ns HIGH 50% \| N/A \| N/A\| N/A\| N/A\| N/A`
248			`------------------------------------------------------------------------------------------------------`
249
250
251			`All constraints were met.`
252			`INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the`
253			`constraint does not cover any paths or that it has no requested value.`
254
255
256
257			`Section 12 - Configuration String Details`
258			`-----------------------------------------`
259			`Use the "-detail" map option to print out Configuration Strings`
260
261			`Section 13 - Control Set Information`
262			`------------------------------------`
263			`No control set information for this architecture.`

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