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Release 9.2.04i - netgen J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
 
Command Line: netgen -ofmt vhdl -w lq057q3dc02_top.ngc
 
Reading design 'lq057q3dc02_top.ngc' ...
Flattening design ...
Processing design ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist 'lq057q3dc02_top.vhd' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM library for correct
   compilation and simulation.
Number of warnings: 0
Number of info messages: 1
Total memory usage is 56472 kilobytes

Line No.	Rev	Author	Line
1	32	jwdonal	`Release 9.2.04i - netgen J.40`
2			`Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.`
3
4			`Command Line: netgen -ofmt vhdl -w lq057q3dc02_top.ngc`
5
6			`Reading design 'lq057q3dc02_top.ngc' ...`
7			`Flattening design ...`
8			`Processing design ...`
9			`Preping design's networks ...`
10			`Preping design's macros ...`
11			`Writing VHDL netlist 'lq057q3dc02_top.vhd' ...`
12			`INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM`
13			`simulation primitives and has to be used with UNISIM library for correct`
14			`compilation and simulation.`
15			`Number of warnings: 0`
16			`Number of info messages: 1`
17			`Total memory usage is 56472 kilobytes`

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[/] [lq057q3dc02/] [trunk/] [implement/] [results/] [lq057q3dc02_top.nlf] - Blame information for rev 47