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Release 9.2.04i par J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
 
NAUTILUS::  Sun Nov 09 22:14:10 2008
 
par -ol high -w lq057q3dc02_top.ncd lq057q3dc02_top.ncd lq057q3dc02_top.pcf
 
 
Constraints file: lq057q3dc02_top.pcf.
Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx\ISE_9_2.
   "lq057q3dc02_top" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
 
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.400 Volts. (default - Range: 1.400 to 1.600 Volts)
 
 
Device speed data version:  "PRODUCTION 1.94 2007-10-19".
 
 
INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.
 
Device Utilization Summary:
 
   Number of BUFGMUXs                        2 out of 16     12%
   Number of DCMs                            1 out of 8      12%
   Number of External IOBs                  27 out of 556     4%
      Number of LOCed IOBs                  27 out of 27    100%
 
   Number of RAMB16s                        87 out of 136    63%
   Number of SLICEs                        127 out of 13696   1%
 
 
Overall effort level (-ol):   High
Router effort level (-rl):    High
 
Starting initial Timing Analysis.  REAL time: 9 secs
Finished initial Timing Analysis.  REAL time: 9 secs
 
Starting Router
 
Phase 1: 4052 unrouted;       REAL time: 20 secs
 
Phase 2: 3381 unrouted;       REAL time: 21 secs
 
Phase 3: 340 unrouted;       REAL time: 25 secs
 
Phase 4: 340 unrouted; (0)      REAL time: 25 secs
 
Phase 5: 340 unrouted; (0)      REAL time: 25 secs
 
Phase 6: 340 unrouted; (0)      REAL time: 25 secs
 
Phase 7: 0 unrouted; (0)      REAL time: 26 secs
 
Phase 8: 0 unrouted; (0)      REAL time: 27 secs
 
WARNING:Route:455 - CLK Net:CLK_LCD_OBUF may have excessive skew because
 
 
Total REAL time to Router completion: 27 secs
Total CPU time to Router completion: 27 secs
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|        CLK_LCD_OBUF |     BUFGMUX6P| No   |  135 |  0.261     |  1.238      |
+---------------------+--------------+------+------+------------+-------------+
 
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
 
 
   The Delay Summary Report
 
 
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
 
   The AVERAGE CONNECTION DELAY for this design is:        2.320
   The MAXIMUM PIN DELAY IS:                               8.568
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   7.164
 
   Listing Pin Delays by value: (nsec)
 
    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 9.00  d >= 9.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1084         783         326          65           4           0
 
Timing Score: 0
 
Number of Timing Constraints that were not applied: 2
 
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.
 
------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing
                                            |         |    Slack   | Achievable | Errors |    Score
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP   |   150.792ns|     9.208ns|       0|           0
  V_BUF" derived from  NET "DCM_LCD_CLK/CLK | HOLD    |     0.609ns|            |       0|           0
  IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%     |         |            |            |        |
------------------------------------------------------------------------------------------------------
  NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD  | N/A     |         N/A|         N/A|     N/A|         N/A
  = 10 ns HIGH 50%                          |         |            |            |        |
------------------------------------------------------------------------------------------------------
  NET "CLK_LCD" PERIOD = 160 ns HIGH 50%    | N/A     |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 29 secs
Total CPU time to PAR completion: 28 secs
 
Peak Memory Usage:  201 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 1
 
Writing design to file lq057q3dc02_top.ncd
 
 
 
PAR done!

Line No.	Rev	Author	Line
1	32	jwdonal	`Release 9.2.04i par J.40`
2			`Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.`
3
4	46	jwdonal	`NAUTILUS:: Sun Nov 09 22:14:10 2008`
5	32	jwdonal
6			`par -ol high -w lq057q3dc02_top.ncd lq057q3dc02_top.ncd lq057q3dc02_top.pcf`
7
8
9			`Constraints file: lq057q3dc02_top.pcf.`
10			`Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx\ISE_9_2.`
11			`"lq057q3dc02_top" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7`
12
13			`Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)`
14			`Initializing voltage to 1.400 Volts. (default - Range: 1.400 to 1.600 Volts)`
15
16
17			`Device speed data version: "PRODUCTION 1.94 2007-10-19".`
18
19
20			`INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.`
21
22			`Device Utilization Summary:`
23
24			`Number of BUFGMUXs 2 out of 16 12%`
25			`Number of DCMs 1 out of 8 12%`
26			`Number of External IOBs 27 out of 556 4%`
27			`Number of LOCed IOBs 27 out of 27 100%`
28
29			`Number of RAMB16s 87 out of 136 63%`
30	38	jwdonal	`Number of SLICEs 127 out of 13696 1%`
31	32	jwdonal
32
33			`Overall effort level (-ol): High`
34			`Router effort level (-rl): High`
35
36	38	jwdonal	`Starting initial Timing Analysis. REAL time: 9 secs`
37			`Finished initial Timing Analysis. REAL time: 9 secs`
38	32	jwdonal
39			`Starting Router`
40
41	46	jwdonal	`Phase 1: 4052 unrouted; REAL time: 20 secs`
42	32	jwdonal
43	46	jwdonal	`Phase 2: 3381 unrouted; REAL time: 21 secs`
44	32	jwdonal
45	46	jwdonal	`Phase 3: 340 unrouted; REAL time: 25 secs`
46	32	jwdonal
47	46	jwdonal	`Phase 4: 340 unrouted; (0) REAL time: 25 secs`
48	32	jwdonal
49	46	jwdonal	`Phase 5: 340 unrouted; (0) REAL time: 25 secs`
50	32	jwdonal
51	46	jwdonal	`Phase 6: 340 unrouted; (0) REAL time: 25 secs`
52	32	jwdonal
53	46	jwdonal	`Phase 7: 0 unrouted; (0) REAL time: 26 secs`
54	32	jwdonal
55	46	jwdonal	`Phase 8: 0 unrouted; (0) REAL time: 27 secs`
56	32	jwdonal
57			`WARNING:Route:455 - CLK Net:CLK_LCD_OBUF may have excessive skew because`
58
59
60	46	jwdonal	`Total REAL time to Router completion: 27 secs`
61			`Total CPU time to Router completion: 27 secs`
62	32	jwdonal
63			`Partition Implementation Status`
64			`-------------------------------`
65
66			`No Partitions were found in this design.`
67
68			`-------------------------------`
69
70			`Generating "PAR" statistics.`
71
72			`**************************`
73			`Generating Clock Report`
74			`**************************`
75
76			`+---------------------+--------------+------+------+------------+-------------+`
77			`\| Clock Net \| Resource \|Locked\|Fanout\|Net Skew(ns)\|Max Delay(ns)\|`
78			`+---------------------+--------------+------+------+------------+-------------+`
79	38	jwdonal	`\| CLK_LCD_OBUF \| BUFGMUX6P\| No \| 135 \| 0.261 \| 1.238 \|`
80	32	jwdonal	`+---------------------+--------------+------+------+------------+-------------+`
81
82			`* Net Skew is the difference between the minimum and maximum routing`
83			`only delays for the net. Note this is different from Clock Skew which`
84			`is reported in TRCE timing report. Clock Skew is the difference between`
85			`the minimum and maximum path delays which includes logic delays.`
86
87
88			`The Delay Summary Report`
89
90
91			`The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0`
92
93	38	jwdonal	`The AVERAGE CONNECTION DELAY for this design is: 2.320`
94			`The MAXIMUM PIN DELAY IS: 8.568`
95			`The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 7.164`
96	32	jwdonal
97			`Listing Pin Delays by value: (nsec)`
98
99			`d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 9.00 d >= 9.00`
100			`--------- --------- --------- --------- --------- ---------`
101	38	jwdonal	`1084 783 326 65 4 0`
102	32	jwdonal
103			`Timing Score: 0`
104
105			`Number of Timing Constraints that were not applied: 2`
106
107			`Asterisk (*) preceding a constraint indicates it was not met.`
108			`This may be due to a setup or hold violation.`
109
110			`------------------------------------------------------------------------------------------------------`
111			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
112			`\| \| Slack \| Achievable \| Errors \| Score`
113			`------------------------------------------------------------------------------------------------------`
114	38	jwdonal	`PERIOD analysis for net "DCM_LCD_CLK/CLKD \| SETUP \| 150.792ns\| 9.208ns\| 0\| 0`
115			`V_BUF" derived from NET "DCM_LCD_CLK/CLK \| HOLD \| 0.609ns\| \| 0\| 0`
116	32	jwdonal	`IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50% \| \| \| \| \|`
117			`------------------------------------------------------------------------------------------------------`
118			`NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD \| N/A \| N/A\| N/A\| N/A\| N/A`
119			`= 10 ns HIGH 50% \| \| \| \| \|`
120			`------------------------------------------------------------------------------------------------------`
121			`NET "CLK_LCD" PERIOD = 160 ns HIGH 50% \| N/A \| N/A\| N/A\| N/A\| N/A`
122			`------------------------------------------------------------------------------------------------------`
123
124
125			`All constraints were met.`
126			`INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the`
127			`constraint does not cover any paths or that it has no requested value.`
128
129
130			`Generating Pad Report.`
131
132			`All signals are completely routed.`
133
134	46	jwdonal	`Total REAL time to PAR completion: 29 secs`
135			`Total CPU time to PAR completion: 28 secs`
136	32	jwdonal
137	38	jwdonal	`Peak Memory Usage: 201 MB`
138	32	jwdonal
139			`Placer: Placement generated during map.`
140			`Routing: Completed - No errors found.`
141			`Timing: Completed - No errors found.`
142
143			`Number of error messages: 0`
144			`Number of warning messages: 1`
145			`Number of info messages: 1`
146
147			`Writing design to file lq057q3dc02_top.ncd`
148
149
150
151			`PAR done!`

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[/] [lq057q3dc02/] [trunk/] [implement/] [results/] [lq057q3dc02_top.par] - Blame information for rev 46