Subversion Repositories lq057q3dc02

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Release 9.2.04i Trace

Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

trce -e 10 lq057q3dc02_top.ncd -o lq057q3dc02_top.twr lq057q3dc02_top.pcf

Design file:              lq057q3dc02_top.ncd

Physical constraint file: lq057q3dc02_top.pcf

Device,package,speed:     xc2vp30,ff896,-7 (PRODUCTION 1.94 2007-10-19)

Report level:             error report, limited to 10 items per constraint

Environment Variable      Effect

--------------------      ------

NONE                      No environment variables were set

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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths

   option. All paths that are not constrained will be reported in the

   unconstrained paths section(s) of the report.

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on

   a 50 Ohm transmission line loading model.  For the details of this model,

   and for more information on accounting for different loading conditions,

   please see the device datasheet.

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Timing constraint: NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%;

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================================================================================

Timing constraint: PERIOD analysis for net "DCM_LCD_CLK/CLKDV_BUF" derived from

 NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%;  multiplied by

16.00 and duty cycle corrected to 160 nS  HIGH 80 nS

 3691 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)

 Minimum period is   9.208ns.

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================================================================================

Timing constraint: NET "CLK_LCD" PERIOD = 160 ns HIGH 50%;

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All constraints were met.

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK_100M_PAD

---------------+---------+---------+---------+---------+

               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

CLK_100M_PAD   |    9.208|         |         |         |

---------------+---------+---------+---------+---------+

Timing summary:

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Timing errors: 0  Score: 0

Constraints cover 3691 paths, 0 nets, and 1952 connections

Design statistics:

   Minimum period:   9.208ns   (Maximum frequency: 108.601MHz)

Analysis completed Sun Nov 09 22:14:45 2008

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Trace Settings:

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Trace Settings

Peak Memory Usage: 148 MB