| 1 |
32 |
jwdonal |
Release 9.2.04i - xst J.40
|
| 2 |
|
|
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
|
| 3 |
|
|
--> -->
|
| 4 |
|
|
TABLE OF CONTENTS
|
| 5 |
|
|
1) Synthesis Options Summary
|
| 6 |
|
|
2) HDL Compilation
|
| 7 |
|
|
3) Design Hierarchy Analysis
|
| 8 |
|
|
4) HDL Analysis
|
| 9 |
|
|
5) HDL Synthesis
|
| 10 |
|
|
5.1) HDL Synthesis Report
|
| 11 |
|
|
6) Advanced HDL Synthesis
|
| 12 |
|
|
6.1) Advanced HDL Synthesis Report
|
| 13 |
|
|
7) Low Level Synthesis
|
| 14 |
|
|
8) Partition Report
|
| 15 |
|
|
9) Final Report
|
| 16 |
|
|
9.1) Device utilization summary
|
| 17 |
|
|
9.2) Partition Resource Summary
|
| 18 |
|
|
9.3) TIMING REPORT
|
| 19 |
|
|
|
| 20 |
|
|
|
| 21 |
|
|
=========================================================================
|
| 22 |
|
|
* Synthesis Options Summary *
|
| 23 |
|
|
=========================================================================
|
| 24 |
|
|
---- Source Parameters
|
| 25 |
|
|
Input Format : MIXED
|
| 26 |
|
|
Input File Name : "../xst.prj"
|
| 27 |
|
|
|
| 28 |
|
|
---- Target Parameters
|
| 29 |
|
|
Target Device : xc2vp30-ff896-7
|
| 30 |
|
|
Output File Name : "lq057q3dc02_top_part"
|
| 31 |
|
|
|
| 32 |
|
|
---- Source Options
|
| 33 |
|
|
Top Module Name : lq057q3dc02_top
|
| 34 |
|
|
|
| 35 |
|
|
---- Target Options
|
| 36 |
|
|
Equivalent register Removal : no
|
| 37 |
|
|
Global Maximum Fanout : 65535
|
| 38 |
|
|
|
| 39 |
|
|
---- General Options
|
| 40 |
|
|
Optimization Goal : SPEED
|
| 41 |
|
|
Optimization Effort : 1
|
| 42 |
|
|
Keep Hierarchy : soft
|
| 43 |
|
|
|
| 44 |
|
|
=========================================================================
|
| 45 |
|
|
|
| 46 |
|
|
|
| 47 |
|
|
=========================================================================
|
| 48 |
|
|
* HDL Compilation *
|
| 49 |
|
|
=========================================================================
|
| 50 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/components.vhd" in Library work_vhsic.
|
| 51 |
32 |
jwdonal |
Package compiled.
|
| 52 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/hsyncx_control.vhd" in Library work_vhsic.
|
| 53 |
32 |
jwdonal |
Entity compiled.
|
| 54 |
|
|
Entity (Architecture ) compiled.
|
| 55 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/vsyncx_control.vhd" in Library work_vhsic.
|
| 56 |
32 |
jwdonal |
Entity compiled.
|
| 57 |
|
|
Entity (Architecture ) compiled.
|
| 58 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/clk_lcd_cyc_cntr.vhd" in Library work_vhsic.
|
| 59 |
32 |
jwdonal |
Entity compiled.
|
| 60 |
|
|
Entity (Architecture ) compiled.
|
| 61 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/enab_control.vhd" in Library work_vhsic.
|
| 62 |
32 |
jwdonal |
Entity compiled.
|
| 63 |
|
|
Entity (Architecture ) compiled.
|
| 64 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/dcm_sys_to_lcd.vhd" in Library work_vhsic.
|
| 65 |
32 |
jwdonal |
Entity compiled.
|
| 66 |
|
|
Entity (Architecture ) compiled.
|
| 67 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/video_controller.vhd" in Library work_vhsic.
|
| 68 |
32 |
jwdonal |
Entity compiled.
|
| 69 |
|
|
Entity (Architecture ) compiled.
|
| 70 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/image_gen_bram.vhd" in Library work_vhsic.
|
| 71 |
32 |
jwdonal |
Entity compiled.
|
| 72 |
|
|
Entity (Architecture ) compiled.
|
| 73 |
38 |
jwdonal |
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" in Library work_vhsic.
|
| 74 |
32 |
jwdonal |
Entity compiled.
|
| 75 |
|
|
Entity (Architecture ) compiled.
|
| 76 |
|
|
|
| 77 |
|
|
=========================================================================
|
| 78 |
|
|
* Design Hierarchy Analysis *
|
| 79 |
|
|
=========================================================================
|
| 80 |
|
|
Analyzing hierarchy for entity in library (architecture ) with generics.
|
| 81 |
|
|
C_BIT_DEPTH = 18
|
| 82 |
|
|
C_BRAM_ADDR_WIDTH = 17
|
| 83 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 84 |
|
|
C_ENAB_TEP = 320
|
| 85 |
|
|
C_ENAB_THE = 8
|
| 86 |
|
|
C_HSYNC_TH = 400
|
| 87 |
|
|
C_HSYNC_THP = 10
|
| 88 |
|
|
C_IMAGE_HEIGHT = 240
|
| 89 |
|
|
C_IMAGE_WIDTH = 320
|
| 90 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 91 |
|
|
C_NUM_CLKS_WIDTH = 9
|
| 92 |
|
|
C_RL_STATUS = '0'
|
| 93 |
|
|
C_UD_STATUS = '1'
|
| 94 |
|
|
C_VQ_STATUS = '0'
|
| 95 |
|
|
C_VSYNC_TV = 255
|
| 96 |
|
|
C_VSYNC_TVP = 3
|
| 97 |
|
|
C_VSYNC_TVS = 7
|
| 98 |
|
|
|
| 99 |
|
|
Analyzing hierarchy for entity in library (architecture ).
|
| 100 |
|
|
|
| 101 |
|
|
Analyzing hierarchy for entity in library (architecture ) with generics.
|
| 102 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 103 |
|
|
C_ENAB_TEP = 320
|
| 104 |
|
|
C_ENAB_THE = 8
|
| 105 |
|
|
C_HSYNC_TH = 400
|
| 106 |
|
|
C_HSYNC_THP = 10
|
| 107 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 108 |
|
|
C_NUM_CLKS_WIDTH = 9
|
| 109 |
|
|
C_RL_STATUS = '0'
|
| 110 |
|
|
C_UD_STATUS = '1'
|
| 111 |
|
|
C_VQ_STATUS = '0'
|
| 112 |
|
|
C_VSYNC_TV = 255
|
| 113 |
|
|
C_VSYNC_TVP = 3
|
| 114 |
|
|
C_VSYNC_TVS = 7
|
| 115 |
|
|
|
| 116 |
|
|
Analyzing hierarchy for entity in library (architecture ) with generics.
|
| 117 |
|
|
C_BIT_DEPTH = 18
|
| 118 |
|
|
C_BRAM_ADDR_WIDTH = 17
|
| 119 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 120 |
|
|
C_ENAB_TEP = 320
|
| 121 |
|
|
C_ENAB_THE = 8
|
| 122 |
|
|
C_IMAGE_HEIGHT = 240
|
| 123 |
|
|
C_IMAGE_WIDTH = 320
|
| 124 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 125 |
|
|
C_VSYNC_TVS = 7
|
| 126 |
|
|
|
| 127 |
|
|
Analyzing hierarchy for entity in library (architecture ) with generics.
|
| 128 |
|
|
C_HSYNC_TH = 400
|
| 129 |
|
|
C_HSYNC_THP = 10
|
| 130 |
|
|
C_NUM_CLKS_WIDTH = 9
|
| 131 |
|
|
|
| 132 |
|
|
Analyzing hierarchy for entity in library (architecture ) with generics.
|
| 133 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 134 |
|
|
C_VSYNC_TV = 255
|
| 135 |
|
|
C_VSYNC_TVP = 3
|
| 136 |
|
|
|
| 137 |
|
|
Analyzing hierarchy for entity in library (architecture ) with generics.
|
| 138 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 139 |
|
|
C_ENAB_TEP = 320
|
| 140 |
|
|
C_ENAB_THE = 8
|
| 141 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 142 |
|
|
C_VSYNC_TVS = 7
|
| 143 |
|
|
|
| 144 |
|
|
Analyzing hierarchy for entity in library (architecture ) with generics.
|
| 145 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 146 |
|
|
C_ENAB_TEP = 320
|
| 147 |
|
|
C_ENAB_THE = 8
|
| 148 |
|
|
C_VSYNC_TVS = 7
|
| 149 |
|
|
|
| 150 |
|
|
|
| 151 |
|
|
=========================================================================
|
| 152 |
|
|
* HDL Analysis *
|
| 153 |
|
|
=========================================================================
|
| 154 |
|
|
Analyzing generic Entity in library (Architecture ).
|
| 155 |
|
|
C_BIT_DEPTH = 18
|
| 156 |
|
|
C_BRAM_ADDR_WIDTH = 17
|
| 157 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 158 |
|
|
C_ENAB_TEP = 320
|
| 159 |
|
|
C_ENAB_THE = 8
|
| 160 |
|
|
C_HSYNC_TH = 400
|
| 161 |
|
|
C_HSYNC_THP = 10
|
| 162 |
|
|
C_IMAGE_HEIGHT = 240
|
| 163 |
|
|
C_IMAGE_WIDTH = 320
|
| 164 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 165 |
|
|
C_NUM_CLKS_WIDTH = 9
|
| 166 |
|
|
C_RL_STATUS = '0'
|
| 167 |
|
|
C_UD_STATUS = '1'
|
| 168 |
|
|
C_VQ_STATUS = '0'
|
| 169 |
|
|
C_VSYNC_TV = 255
|
| 170 |
|
|
C_VSYNC_TVP = 3
|
| 171 |
|
|
C_VSYNC_TVS = 7
|
| 172 |
38 |
jwdonal |
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'dcm_sys_to_lcd'.
|
| 173 |
|
|
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLK0_OUT' of component 'dcm_sys_to_lcd'.
|
| 174 |
|
|
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKFX_OUT' of component 'dcm_sys_to_lcd'.
|
| 175 |
32 |
jwdonal |
Entity analyzed. Unit generated.
|
| 176 |
|
|
|
| 177 |
|
|
Analyzing Entity in library (Architecture ).
|
| 178 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 179 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 180 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 181 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 182 |
|
|
Set user-defined property "CLKFX_DIVIDE = 4" for instance in unit .
|
| 183 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = TRUE" for instance in unit .
|
| 184 |
|
|
Set user-defined property "CLKDV_DIVIDE = 8.0000000000000000" for instance in unit .
|
| 185 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 186 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 2" for instance in unit .
|
| 187 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.0000000000000000" for instance in unit .
|
| 188 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 189 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 190 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 191 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 192 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 193 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 194 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 195 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 196 |
|
|
Entity analyzed. Unit generated.
|
| 197 |
|
|
|
| 198 |
|
|
Analyzing generic Entity in library (Architecture ).
|
| 199 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 200 |
|
|
C_ENAB_TEP = 320
|
| 201 |
|
|
C_ENAB_THE = 8
|
| 202 |
|
|
C_HSYNC_TH = 400
|
| 203 |
|
|
C_HSYNC_THP = 10
|
| 204 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 205 |
|
|
C_NUM_CLKS_WIDTH = 9
|
| 206 |
|
|
C_RL_STATUS = '0'
|
| 207 |
|
|
C_UD_STATUS = '1'
|
| 208 |
|
|
C_VQ_STATUS = '0'
|
| 209 |
|
|
C_VSYNC_TV = 255
|
| 210 |
|
|
C_VSYNC_TVP = 3
|
| 211 |
|
|
C_VSYNC_TVS = 7
|
| 212 |
|
|
Entity analyzed. Unit generated.
|
| 213 |
|
|
|
| 214 |
|
|
Analyzing generic Entity in library (Architecture ).
|
| 215 |
|
|
C_HSYNC_TH = 400
|
| 216 |
|
|
C_HSYNC_THP = 10
|
| 217 |
|
|
C_NUM_CLKS_WIDTH = 9
|
| 218 |
|
|
Entity analyzed. Unit generated.
|
| 219 |
|
|
|
| 220 |
|
|
Analyzing generic Entity in library (Architecture ).
|
| 221 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 222 |
|
|
C_VSYNC_TV = 255
|
| 223 |
|
|
C_VSYNC_TVP = 3
|
| 224 |
|
|
Entity analyzed. Unit generated.
|
| 225 |
|
|
|
| 226 |
|
|
Analyzing generic Entity in library (Architecture ).
|
| 227 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 228 |
|
|
C_ENAB_TEP = 320
|
| 229 |
|
|
C_ENAB_THE = 8
|
| 230 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 231 |
|
|
C_VSYNC_TVS = 7
|
| 232 |
|
|
Entity analyzed. Unit generated.
|
| 233 |
|
|
|
| 234 |
|
|
Analyzing generic Entity in library (Architecture ).
|
| 235 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 236 |
|
|
C_ENAB_TEP = 320
|
| 237 |
|
|
C_ENAB_THE = 8
|
| 238 |
|
|
C_VSYNC_TVS = 7
|
| 239 |
|
|
Entity analyzed. Unit generated.
|
| 240 |
|
|
|
| 241 |
|
|
Analyzing generic Entity in library (Architecture ).
|
| 242 |
|
|
C_BIT_DEPTH = 18
|
| 243 |
|
|
C_BRAM_ADDR_WIDTH = 17
|
| 244 |
|
|
C_CLK_LCD_CYC_NUM_WIDTH = 9
|
| 245 |
|
|
C_ENAB_TEP = 320
|
| 246 |
|
|
C_ENAB_THE = 8
|
| 247 |
|
|
C_IMAGE_HEIGHT = 240
|
| 248 |
|
|
C_IMAGE_WIDTH = 320
|
| 249 |
|
|
C_LINE_NUM_WIDTH = 9
|
| 250 |
|
|
C_VSYNC_TVS = 7
|
| 251 |
|
|
Entity analyzed. Unit generated.
|
| 252 |
|
|
|
| 253 |
|
|
|
| 254 |
|
|
=========================================================================
|
| 255 |
|
|
* HDL Synthesis *
|
| 256 |
|
|
=========================================================================
|
| 257 |
|
|
|
| 258 |
|
|
Performing bidirectional port resolution...
|
| 259 |
|
|
|
| 260 |
|
|
Synthesizing Unit .
|
| 261 |
38 |
jwdonal |
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/hsyncx_control.vhd".
|
| 262 |
32 |
jwdonal |
Found 1-bit register for signal .
|
| 263 |
|
|
Found 10-bit comparator less for signal created at line 136.
|
| 264 |
|
|
Found 9-bit up counter for signal .
|
| 265 |
|
|
Summary:
|
| 266 |
|
|
inferred 1 Counter(s).
|
| 267 |
|
|
inferred 1 D-type flip-flop(s).
|
| 268 |
|
|
inferred 1 Comparator(s).
|
| 269 |
|
|
Unit synthesized.
|
| 270 |
|
|
|
| 271 |
|
|
|
| 272 |
|
|
Synthesizing Unit .
|
| 273 |
38 |
jwdonal |
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/vsyncx_control.vhd".
|
| 274 |
32 |
jwdonal |
Found finite state machine for signal .
|
| 275 |
|
|
-----------------------------------------------------------------------
|
| 276 |
|
|
| States | 4 |
|
| 277 |
|
|
| Transitions | 8 |
|
| 278 |
|
|
| Inputs | 2 |
|
| 279 |
|
|
| Outputs | 2 |
|
| 280 |
|
|
| Clock | CLK_LCD (rising_edge) |
|
| 281 |
|
|
| Reset | RSTx (negative) |
|
| 282 |
|
|
| Reset type | asynchronous |
|
| 283 |
|
|
| Reset State | ready |
|
| 284 |
|
|
| Power Up State | frame_start |
|
| 285 |
|
|
| Encoding | automatic |
|
| 286 |
|
|
| Implementation | automatic |
|
| 287 |
|
|
-----------------------------------------------------------------------
|
| 288 |
|
|
Found 1-bit register for signal .
|
| 289 |
|
|
Found 9-bit up counter for signal .
|
| 290 |
|
|
Found 10-bit comparator less for signal created at line 382.
|
| 291 |
|
|
Summary:
|
| 292 |
|
|
inferred 1 Finite State Machine(s).
|
| 293 |
|
|
inferred 1 Counter(s).
|
| 294 |
|
|
inferred 1 D-type flip-flop(s).
|
| 295 |
|
|
inferred 1 Comparator(s).
|
| 296 |
|
|
Unit synthesized.
|
| 297 |
|
|
|
| 298 |
|
|
|
| 299 |
|
|
Synthesizing Unit .
|
| 300 |
38 |
jwdonal |
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/clk_lcd_cyc_cntr.vhd".
|
| 301 |
32 |
jwdonal |
Found finite state machine for signal .
|
| 302 |
|
|
-----------------------------------------------------------------------
|
| 303 |
|
|
| States | 5 |
|
| 304 |
|
|
| Transitions | 12 |
|
| 305 |
|
|
| Inputs | 6 |
|
| 306 |
|
|
| Outputs | 1 |
|
| 307 |
|
|
| Clock | CLK_LCD (rising_edge) |
|
| 308 |
|
|
| Reset | RSTx (negative) |
|
| 309 |
|
|
| Reset type | asynchronous |
|
| 310 |
|
|
| Reset State | inactive_wait_1 |
|
| 311 |
|
|
| Power Up State | inactive_wait_1 |
|
| 312 |
|
|
| Encoding | automatic |
|
| 313 |
|
|
| Implementation | automatic |
|
| 314 |
|
|
-----------------------------------------------------------------------
|
| 315 |
|
|
Found 10-bit comparator less for signal created at line 205.
|
| 316 |
|
|
Found 9-bit up counter for signal .
|
| 317 |
|
|
Summary:
|
| 318 |
|
|
inferred 1 Finite State Machine(s).
|
| 319 |
|
|
inferred 1 Counter(s).
|
| 320 |
|
|
inferred 1 Comparator(s).
|
| 321 |
|
|
Unit synthesized.
|
| 322 |
|
|
|
| 323 |
|
|
|
| 324 |
|
|
Synthesizing Unit .
|
| 325 |
38 |
jwdonal |
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/enab_control.vhd".
|
| 326 |
32 |
jwdonal |
Found 1-bit register for signal .
|
| 327 |
|
|
Found 10-bit comparator greatequal for signal created at line 131.
|
| 328 |
|
|
Found 10-bit comparator less for signal created at line 131.
|
| 329 |
|
|
Summary:
|
| 330 |
|
|
inferred 1 D-type flip-flop(s).
|
| 331 |
|
|
inferred 2 Comparator(s).
|
| 332 |
|
|
Unit synthesized.
|
| 333 |
|
|
|
| 334 |
|
|
|
| 335 |
|
|
Synthesizing Unit .
|
| 336 |
38 |
jwdonal |
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/dcm_sys_to_lcd.vhd".
|
| 337 |
32 |
jwdonal |
Unit synthesized.
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
|
|
Synthesizing Unit .
|
| 341 |
38 |
jwdonal |
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/video_controller.vhd".
|
| 342 |
32 |
jwdonal |
Unit synthesized.
|
| 343 |
|
|
|
| 344 |
|
|
|
| 345 |
|
|
Synthesizing Unit .
|
| 346 |
38 |
jwdonal |
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/image_gen_bram.vhd".
|
| 347 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 348 |
32 |
jwdonal |
Found 17-bit up counter for signal .
|
| 349 |
46 |
jwdonal |
Found 10-bit comparator greatequal for signal created at line 233.
|
| 350 |
|
|
Found 10-bit comparator greatequal for signal created at line 239.
|
| 351 |
|
|
Found 10-bit comparator less for signal created at line 233.
|
| 352 |
|
|
Found 10-bit comparator less for signal created at line 233.
|
| 353 |
32 |
jwdonal |
Summary:
|
| 354 |
|
|
inferred 1 Counter(s).
|
| 355 |
38 |
jwdonal |
inferred 4 Comparator(s).
|
| 356 |
32 |
jwdonal |
Unit synthesized.
|
| 357 |
|
|
|
| 358 |
|
|
|
| 359 |
|
|
Synthesizing Unit .
|
| 360 |
38 |
jwdonal |
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd".
|
| 361 |
32 |
jwdonal |
Unit synthesized.
|
| 362 |
|
|
|
| 363 |
|
|
|
| 364 |
|
|
=========================================================================
|
| 365 |
|
|
HDL Synthesis Report
|
| 366 |
|
|
|
| 367 |
|
|
Macro Statistics
|
| 368 |
|
|
# Counters : 4
|
| 369 |
|
|
17-bit up counter : 1
|
| 370 |
|
|
9-bit up counter : 3
|
| 371 |
38 |
jwdonal |
# Registers : 3
|
| 372 |
|
|
1-bit register : 3
|
| 373 |
|
|
# Comparators : 9
|
| 374 |
|
|
10-bit comparator greatequal : 3
|
| 375 |
|
|
10-bit comparator less : 6
|
| 376 |
32 |
jwdonal |
|
| 377 |
|
|
=========================================================================
|
| 378 |
|
|
|
| 379 |
|
|
=========================================================================
|
| 380 |
|
|
* Advanced HDL Synthesis *
|
| 381 |
|
|
=========================================================================
|
| 382 |
|
|
|
| 383 |
|
|
Analyzing FSM for best encoding.
|
| 384 |
|
|
Optimizing FSM on signal with sequential encoding.
|
| 385 |
|
|
-------------------------------
|
| 386 |
|
|
State | Encoding
|
| 387 |
|
|
-------------------------------
|
| 388 |
|
|
inactive_wait_1 | 000
|
| 389 |
|
|
inactive_wait_2 | 010
|
| 390 |
|
|
inactive_wait_tvs | 001
|
| 391 |
|
|
inactive_wait_the | 011
|
| 392 |
|
|
active | 100
|
| 393 |
|
|
-------------------------------
|
| 394 |
|
|
Analyzing FSM for best encoding.
|
| 395 |
|
|
Optimizing FSM on signal with gray encoding.
|
| 396 |
|
|
-------------------------
|
| 397 |
|
|
State | Encoding
|
| 398 |
|
|
-------------------------
|
| 399 |
|
|
frame_start | 00
|
| 400 |
|
|
add | 10
|
| 401 |
|
|
add_wait | 11
|
| 402 |
|
|
ready | 01
|
| 403 |
|
|
-------------------------
|
| 404 |
|
|
Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx\ISE_9_2.
|
| 405 |
|
|
|
| 406 |
|
|
=========================================================================
|
| 407 |
|
|
Advanced HDL Synthesis Report
|
| 408 |
|
|
|
| 409 |
|
|
Macro Statistics
|
| 410 |
|
|
# FSMs : 2
|
| 411 |
|
|
# Counters : 4
|
| 412 |
|
|
17-bit up counter : 1
|
| 413 |
|
|
9-bit up counter : 3
|
| 414 |
38 |
jwdonal |
# Registers : 8
|
| 415 |
|
|
Flip-Flops : 8
|
| 416 |
|
|
# Comparators : 9
|
| 417 |
|
|
10-bit comparator greatequal : 3
|
| 418 |
|
|
10-bit comparator less : 6
|
| 419 |
32 |
jwdonal |
|
| 420 |
|
|
=========================================================================
|
| 421 |
|
|
|
| 422 |
|
|
=========================================================================
|
| 423 |
|
|
* Low Level Synthesis *
|
| 424 |
|
|
=========================================================================
|
| 425 |
|
|
|
| 426 |
|
|
Optimizing unit ...
|
| 427 |
|
|
|
| 428 |
|
|
Optimizing unit ...
|
| 429 |
|
|
|
| 430 |
|
|
Optimizing unit ...
|
| 431 |
|
|
|
| 432 |
|
|
Optimizing unit ...
|
| 433 |
|
|
|
| 434 |
|
|
Optimizing unit ...
|
| 435 |
|
|
|
| 436 |
|
|
Optimizing unit ...
|
| 437 |
|
|
|
| 438 |
|
|
Optimizing unit ...
|
| 439 |
|
|
|
| 440 |
|
|
Optimizing unit ...
|
| 441 |
|
|
|
| 442 |
|
|
Mapping all equations...
|
| 443 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 444 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 445 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 446 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 447 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 448 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 449 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 450 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 451 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 452 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 453 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 454 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 455 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 456 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 457 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 458 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 459 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 460 |
|
|
WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.
|
| 461 |
|
|
Building and optimizing final netlist ...
|
| 462 |
|
|
|
| 463 |
|
|
Final Macro Processing ...
|
| 464 |
|
|
|
| 465 |
|
|
=========================================================================
|
| 466 |
|
|
Final Register Report
|
| 467 |
|
|
|
| 468 |
|
|
Macro Statistics
|
| 469 |
38 |
jwdonal |
# Registers : 52
|
| 470 |
|
|
Flip-Flops : 52
|
| 471 |
32 |
jwdonal |
|
| 472 |
|
|
=========================================================================
|
| 473 |
|
|
|
| 474 |
|
|
=========================================================================
|
| 475 |
|
|
* Partition Report *
|
| 476 |
|
|
=========================================================================
|
| 477 |
|
|
|
| 478 |
|
|
Partition Implementation Status
|
| 479 |
|
|
-------------------------------
|
| 480 |
|
|
|
| 481 |
|
|
No Partitions were found in this design.
|
| 482 |
|
|
|
| 483 |
|
|
-------------------------------
|
| 484 |
|
|
|
| 485 |
|
|
=========================================================================
|
| 486 |
|
|
* Final Report *
|
| 487 |
|
|
=========================================================================
|
| 488 |
|
|
Final Results
|
| 489 |
|
|
Top Level Output File Name : lq057q3dc02_top_part
|
| 490 |
|
|
Output Format : ngc
|
| 491 |
|
|
Optimization Goal : SPEED
|
| 492 |
|
|
Keep Hierarchy : soft
|
| 493 |
|
|
|
| 494 |
|
|
Design Statistics
|
| 495 |
|
|
# IOs : 27
|
| 496 |
|
|
|
| 497 |
|
|
Cell Usage :
|
| 498 |
38 |
jwdonal |
# BELS : 207
|
| 499 |
32 |
jwdonal |
# GND : 6
|
| 500 |
|
|
# INV : 9
|
| 501 |
|
|
# LUT1 : 8
|
| 502 |
|
|
# LUT2 : 7
|
| 503 |
38 |
jwdonal |
# LUT2_L : 5
|
| 504 |
|
|
# LUT3 : 25
|
| 505 |
|
|
# LUT3_D : 1
|
| 506 |
32 |
jwdonal |
# LUT3_L : 1
|
| 507 |
38 |
jwdonal |
# LUT4 : 52
|
| 508 |
32 |
jwdonal |
# LUT4_L : 7
|
| 509 |
|
|
# MUXCY : 40
|
| 510 |
38 |
jwdonal |
# MUXF5 : 1
|
| 511 |
32 |
jwdonal |
# VCC : 2
|
| 512 |
|
|
# XORCY : 43
|
| 513 |
38 |
jwdonal |
# FlipFlops/Latches : 52
|
| 514 |
|
|
# FDC : 23
|
| 515 |
32 |
jwdonal |
# FDCE : 26
|
| 516 |
|
|
# FDP : 3
|
| 517 |
|
|
# Clock Buffers : 3
|
| 518 |
|
|
# BUFG : 3
|
| 519 |
|
|
# IO Buffers : 27
|
| 520 |
|
|
# IBUF : 1
|
| 521 |
|
|
# IBUFG : 1
|
| 522 |
|
|
# OBUF : 25
|
| 523 |
|
|
# DCMs : 1
|
| 524 |
|
|
# DCM : 1
|
| 525 |
|
|
# Others : 3
|
| 526 |
|
|
# image_gen_bram_blue : 1
|
| 527 |
|
|
# image_gen_bram_green : 1
|
| 528 |
|
|
# image_gen_bram_red : 1
|
| 529 |
|
|
=========================================================================
|
| 530 |
|
|
|
| 531 |
|
|
Device utilization summary:
|
| 532 |
|
|
---------------------------
|
| 533 |
|
|
|
| 534 |
|
|
Selected Device : 2vp30ff896-7
|
| 535 |
|
|
|
| 536 |
38 |
jwdonal |
Number of Slices: 58 out of 13696 0%
|
| 537 |
|
|
Number of Slice Flip Flops: 52 out of 27392 0%
|
| 538 |
|
|
Number of 4 input LUTs: 115 out of 27392 0%
|
| 539 |
32 |
jwdonal |
Number of IOs: 27
|
| 540 |
|
|
Number of bonded IOBs: 26 out of 556 4%
|
| 541 |
|
|
Number of GCLKs: 3 out of 16 18%
|
| 542 |
|
|
Number of DCMs: 1 out of 8 12%
|
| 543 |
|
|
|
| 544 |
|
|
---------------------------
|
| 545 |
|
|
Partition Resource Summary:
|
| 546 |
|
|
---------------------------
|
| 547 |
|
|
|
| 548 |
|
|
No Partitions were found in this design.
|
| 549 |
|
|
|
| 550 |
|
|
---------------------------
|
| 551 |
|
|
|
| 552 |
|
|
|
| 553 |
|
|
=========================================================================
|
| 554 |
|
|
TIMING REPORT
|
| 555 |
|
|
|
| 556 |
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
| 557 |
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
| 558 |
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
| 559 |
|
|
|
| 560 |
|
|
Clock Information:
|
| 561 |
|
|
------------------
|
| 562 |
|
|
-----------------------------------+------------------------+-------+
|
| 563 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 564 |
|
|
-----------------------------------+------------------------+-------+
|
| 565 |
38 |
jwdonal |
CLK_100M_PAD | DCM_INST:CLKDV | 52 |
|
| 566 |
32 |
jwdonal |
-----------------------------------+------------------------+-------+
|
| 567 |
|
|
|
| 568 |
|
|
Asynchronous Control Signals Information:
|
| 569 |
|
|
----------------------------------------
|
| 570 |
46 |
jwdonal |
-----------------------------------------------------------------------------------------------+-----------------------------------------------+-------+
|
| 571 |
|
|
Control Signal | Buffer(FF name) | Load |
|
| 572 |
|
|
-----------------------------------------------------------------------------------------------+-----------------------------------------------+-------+
|
| 573 |
|
|
V_C/HSYNCx_C/RSTx_inv(V_C/HSYNCx_C/RSTx_inv1_INV_0:O) | NONE(V_C/HSYNCx_C/HSYNCx) | 10 |
|
| 574 |
|
|
V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv(V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv1_INV_0:O)| NONE(V_C/CLK_LCD_CYCLE_Cntr/clk_cyc_num_reg_1)| 12 |
|
| 575 |
|
|
IMAGE/RSTx_inv(IMAGE/RSTx_inv1_INV_0:O) | NONE(IMAGE/ADDR_wire_10) | 17 |
|
| 576 |
|
|
V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv(V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv1_INV_0:O) | NONE(V_C/VSYNCx_C/line_num_reg_6) | 12 |
|
| 577 |
|
|
V_C/ENAB_C/RSTx_inv(V_C/ENAB_C/RSTx_inv1_INV_0:O) | NONE(V_C/ENAB_C/ENAB) | 1 |
|
| 578 |
|
|
-----------------------------------------------------------------------------------------------+-----------------------------------------------+-------+
|
| 579 |
32 |
jwdonal |
|
| 580 |
|
|
Timing Summary:
|
| 581 |
|
|
---------------
|
| 582 |
|
|
Speed Grade: -7
|
| 583 |
|
|
|
| 584 |
|
|
Minimum period: 0.500ns (Maximum Frequency: 2000.475MHz)
|
| 585 |
|
|
Minimum input arrival time before clock: No path found
|
| 586 |
|
|
Maximum output required time after clock: 3.390ns
|
| 587 |
|
|
Maximum combinational path delay: 2.924ns
|
| 588 |
|
|
|
| 589 |
|
|
Timing Detail:
|
| 590 |
|
|
--------------
|
| 591 |
|
|
All values displayed in nanoseconds (ns)
|
| 592 |
|
|
|
| 593 |
|
|
=========================================================================
|
| 594 |
|
|
Timing constraint: Default period analysis for Clock 'CLK_100M_PAD'
|
| 595 |
|
|
Clock period: 0.500ns (frequency: 2000.475MHz)
|
| 596 |
38 |
jwdonal |
Total number of paths / destination ports: 2197 / 78
|
| 597 |
32 |
jwdonal |
-------------------------------------------------------------------------
|
| 598 |
|
|
Delay: 3.999ns (Levels of Logic = 21)
|
| 599 |
|
|
Source: V_C/VSYNCx_C/line_num_reg_6 (FF)
|
| 600 |
|
|
Destination: IMAGE/ADDR_wire_16 (FF)
|
| 601 |
|
|
Source Clock: CLK_100M_PAD rising 0.1X
|
| 602 |
|
|
Destination Clock: CLK_100M_PAD rising 0.1X
|
| 603 |
|
|
|
| 604 |
|
|
Data Path: V_C/VSYNCx_C/line_num_reg_6 to IMAGE/ADDR_wire_16
|
| 605 |
|
|
Gate Net
|
| 606 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 607 |
|
|
---------------------------------------- ------------
|
| 608 |
|
|
FDCE:C->Q 8 0.370 0.614 line_num_reg_6 (LINE_NUM<6>)
|
| 609 |
|
|
end scope: 'VSYNCx_C'
|
| 610 |
|
|
end scope: 'V_C'
|
| 611 |
|
|
begin scope: 'IMAGE'
|
| 612 |
38 |
jwdonal |
LUT4:I0->O 16 0.275 0.668 Mcount_ADDR_wire_lut<0>_SW0 (N92)
|
| 613 |
32 |
jwdonal |
LUT4:I3->O 1 0.275 0.000 Mcount_ADDR_wire_lut<0> (N2)
|
| 614 |
|
|
MUXCY:S->O 1 0.334 0.000 Mcount_ADDR_wire_cy<0> (Mcount_ADDR_wire_cy<0>)
|
| 615 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<1> (Mcount_ADDR_wire_cy<1>)
|
| 616 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<2> (Mcount_ADDR_wire_cy<2>)
|
| 617 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<3> (Mcount_ADDR_wire_cy<3>)
|
| 618 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<4> (Mcount_ADDR_wire_cy<4>)
|
| 619 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<5> (Mcount_ADDR_wire_cy<5>)
|
| 620 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<6> (Mcount_ADDR_wire_cy<6>)
|
| 621 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<7> (Mcount_ADDR_wire_cy<7>)
|
| 622 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<8> (Mcount_ADDR_wire_cy<8>)
|
| 623 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<9> (Mcount_ADDR_wire_cy<9>)
|
| 624 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<10> (Mcount_ADDR_wire_cy<10>)
|
| 625 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<11> (Mcount_ADDR_wire_cy<11>)
|
| 626 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<12> (Mcount_ADDR_wire_cy<12>)
|
| 627 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<13> (Mcount_ADDR_wire_cy<13>)
|
| 628 |
|
|
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<14> (Mcount_ADDR_wire_cy<14>)
|
| 629 |
|
|
MUXCY:CI->O 0 0.036 0.000 Mcount_ADDR_wire_cy<15> (Mcount_ADDR_wire_cy<15>)
|
| 630 |
|
|
XORCY:CI->O 1 0.708 0.000 Mcount_ADDR_wire_xor<16> (Mcount_ADDR_wire16)
|
| 631 |
|
|
FDCE:D 0.208 ADDR_wire_16
|
| 632 |
|
|
----------------------------------------
|
| 633 |
|
|
Total 3.999ns (2.717ns logic, 1.282ns route)
|
| 634 |
|
|
(68.0% logic, 32.0% route)
|
| 635 |
|
|
|
| 636 |
|
|
=========================================================================
|
| 637 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK_100M_PAD'
|
| 638 |
38 |
jwdonal |
Total number of paths / destination ports: 54 / 54
|
| 639 |
32 |
jwdonal |
-------------------------------------------------------------------------
|
| 640 |
|
|
Offset: 3.390ns (Levels of Logic = 2)
|
| 641 |
|
|
Source: V_C/HSYNCx_C/HSYNCx (FF)
|
| 642 |
|
|
Destination: HSYNCx (PAD)
|
| 643 |
|
|
Source Clock: CLK_100M_PAD rising 0.1X
|
| 644 |
|
|
|
| 645 |
|
|
Data Path: V_C/HSYNCx_C/HSYNCx to HSYNCx
|
| 646 |
|
|
Gate Net
|
| 647 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 648 |
|
|
---------------------------------------- ------------
|
| 649 |
|
|
FDP:C->Q 5 0.370 0.428 HSYNCx (HSYNCx)
|
| 650 |
|
|
end scope: 'HSYNCx_C'
|
| 651 |
|
|
end scope: 'V_C'
|
| 652 |
|
|
OBUF:I->O 2.592 HSYNCx_OBUF (HSYNCx)
|
| 653 |
|
|
----------------------------------------
|
| 654 |
|
|
Total 3.390ns (2.962ns logic, 0.428ns route)
|
| 655 |
|
|
(87.4% logic, 12.6% route)
|
| 656 |
|
|
|
| 657 |
|
|
=========================================================================
|
| 658 |
|
|
Timing constraint: Default path analysis
|
| 659 |
|
|
Total number of paths / destination ports: 18 / 18
|
| 660 |
|
|
-------------------------------------------------------------------------
|
| 661 |
|
|
Delay: 2.924ns (Levels of Logic = 2)
|
| 662 |
38 |
jwdonal |
Source: IMAGE/image_BLUE_data:douta<5> (PAD)
|
| 663 |
32 |
jwdonal |
Destination: B<5> (PAD)
|
| 664 |
|
|
|
| 665 |
38 |
jwdonal |
Data Path: IMAGE/image_BLUE_data:douta<5> to B<5>
|
| 666 |
32 |
jwdonal |
Gate Net
|
| 667 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 668 |
|
|
---------------------------------------- ------------
|
| 669 |
38 |
jwdonal |
image_gen_bram_blue:douta<5> 1 0.000 0.000 image_BLUE_data (B<5>)
|
| 670 |
32 |
jwdonal |
end scope: 'IMAGE'
|
| 671 |
|
|
OBUF:I->O 2.592 B_5_OBUF (B<5>)
|
| 672 |
|
|
----------------------------------------
|
| 673 |
|
|
Total 2.924ns (2.924ns logic, 0.000ns route)
|
| 674 |
|
|
(100.0% logic, 0.0% route)
|
| 675 |
|
|
|
| 676 |
|
|
=========================================================================
|
| 677 |
46 |
jwdonal |
CPU : 14.75 / 15.05 s | Elapsed : 15.00 / 15.00 s
|
| 678 |
32 |
jwdonal |
|
| 679 |
|
|
-->
|
| 680 |
|
|
|
| 681 |
|
|
Total memory usage is 206148 kilobytes
|
| 682 |
|
|
|
| 683 |
|
|
Number of errors : 0 ( 0 filtered)
|
| 684 |
38 |
jwdonal |
Number of warnings : 22 ( 0 filtered)
|
| 685 |
32 |
jwdonal |
Number of infos : 0 ( 0 filtered)
|
| 686 |
|
|
|
