URL https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk

Subversion Repositories lq057q3dc02

[/] [lq057q3dc02/] [trunk/] [implement/] [xst.prj] - Blame information for rev 30

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vhdl    work_vhsic   ../../design/clk_lcd_cyc_cntr.vhd
vhdl    work_vhsic   ../../design/components.vhd
vhdl    work_vhsic   ../../design/enab_control.vhd
vhdl    work_vhsic   ../../design/hsyncx_control.vhd
vhdl    work_vhsic   ../../design/image_gen_bram.vhd
vhdl    work_vhsic   ../../design/lq057q3dc02_top.vhd
vhdl    work_vhsic   ../../design/video_controller.vhd
vhdl    work_vhsic   ../../design/vsyncx_control.vhd
vhdl    work_vhsic   ../../design/dcm_sys_to_lcd.vhd

Line No.	Rev	Author	Line
1	30	jwdonal	`vhdl work_vhsic ../../design/clk_lcd_cyc_cntr.vhd`
2			`vhdl work_vhsic ../../design/components.vhd`
3			`vhdl work_vhsic ../../design/enab_control.vhd`
4			`vhdl work_vhsic ../../design/hsyncx_control.vhd`
5			`vhdl work_vhsic ../../design/image_gen_bram.vhd`
6			`vhdl work_vhsic ../../design/lq057q3dc02_top.vhd`
7			`vhdl work_vhsic ../../design/video_controller.vhd`
8			`vhdl work_vhsic ../../design/vsyncx_control.vhd`
9			`vhdl work_vhsic ../../design/dcm_sys_to_lcd.vhd`

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Subversion Repositories lq057q3dc02

[/] [lq057q3dc02/] [trunk/] [implement/] [xst.prj] - Blame information for rev 30