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[/] [lwrisc/] [tags/] [arelease/] [LWRISC8.v] - Blame information for rev 19

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`define MUXA_W      0
`define MUXA_BD     1
`define MUXB_K      0
`define MUXB_F      1
 
`define BRC_NOP     0
`define BRC_ZERO    1
`define BRC_NZERO   2
 
`define BG_ZERO  1
`define BG_NZERO 2
`define BG_IGN 0
`define BG_NOP 0
 
`define PC_NOP      0
`define PC_BRC      1
`define PC_GOTO     2
`define PC_CALL     3
`define PC_RET      4
 
`define R1_LEN          1
`define R2_LEN          2
`define R3_LEN          3
`define R4_LEN          4
`define R5_LEN          5
`define R8_LEN          8
`define R12_LEN         12
 
`define  ALU_ADD   1
`define  ALU_SUB   2
`define  ALU_AND   3
`define  ALU_OR    4
`define  ALU_XOR   5
`define  ALU_COM   6
`define  ALU_ROR   7
`define  ALU_ROL   8
`define  ALU_SWAP  9
`define  ALU_BSF   10
`define  ALU_BCF   11
`define  ALU_ZERO  12
`define  ALU_DEC   13
`define  ALU_INC   14
`define  ALU_PB    15
`define  ALU_PA    16
module ttoe(
        input [2:0] din,
        output reg [7:0] dout
    );
 
    always @ (*)
    case (din)
        0:dout=1<<0;
        1:dout=1<<1;
        2:dout=1<<2;
        3:dout=1<<3;
        4:dout=1<<4;
        5:dout=1<<5;
        6:dout=1<<6;
        7:dout=1<<7;
    endcase
endmodule
 
 
 
module alu_muxa(
        input ctl,
        output reg [7:0]alu_a,
        input [7:0]w,
        input [7:0]bd
    );
 
    always@(*)
        if (ctl==`MUXA_W)
            alu_a=w;
        else
            alu_a=bd;
endmodule
 
module alu_muxb(
        input ctl,
        output reg [7:0] alu_b,
        input [8:0] k,
        input [7:0] f
    );
 
    always@(*)
        if (ctl==`MUXB_K)
            alu_b=k[7:0];
        else alu_b=f;
 
endmodule
 
 
module w_reg(input [7:0]d,input clk,output reg [7:0] q,input w_wr_en)              ;
always @(posedge clk)   if (w_wr_en) q<=d;
endmodule
 
module pc_gen(
 
        input [10:0]pc_i,
        output reg [10:0] pc_o,
        input [7:0] jmp_addr,
        input [10:0] stack_pc,
        input [4:0]ctl,
        input brc,
        input [7:0]status
 
        );
 
        always @ (*)
                case(ctl)
                        `PC_NOP :pc_o = pc_i+1;
                        `PC_BRC :         if(brc)pc_o = {status[7:6],jmp_addr[7:0]};     //jmp_addr means K
                        `PC_GOTO,
                        `PC_CALL:         pc_o = {status[7:6],jmp_addr[7:0]};
                        `PC_RET:          pc_o = stack_pc;
                        default
                                        pc_o = pc_i+1;
                        endcase
endmodule
 
 
module bg(
        input z ,
        input [1:0]ctl,
        output reg branch);
        always @(*)
                case (ctl)
                        `BG_ZERO :branch =  z;
                        `BG_NZERO :branch = ~z;
                        default branch = 0;
                endcase
        endmodule
 
`if 0
module decoder(
        input [11:0]inst,
        output reg [2:0]pc_ctl,
        output reg [1:0]stack_op,
        output reg alu_muxa,
        output reg alu_muxb,
        output reg [3:0]alu_op,
        output reg men_wr,
        output reg w_wr,
        output reg c_wr,
        output reg z_wr,
        output reg [1:0]bg_op
        );
        always @(inst) begin
        casex (inst) //synopsys parallel_case
                12'b0000_0000_0000:     //REPLACE ID = NOP 
 
                12'b0000_001X_XXXX: //REPLACE ID = MOVWF
 
                12'b0000_0100_0000: //REPLACE ID = CLRW
 
                12'b0000_011X_XXXX: //REPLACE ID = CLRF
 
                12'b0000_100X_XXXX: //REPLACE ID = SUBWF_W
 
                12'b0000_101X_XXXX: //REPLACE ID = SUBWF_F
 
                12'b0000_110X_XXXX: //REPLACE ID = DECF_W
 
                12'b0000_111X_XXXX: //REPLACE ID = DECF_F
 
                12'b0001_000X_XXXX: //REPLACE ID = IORWF _W
 
                12'b0001_001X_XXXX: //REPLACE ID = IORWF_F
 
                12'b0001_010X_XXXX: //REPLACE ID = ANDWF_W
 
                12'b0001_011X_XXXX: //REPLACE ID = ANDWF_F
 
                12'b0001_100X_XXXX: //REPLACE ID = XORWF_W
 
                12'b0001_101X_XXXX: //REPLACE ID = XORWF_F
 
                12'b0001_110X_XXXX: //REPLACE ID = ADDWF_W
 
                12'b0001_111X_XXXX: //REPLACE ID = ADDWF_F
 
                12'b0010_000X_XXXX: //REPLACE ID = MOVF_W
 
                12'b0010_001X_XXXX: //REPLACE ID = MOVF_F
 
                12'b0010_010X_XXXX: //REPLACE ID = COMF_W
 
                12'b0010_011X_XXXX: //REPLACE ID = COMF_F
 
                12'b0010_100X_XXXX: //REPLACE ID = INCF_W
 
                12'b0010_101X_XXXX: //REPLACE ID = INCF_F
 
                12'b0010_110X_XXXX: //REPLACE ID = DECFSZ_W
 
                12'b0010_111X_XXXX: //REPLACE ID = DECFSZ_F
 
                12'b0011_000X_XXXX: //REPLACE ID = RRF_W
 
                12'b0011_001X_XXXX: //REPLACE ID = RRF_F
 
                12'b0011_010X_XXXX: //REPLACE ID = RLF_W
 
                12'b0011_011X_XXXX: //REPLACE ID = RLF_F
 
                12'b0011_100X_XXXX: //REPLACE ID = SWAPF_W
 
                12'b0011_101X_XXXX: //REPLACE ID = SWAPF_F
 
                12'b0011_110X_XXXX: //REPLACE ID = INCFSZ_W
 
                12'b0011_111X_XXXX: //REPLACE ID = INCFSZ_F
 
                12'b0100_XXXX_XXXX: //REPLACE ID = BCF
 
                12'b0101_XXXX_XXXX: //REPLACE ID = BSF
 
                12'b0110_XXXX_XXXX: //REPLACE ID = BTFSC
 
                12'b0111_XXXX_XXXX: //REPLACE ID = BTFSS
 
                12'b0000_0000_0010: //REPLACE ID = OPTION
 
                12'b0000_0000_0011: //REPLACE ID = SLEEP
 
                12'b0000_0000_0100: //REPLACE ID = CLRWDT
 
                12'b0000_0000_0101: //REPLACE ID = TRIS 5
 
                12'b0000_0000_0110: //REPLACE ID = TRIS 6
 
                12'b0000_0000_0111: //REPLACE ID = TRIS 7
 
                12'b1000_XXXX_XXXX: //REPLACE ID = RETLW
 
                12'b1001_XXXX_XXXX: //REPLACE ID = CALL
 
                12'b101X_XXXX_XXXX: //REPLACE ID = GOTO
 
                12'b1100_XXXX_XXXX: //REPLACE ID = MOVLW
 
                12'b1101_XXXX_XXXX: //REPLACE ID = IORLW
 
                12'b1110_XXXX_XXXX: //REPLACE ID = ANDLW
 
                12'b1111_XXXX_XXXX: //REPLACE ID = XORLW                        
 
                default:
 
        endcase
        end
endmodule
`endif
 
module r1_reg_clr_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r1_o<=0;else if(cls)r1_o<=r1_o;else r1_o<=r1_i;endmodule
module r2_reg_clr_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r2_o<=0;else if(cls)r2_o<=r2_o;else r2_o<=r2_i;endmodule
module r3_reg_clr_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r3_o<=0;else if(cls)r3_o<=r3_o;else r3_o<=r3_i;endmodule
module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule
module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule
module r8_reg_clr_cls(input[`R8_LEN-1:0] r8_i,output reg[`R8_LEN-1:0] r8_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r8_o<=0;else if(cls)r8_o<=r8_o;else r8_o<=r8_i;endmodule
module r12_reg_clr_cls(input[`R12_LEN-1:0] r12_i,output reg[`R12_LEN-1:0] r12_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r12_o<=0;else if(cls)r12_o<=r12_o;else r12_o<=r12_i;endmodule
 
`define PUSH 2'B01
`define POP  2'B10
`define NOP  2'B00
 
// A Basic Synchrounous FIFO (4 entries deep)
module sfifo4x11(clk, ctl,din, dout);
    input               clk;
    input               [1:0] ctl;
    input       [10:0]   din;
    output      [10:0]   dout;
    reg [10:0]   stack1, stack2, stack3, stack4;
    assign dout = stack1;
    always @(posedge clk)
    begin
        case (ctl)
            `PUSH       :// PUSH stack
            begin
                stack4 <= stack3;
                stack3 <= stack2;
                stack2 <= stack1;
                stack1 <= din;
            end
            `POP        :// POP stack
            begin
                stack1 <= stack2;
                stack2 <= stack3;
                stack3 <= stack4;
            end
            //  default ://do nothing
        endcase
    end
endmodule
 
 
 
module alu(op,a,b,y,cin,cout,zout);
    input  [4:0] op;     // ALU Operation
    input  [7:0] a;      // 8-bit Input a
    input  [7:0] b;      // 8-bit Input b
    output [7:0] y;      // 8-bit Output
    input               cin;
    output              cout;
    output              zout;
    // Reg declarations for outputs
    reg [7:0]    y;
    // Internal declarations
    reg         addercout; // Carry out straight from the adder itself.
    always @(*) begin
        case (op) // synsys parallel_case
            `ALU_ADD:  {addercout,  y}  = a + b;
            `ALU_SUB:  {addercout,  y}  = b - a; // Carry out is really "borrow"
            `ALU_AND:  {addercout,  y}  = {1'b0, a & b};
            `ALU_ROR:  {addercout,  y}  = {b[0], cin, b[7:1]};
            `ALU_ROL:  {addercout,  y}  = {b[7], b[6:0], cin};
            `ALU_OR:   {addercout,  y}  = {1'b0, a | b};
            `ALU_XOR:  {addercout,  y}  = {1'b0, a ^ b};
            `ALU_COM:  {addercout,  y}  = {1'b0, ~b};
            `ALU_SWAP: {addercout,  y}  = {1'b0, b[3:0], b[7:4]};
            /*below added by liwei*/
            `ALU_BTFSC  {addercout,  y}  = {1'b0, a & b };
            `ALU_BTFSS  {addercout,  y}  = {1'b0, ~a | b };
            `ALU_DEC:                y   =  b - 1;
            `ALU_INC:                y   =  1 + b;
            `ALU_PA :   {addercout,  y}  = {1'b0, a};
            `ALU_PB :   {addercout,  y}  = {1'b0, b};
            `ALU_BSF :  {addercout,  y}  = {1b'0,a | b};
            `ALU_BCF :  {addercout,  y}  = {1'b0,~a & b};
            `ALU_ZERO:  {addercout,  y}  = {1'b0, 8'h00};
            default:     {addercout, y}  = {1'b0, 8'h00};
        endcase
    end
 
    assign  zout = (y == 8'h00);
    assign  cout =  (op == `ALUOP_SUB) ?  ~addercout : addercout;
 
endmodule
 

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Subversion Repositories lwrisc

[/] [lwrisc/] [tags/] [arelease/] [LWRISC8.v] - Blame information for rev 19

Line No.	Rev	Author	Line
1	2	mcupro	`define MUXA_W 0
2			`define MUXA_BD 1
3			`define MUXB_K 0
4			`define MUXB_F 1
5
6			`define BRC_NOP 0
7			`define BRC_ZERO 1
8			`define BRC_NZERO 2
9
10			`define BG_ZERO 1
11			`define BG_NZERO 2
12			`define BG_IGN 0
13			`define BG_NOP 0
14
15			`define PC_NOP 0
16			`define PC_BRC 1
17			`define PC_GOTO 2
18			`define PC_CALL 3
19			`define PC_RET 4
20
21			`define R1_LEN 1
22			`define R2_LEN 2
23			`define R3_LEN 3
24			`define R4_LEN 4
25			`define R5_LEN 5
26			`define R8_LEN 8
27			`define R12_LEN 12
28
29			`define ALU_ADD 1
30			`define ALU_SUB 2
31			`define ALU_AND 3
32			`define ALU_OR 4
33			`define ALU_XOR 5
34			`define ALU_COM 6
35			`define ALU_ROR 7
36			`define ALU_ROL 8
37			`define ALU_SWAP 9
38			`define ALU_BSF 10
39			`define ALU_BCF 11
40			`define ALU_ZERO 12
41			`define ALU_DEC 13
42			`define ALU_INC 14
43			`define ALU_PB 15
44			`define ALU_PA 16
45			`module ttoe(`
46			`input [2:0] din,`
47			`output reg [7:0] dout`
48			`);`
49
50			`always @ (*)`
51			`case (din)`
52			`0:dout=1<<0;`
53			`1:dout=1<<1;`
54			`2:dout=1<<2;`
55			`3:dout=1<<3;`
56			`4:dout=1<<4;`
57			`5:dout=1<<5;`
58			`6:dout=1<<6;`
59			`7:dout=1<<7;`
60			`endcase`
61			`endmodule`
62
63
64
65			`module alu_muxa(`
66			`input ctl,`
67			`output reg [7:0]alu_a,`
68			`input [7:0]w,`
69			`input [7:0]bd`
70			`);`
71
72			`always@(*)`
73			if (ctl==`MUXA_W)
74			`alu_a=w;`
75			`else`
76			`alu_a=bd;`
77			`endmodule`
78
79			`module alu_muxb(`
80			`input ctl,`
81			`output reg [7:0] alu_b,`
82			`input [8:0] k,`
83			`input [7:0] f`
84			`);`
85
86			`always@(*)`
87			if (ctl==`MUXB_K)
88			`alu_b=k[7:0];`
89			`else alu_b=f;`
90
91			`endmodule`
92
93
94			`module w_reg(input [7:0]d,input clk,output reg [7:0] q,input w_wr_en) ;`
95			`always @(posedge clk) if (w_wr_en) q<=d;`
96			`endmodule`
97
98			`module pc_gen(`
99
100			`input [10:0]pc_i,`
101			`output reg [10:0] pc_o,`
102			`input [7:0] jmp_addr,`
103			`input [10:0] stack_pc,`
104			`input [4:0]ctl,`
105			`input brc,`
106			`input [7:0]status`
107
108			`);`
109
110			`always @ (*)`
111			`case(ctl)`
112			`PC_NOP :pc_o = pc_i+1;
113			`PC_BRC : if(brc)pc_o = {status[7:6],jmp_addr[7:0]}; //jmp_addr means K
114			`PC_GOTO,
115			`PC_CALL: pc_o = {status[7:6],jmp_addr[7:0]};
116			`PC_RET: pc_o = stack_pc;
117			`default`
118			`pc_o = pc_i+1;`
119			`endcase`
120			`endmodule`
121
122
123			`module bg(`
124			`input z ,`
125			`input [1:0]ctl,`
126			`output reg branch);`
127			`always @(*)`
128			`case (ctl)`
129			`BG_ZERO :branch = z;
130			`BG_NZERO :branch = ~z;
131			`default branch = 0;`
132			`endcase`
133			`endmodule`
134
135			`if 0
136			`module decoder(`
137			`input [11:0]inst,`
138			`output reg [2:0]pc_ctl,`
139			`output reg [1:0]stack_op,`
140			`output reg alu_muxa,`
141			`output reg alu_muxb,`
142			`output reg [3:0]alu_op,`
143			`output reg men_wr,`
144			`output reg w_wr,`
145			`output reg c_wr,`
146			`output reg z_wr,`
147			`output reg [1:0]bg_op`
148			`);`
149			`always @(inst) begin`
150			`casex (inst) //synopsys parallel_case`
151			`12'b0000_0000_0000: //REPLACE ID = NOP`
152
153			`12'b0000_001X_XXXX: //REPLACE ID = MOVWF`
154
155			`12'b0000_0100_0000: //REPLACE ID = CLRW`
156
157			`12'b0000_011X_XXXX: //REPLACE ID = CLRF`
158
159			`12'b0000_100X_XXXX: //REPLACE ID = SUBWF_W`
160
161			`12'b0000_101X_XXXX: //REPLACE ID = SUBWF_F`
162
163			`12'b0000_110X_XXXX: //REPLACE ID = DECF_W`
164
165			`12'b0000_111X_XXXX: //REPLACE ID = DECF_F`
166
167			`12'b0001_000X_XXXX: //REPLACE ID = IORWF _W`
168
169			`12'b0001_001X_XXXX: //REPLACE ID = IORWF_F`
170
171			`12'b0001_010X_XXXX: //REPLACE ID = ANDWF_W`
172
173			`12'b0001_011X_XXXX: //REPLACE ID = ANDWF_F`
174
175			`12'b0001_100X_XXXX: //REPLACE ID = XORWF_W`
176
177			`12'b0001_101X_XXXX: //REPLACE ID = XORWF_F`
178
179			`12'b0001_110X_XXXX: //REPLACE ID = ADDWF_W`
180
181			`12'b0001_111X_XXXX: //REPLACE ID = ADDWF_F`
182
183			`12'b0010_000X_XXXX: //REPLACE ID = MOVF_W`
184
185			`12'b0010_001X_XXXX: //REPLACE ID = MOVF_F`
186
187			`12'b0010_010X_XXXX: //REPLACE ID = COMF_W`
188
189			`12'b0010_011X_XXXX: //REPLACE ID = COMF_F`
190
191			`12'b0010_100X_XXXX: //REPLACE ID = INCF_W`
192
193			`12'b0010_101X_XXXX: //REPLACE ID = INCF_F`
194
195			`12'b0010_110X_XXXX: //REPLACE ID = DECFSZ_W`
196
197			`12'b0010_111X_XXXX: //REPLACE ID = DECFSZ_F`
198
199			`12'b0011_000X_XXXX: //REPLACE ID = RRF_W`
200
201			`12'b0011_001X_XXXX: //REPLACE ID = RRF_F`
202
203			`12'b0011_010X_XXXX: //REPLACE ID = RLF_W`
204
205			`12'b0011_011X_XXXX: //REPLACE ID = RLF_F`
206
207			`12'b0011_100X_XXXX: //REPLACE ID = SWAPF_W`
208
209			`12'b0011_101X_XXXX: //REPLACE ID = SWAPF_F`
210
211			`12'b0011_110X_XXXX: //REPLACE ID = INCFSZ_W`
212
213			`12'b0011_111X_XXXX: //REPLACE ID = INCFSZ_F`
214
215			`12'b0100_XXXX_XXXX: //REPLACE ID = BCF`
216
217			`12'b0101_XXXX_XXXX: //REPLACE ID = BSF`
218
219			`12'b0110_XXXX_XXXX: //REPLACE ID = BTFSC`
220
221			`12'b0111_XXXX_XXXX: //REPLACE ID = BTFSS`
222
223			`12'b0000_0000_0010: //REPLACE ID = OPTION`
224
225			`12'b0000_0000_0011: //REPLACE ID = SLEEP`
226
227			`12'b0000_0000_0100: //REPLACE ID = CLRWDT`
228
229			`12'b0000_0000_0101: //REPLACE ID = TRIS 5`
230
231			`12'b0000_0000_0110: //REPLACE ID = TRIS 6`
232
233			`12'b0000_0000_0111: //REPLACE ID = TRIS 7`
234
235			`12'b1000_XXXX_XXXX: //REPLACE ID = RETLW`
236
237			`12'b1001_XXXX_XXXX: //REPLACE ID = CALL`
238
239			`12'b101X_XXXX_XXXX: //REPLACE ID = GOTO`
240
241			`12'b1100_XXXX_XXXX: //REPLACE ID = MOVLW`
242
243			`12'b1101_XXXX_XXXX: //REPLACE ID = IORLW`
244
245			`12'b1110_XXXX_XXXX: //REPLACE ID = ANDLW`
246
247			`12'b1111_XXXX_XXXX: //REPLACE ID = XORLW`
248
249			`default:`
250
251			`endcase`
252			`end`
253			`endmodule`
254			`endif
255
256			module r1_reg_clr_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r1_o<=0;else if(cls)r1_o<=r1_o;else r1_o<=r1_i;endmodule
257			module r2_reg_clr_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r2_o<=0;else if(cls)r2_o<=r2_o;else r2_o<=r2_i;endmodule
258			module r3_reg_clr_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r3_o<=0;else if(cls)r3_o<=r3_o;else r3_o<=r3_i;endmodule
259			module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule
260			module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule
261			module r8_reg_clr_cls(input[`R8_LEN-1:0] r8_i,output reg[`R8_LEN-1:0] r8_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r8_o<=0;else if(cls)r8_o<=r8_o;else r8_o<=r8_i;endmodule
262			module r12_reg_clr_cls(input[`R12_LEN-1:0] r12_i,output reg[`R12_LEN-1:0] r12_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r12_o<=0;else if(cls)r12_o<=r12_o;else r12_o<=r12_i;endmodule
263
264			`define PUSH 2'B01
265			`define POP 2'B10
266			`define NOP 2'B00
267
268			`// A Basic Synchrounous FIFO (4 entries deep)`
269			`module sfifo4x11(clk, ctl,din, dout);`
270			`input clk;`
271			`input [1:0] ctl;`
272			`input [10:0] din;`
273			`output [10:0] dout;`
274			`reg [10:0] stack1, stack2, stack3, stack4;`
275			`assign dout = stack1;`
276			`always @(posedge clk)`
277			`begin`
278			`case (ctl)`
279			`PUSH :// PUSH stack
280			`begin`
281			`stack4 <= stack3;`
282			`stack3 <= stack2;`
283			`stack2 <= stack1;`
284			`stack1 <= din;`
285			`end`
286			`POP :// POP stack
287			`begin`
288			`stack1 <= stack2;`
289			`stack2 <= stack3;`
290			`stack3 <= stack4;`
291			`end`
292			`// default ://do nothing`
293			`endcase`
294			`end`
295			`endmodule`
296
297
298
299			`module alu(op,a,b,y,cin,cout,zout);`
300			`input [4:0] op; // ALU Operation`
301			`input [7:0] a; // 8-bit Input a`
302			`input [7:0] b; // 8-bit Input b`
303			`output [7:0] y; // 8-bit Output`
304			`input cin;`
305			`output cout;`
306			`output zout;`
307			`// Reg declarations for outputs`
308			`reg [7:0] y;`
309			`// Internal declarations`
310			`reg addercout; // Carry out straight from the adder itself.`
311			`always @(*) begin`
312			`case (op) // synsys parallel_case`
313			`ALU_ADD: {addercout, y} = a + b;
314			`ALU_SUB: {addercout, y} = b - a; // Carry out is really "borrow"
315			`ALU_AND: {addercout, y} = {1'b0, a & b};
316			`ALU_ROR: {addercout, y} = {b[0], cin, b[7:1]};
317			`ALU_ROL: {addercout, y} = {b[7], b[6:0], cin};
318			`ALU_OR: {addercout, y} = {1'b0, a \| b};
319			`ALU_XOR: {addercout, y} = {1'b0, a ^ b};
320			`ALU_COM: {addercout, y} = {1'b0, ~b};
321			`ALU_SWAP: {addercout, y} = {1'b0, b[3:0], b[7:4]};
322			`/below added by liwei/`
323			`ALU_BTFSC {addercout, y} = {1'b0, a & b };
324			`ALU_BTFSS {addercout, y} = {1'b0, ~a \| b };
325			`ALU_DEC: y = b - 1;
326			`ALU_INC: y = 1 + b;
327			`ALU_PA : {addercout, y} = {1'b0, a};
328			`ALU_PB : {addercout, y} = {1'b0, b};
329			`ALU_BSF : {addercout, y} = {1b'0,a \| b};
330			`ALU_BCF : {addercout, y} = {1'b0,~a & b};
331			`ALU_ZERO: {addercout, y} = {1'b0, 8'h00};
332			`default: {addercout, y} = {1'b0, 8'h00};`
333			`endcase`
334			`end`
335
336			`assign zout = (y == 8'h00);`
337			assign cout = (op == `ALUOP_SUB) ? ~addercout : addercout;
338
339			`endmodule`
340