OpenCores
URL https://opencores.org/ocsvn/lwrisc/lwrisc/trunk

Subversion Repositories lwrisc

[/] [lwrisc/] [trunk/] [BENCH/] [test1/] [sw_led.c] - Blame information for rev 20

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 mcupro
#device PIC16F54
2
 
3
#define    PORT_DATA        *(unsigned char*)0 
4
#define    IN_PORT_ADDR     *(unsigned char*)1 
5
#define    OUT_PORT_ADDR    *(unsigned char*)2 
6
#define    STATUS           *(unsigned char*)3 
7
 
8
#define PORT_ADDR_SEG    0
9
#define PORT_ADDR_LED    8
10
#define PORT_ADDR_SW     9
11
#define PORT_ADDR_KEY    10  
12
#define PORT_ADDR_BEEP   11 
13
 
14
void outport(unsigned  char addr,unsigned char data)
15
{
16
   OUT_PORT_ADDR = addr;
17
   PORT_DATA = data;
18
}
19
 
20
unsigned char inport(unsigned char addr)
21
{
22
   IN_PORT_ADDR = addr;
23
   return PORT_DATA;
24
}
25
 
26
#define GetKey() inport(PORT_ADDR_KEY)
27
#define GetSwich() inport(PORT_ADDR_SW)
28
#define BeepSet(data) outport(PORT_ADDR_BEEP,data)
29
   #define BeepON() outport(PORT_ADDR_BEEP,1)
30
   #define BeepOFF() outport(PORT_ADDR_BEEP,0)
31
#define SetLed(data) outport(PORT_ADDR_LED,data)
32
 
33
#define Seg7Led(addr,data) outport(addr,data)
34
   #define Seg7Led0(data)  outport(0,data)
35
   #define Seg7Led1(data)  outport(1,data)
36
   #define Seg7Led2(data)  outport(2,data)
37
   #define Seg7Led3(data)  outport(3,data)
38
   #define Seg7Led4(data)  outport(4,data)
39
   #define Seg7Led5(data)  outport(5,data)
40
   #define Seg7Led6(data)  outport(6,data)
41
   #define Seg7Led7(data)  outport(7,data)
42
 
43
 
44
void main()
45
{
46
     unsigned char i;
47
      while(1){
48
      i=GetSwich();
49
      SetLed(i);
50
      }
51
 
52
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.