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URL https://opencores.org/ocsvn/lwrisc/lwrisc/trunk

Subversion Repositories lwrisc

[/] [lwrisc/] [trunk/] [QU2/] [db/] [ClaiRISC_core.hier_info] - Blame information for rev 19

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Line No. Rev Author Line
1 10 mcupro 
|ClaiRISC_core
2 
clk => clk_in.PADIO
3 
rst => rst_in.PADIO
4 
wb_din[0] => ~NO_FANOUT~
5 
wb_din[1] => ~NO_FANOUT~
6 
wb_din[2] => ~NO_FANOUT~
7 
wb_din[3] => ~NO_FANOUT~
8 
wb_din[4] => ~NO_FANOUT~
9 
wb_din[5] => ~NO_FANOUT~
10 
wb_din[6] => ~NO_FANOUT~
11 
wb_din[7] => ~NO_FANOUT~
12 
in0[0] => in0_in_0_.PADIO
13 
in0[1] => in0_in_1_.PADIO
14 
in0[2] => in0_in_2_.PADIO
15 
in0[3] => in0_in_3_.PADIO
16 
in0[4] => in0_in_4_.PADIO
17 
in0[5] => in0_in_5_.PADIO
18 
in0[6] => in0_in_6_.PADIO
19 
in0[7] => in0_in_7_.PADIO
20 
in1[0] => in1_in_0_.PADIO
21 
in1[1] => in1_in_1_.PADIO
22 
in1[2] => in1_in_2_.PADIO
23 
in1[3] => in1_in_3_.PADIO
24 
in1[4] => in1_in_4_.PADIO
25 
in1[5] => in1_in_5_.PADIO
26 
in1[6] => in1_in_6_.PADIO
27 
in1[7] => in1_in_7_.PADIO
28 
out0[0] <= out0_out_0_.PADIO
29 
out0[1] <= out0_out_1_.PADIO
30 
out0[2] <= out0_out_2_.PADIO
31 
out0[3] <= out0_out_3_.PADIO
32 
out0[4] <= out0_out_4_.PADIO
33 
out0[5] <= out0_out_5_.PADIO
34 
out0[6] <= out0_out_6_.PADIO
35 
out0[7] <= out0_out_7_.PADIO
36 
out1[0] <= out1_out_0_.PADIO
37 
out1[1] <= out1_out_1_.PADIO
38 
out1[2] <= out1_out_2_.PADIO
39 
out1[3] <= out1_out_3_.PADIO
40 
out1[4] <= out1_out_4_.PADIO
41 
out1[5] <= out1_out_5_.PADIO
42 
out1[6] <= out1_out_6_.PADIO
43 
out1[7] <= out1_out_7_.PADIO
44 
 
45 
 
46 
|ClaiRISC_core|wb_mem_man:mem_man
47 
w_ins_0 => ram128x8:i_reg_file.w_ins_0
48 
w_ins_1 => ram128x8:i_reg_file.w_ins_1
49 
w_ins_2 => ram128x8:i_reg_file.w_ins_2
50 
w_ins_3 => ram128x8:i_reg_file.w_ins_3
51 
w_ins_4 => ram128x8:i_reg_file.w_ins_4
52 
out0_0 <= out0_0__Z.REGOUT
53 
out0_1 <= out0_1__Z.REGOUT
54 
out0_2 <= out0_2__Z.REGOUT
55 
out0_3 <= out0_3__Z.REGOUT
56 
out0_4 <= out0_4__Z.REGOUT
57 
out0_5 <= out0_5__Z.REGOUT
58 
out0_6 <= out0_6__Z.REGOUT
59 
out0_7 <= out0_7__Z.REGOUT
60 
out1_0 <= out1_0__Z.REGOUT
61 
out1_1 <= out1_1__Z.REGOUT
62 
out1_2 <= out1_2__Z.REGOUT
63 
out1_3 <= out1_3__Z.REGOUT
64 
out1_4 <= out1_4__Z.REGOUT
65 
out1_5 <= out1_5__Z.REGOUT
66 
out1_6 <= out1_6__Z.REGOUT
67 
out1_7 <= out1_7__Z.REGOUT
68 
w_alu_res_1_1_0 => status_3__Z.DATAD
69 
w_alu_res_1_1_0 => ram128x8:i_reg_file.w_alu_res_1_1_0
70 
w_alu_res_1_3_0 => status_4__Z.DATAD
71 
w_alu_res_1_3_0 => ram128x8:i_reg_file.w_alu_res_1_3_0
72 
w_alu_res_1_6_0 => status_5__Z.DATAD
73 
w_alu_res_1_6_0 => ram128x8:i_reg_file.w_alu_res_1_6_0
74 
w_alu_res_1_6_1 => status_6__Z.DATAD
75 
w_alu_res_1_6_1 => ram128x8:i_reg_file.w_alu_res_1_6_1
76 
w_alu_res_1_6_2 => status_7__Z.DATAD
77 
w_alu_res_1_6_2 => ram128x8:i_reg_file.w_alu_res_1_6_2
78 
in0_c_0 => reg_in0_0__Z.DATAD
79 
in0_c_1 => reg_in0_1__Z.DATAD
80 
in0_c_2 => reg_in0_2__Z.DATAD
81 
in0_c_3 => reg_in0_3__Z.DATAD
82 
in0_c_4 => reg_in0_4__Z.DATAD
83 
in0_c_5 => reg_in0_5__Z.DATAD
84 
in0_c_6 => reg_in0_6__Z.DATAD
85 
in0_c_7 => reg_in0_7__Z.DATAD
86 
w_alu_res_1_0_1 => status_1__Z.DATAD
87 
w_alu_res_1_0_1 => ram128x8:i_reg_file.w_alu_res_1_0_1
88 
w_alu_res_1_0_2 => status_2__Z.DATAC
89 
w_alu_res_1_0_2 => ram128x8:i_reg_file.w_alu_res_1_0_2
90 
w_alu_res_1_0_0 <= din_r_0__Z.COMBOUT
91 
w_alu_res_1_0_a2_1_0 => din_r_0__Z.DATAD
92 
w_alu_res_1_0_a2_1_0 => out1_0__Z.DATAC
93 
w_alu_res_1_0_a2_1_0 => out0_0__Z.DATAC
94 
w_alu_res_1_0_a2_1_0 => fsr_0__Z.DATAC
95 
w_alu_res_1_0_a2_1_1 => din_r_1__Z.DATAC
96 
w_alu_res_1_0_a2_1_1 => out1_1__Z.DATAC
97 
w_alu_res_1_0_a2_1_1 => out0_1__Z.DATAC
98 
w_alu_res_1_0_a2_1_1 => fsr_1__Z.DATAC
99 
dout_4 <= dout_4_.COMBOUT
100 
dout_7 <= dout_7_.COMBOUT
101 
dout_5 <= dout_5_.COMBOUT
102 
dout_3 <= dout_3_.COMBOUT
103 
dout_2 <= dout_2_.COMBOUT
104 
dout_6 <= dout_6_.COMBOUT
105 
dout_0 <= dout_0_.COMBOUT
106 
dout_1 <= dout_1_.COMBOUT
107 
w_alu_res_1_0_a2_2_0_0 => din_r_0__Z.DATAA
108 
w_alu_res_1_0_a2_2_0_0 => out1_0__Z.DATAA
109 
w_alu_res_1_0_a2_2_0_0 => out0_0__Z.DATAA
110 
w_alu_res_1_0_a2_2_0_0 => fsr_0__Z.DATAA
111 
w_alu_res_1_0_a2_2_0_1 => din_r_1__Z.DATAA
112 
w_alu_res_1_0_a2_2_0_1 => out1_1__Z.DATAA
113 
w_alu_res_1_0_a2_2_0_1 => out0_1__Z.DATAA
114 
w_alu_res_1_0_a2_2_0_1 => fsr_1__Z.DATAA
115 
w_alu_res_1_0_0_0 => din_r_2__Z.DATAD
116 
w_alu_res_1_0_0_0 => out1_2__Z.DATAD
117 
w_alu_res_1_0_0_0 => out0_2__Z.DATAD
118 
w_alu_res_1_0_0_0 => fsr_2__Z.DATAD
119 
w_alu_res_1_0_a2_0_0 => din_r_0__Z.DATAC
120 
w_alu_res_1_0_a2_0_0 => out1_0__Z.DATAD
121 
w_alu_res_1_0_a2_0_0 => out0_0__Z.DATAD
122 
w_alu_res_1_0_a2_0_0 => fsr_0__Z.DATAD
123 
w_alu_res_1_0_a2_0_1 => din_r_1__Z.DATAD
124 
w_alu_res_1_0_a2_0_1 => out1_1__Z.DATAD
125 
w_alu_res_1_0_a2_0_1 => out0_1__Z.DATAD
126 
w_alu_res_1_0_a2_0_1 => fsr_1__Z.DATAD
127 
w_alu_res_1_0_a2_0_2 => din_r_2__Z.DATAC
128 
w_alu_res_1_0_a2_0_2 => out1_2__Z.DATAC
129 
w_alu_res_1_0_a2_0_2 => out0_2__Z.DATAC
130 
w_alu_res_1_0_a2_0_2 => fsr_2__Z.DATAC
131 
w_alu_res_1_1_a_0 => din_r_3__Z.DATAD
132 
w_alu_res_1_1_a_0 => out1_3__Z.DATAD
133 
w_alu_res_1_1_a_0 => out0_3__Z.DATAD
134 
w_alu_res_1_1_a_0 => fsr_3__Z.DATAD
135 
w_alu_res_1_1_1_0 => din_r_3__Z.DATAC
136 
w_alu_res_1_1_1_0 => out1_3__Z.DATAC
137 
w_alu_res_1_1_1_0 => out0_3__Z.DATAC
138 
w_alu_res_1_1_1_0 => fsr_3__Z.DATAC
139 
w_alu_res_1_3_a_0 => din_r_4__Z.DATAD
140 
w_alu_res_1_3_a_0 => out1_4__Z.DATAD
141 
w_alu_res_1_3_a_0 => out0_4__Z.DATAD
142 
w_alu_res_1_3_a_0 => fsr_4__Z.DATAD
143 
w_alu_res_1_3_1_0 => din_r_4__Z.DATAC
144 
w_alu_res_1_3_1_0 => out1_4__Z.DATAC
145 
w_alu_res_1_3_1_0 => out0_4__Z.DATAC
146 
w_alu_res_1_3_1_0 => fsr_4__Z.DATAC
147 
w_alu_res_1_6_a_2 => out1_7__Z.DATAD
148 
w_alu_res_1_6_a_2 => out0_7__Z.DATAD
149 
w_alu_res_1_6_a_2 => fsr_7__Z.DATAD
150 
w_alu_res_1_6_a_0 => din_r_5__Z.DATAD
151 
w_alu_res_1_6_a_0 => out1_5__Z.DATAD
152 
w_alu_res_1_6_a_0 => out0_5__Z.DATAD
153 
w_alu_res_1_6_a_0 => fsr_5__Z.DATAD
154 
w_alu_res_1_6_a_1 => din_r_6__Z.DATAD
155 
w_alu_res_1_6_a_1 => out1_6__Z.DATAD
156 
w_alu_res_1_6_a_1 => out0_6__Z.DATAD
157 
w_alu_res_1_6_a_1 => fsr_6__Z.DATAD
158 
w_alu_res_1_6_1_2 => out1_7__Z.DATAC
159 
w_alu_res_1_6_1_2 => out0_7__Z.DATAC
160 
w_alu_res_1_6_1_2 => fsr_7__Z.DATAC
161 
w_alu_res_1_6_1_0 => din_r_5__Z.DATAC
162 
w_alu_res_1_6_1_0 => out1_5__Z.DATAC
163 
w_alu_res_1_6_1_0 => out0_5__Z.DATAC
164 
w_alu_res_1_6_1_0 => fsr_5__Z.DATAC
165 
w_alu_res_1_6_1_1 => din_r_6__Z.DATAC
166 
w_alu_res_1_6_1_1 => out1_6__Z.DATAC
167 
w_alu_res_1_6_1_1 => out0_6__Z.DATAC
168 
w_alu_res_1_6_1_1 => fsr_6__Z.DATAC
169 
in1_c_7 => reg_in1_7__Z.DATAC
170 
in1_c_6 => reg_in1_6__Z.DATAC
171 
in1_c_5 => reg_in1_5__Z.DATAC
172 
in1_c_4 => reg_in1_4__Z.DATAC
173 
in1_c_3 => reg_in1_3__Z.DATAC
174 
in1_c_2 => reg_in1_2__Z.DATAC
175 
in1_c_1 => reg_in1_1__Z.DATAC
176 
in1_c_0 => reg_in1_0__Z.DATAC
177 
w_ek_r_4 => wr_addr_r_3__Z.DATAD
178 
w_ek_r_4 => wr_addr_r_4__Z.DATAD
179 
w_ek_r_4 => dout_sn_m5_e_0_a2_a_cZ.DATAB
180 
w_ek_r_4 => dout10_cZ.DATAA
181 
w_ek_r_4 => dout8_cZ.DATAA
182 
w_ek_r_4 => dout_sn_m6_0_a2_cZ.DATAA
183 
w_ek_r_4 => write_out0_0_a3_0_o2_cZ.DATAC
184 
w_ek_r_4 => ram128x8:i_reg_file.w_ek_r_4
185 
w_ek_r_3 => wr_addr_r_3__Z.DATAC
186 
w_ek_r_3 => wr_addr_r_3__Z.DATAB
187 
w_ek_r_3 => dout_sn_m5_e_0_a2_cZ.DATAA
188 
w_ek_r_3 => write_out0_0_a3_0_o2_cZ.DATAB
189 
w_ek_r_3 => dout7_1_cZ.DATAA
190 
w_ek_r_3 => dout10_2_cZ.DATAC
191 
w_ek_r_3 => ram128x8:i_reg_file.w_ek_r_3
192 
w_ek_r_2 => wr_addr_r_2__Z.DATAC
193 
w_ek_r_2 => wr_addr_r_2__Z.DATAA
194 
w_ek_r_2 => status_0_0_0_a2_1_6_.DATAB
195 
w_ek_r_2 => status_0_0_0_a2_2_6_.DATAB
196 
w_ek_r_2 => dout_sn_m5_e_0_a2_cZ.DATAB
197 
w_ek_r_2 => dout7_1_cZ.DATAC
198 
w_ek_r_2 => dout10_2_cZ.DATAD
199 
w_ek_r_2 => ram128x8:i_reg_file.w_ek_r_2
200 
w_ek_r_1 => wr_addr_r_1__Z.DATAC
201 
w_ek_r_1 => wr_addr_r_1__Z.DATAA
202 
w_ek_r_1 => dout_sn_m5_e_0_a2_a_cZ.DATAC
203 
w_ek_r_1 => dout10_cZ.DATAB
204 
w_ek_r_1 => dout8_cZ.DATAB
205 
w_ek_r_1 => write_out0_0_a3_0_o2_cZ.DATAD
206 
w_ek_r_1 => dout7_1_cZ.DATAB
207 
w_ek_r_1 => ram128x8:i_reg_file.w_ek_r_1
208 
w_ek_r_0 => wr_en_r_Z.DATAB
209 
w_ek_r_0 => wr_addr_r_0__Z.DATAD
210 
w_ek_r_0 => status_0_0_0_a2_1_6_.DATAC
211 
w_ek_r_0 => status_0_0_0_a2_2_6_.DATAC
212 
w_ek_r_0 => dout_sn_m5_e_0_a2_a_cZ.DATAD
213 
w_ek_r_0 => dout10_cZ.DATAC
214 
w_ek_r_0 => dout8_cZ.DATAC
215 
w_ek_r_0 => dout7_1_cZ.DATAD
216 
w_ek_r_0 => ram128x8:i_reg_file.w_ek_r_0
217 
write_out0_0_a3_0_o2 <= write_out0_0_a3_0_o2_cZ.COMBOUT
218 
rst_c => status_0_0_0_a2_1_6_.DATAA
219 
rst_c => status_0_0_0_a2_2_6_.DATAA
220 
un11_w_alu_res_carry_7 => status_6_a_0_.DATAD
221 
w_c_2mem_i_a2_0_0 => status_6_a_0_.DATAB
222 
N_796 => status_6_0_.DATAD
223 
w_c_wr_r => status_6_0_.DATAB
224 
w_z_0_a2 => status_0_i_0_a_2_.DATAD
225 
w_z_wr_r => status_0_i_0_a_2_.DATAC
226 
G_287 => fsr_7__Z.ENA
227 
G_287 => fsr_6__Z.ENA
228 
G_287 => fsr_5__Z.ENA
229 
G_287 => fsr_4__Z.ENA
230 
G_287 => fsr_3__Z.ENA
231 
G_287 => fsr_2__Z.ENA
232 
G_287 => fsr_1__Z.ENA
233 
G_287 => fsr_0__Z.ENA
234 
G_279 => out0_7__Z.ENA
235 
G_279 => out0_6__Z.ENA
236 
G_279 => out0_5__Z.ENA
237 
G_279 => out0_4__Z.ENA
238 
G_279 => out0_3__Z.ENA
239 
G_279 => out0_2__Z.ENA
240 
G_279 => out0_1__Z.ENA
241 
G_279 => out0_0__Z.ENA
242 
G_271 => out1_7__Z.ENA
243 
G_271 => out1_6__Z.ENA
244 
G_271 => out1_5__Z.ENA
245 
G_271 => out1_4__Z.ENA
246 
G_271 => out1_3__Z.ENA
247 
G_271 => out1_2__Z.ENA
248 
G_271 => out1_1__Z.ENA
249 
G_271 => out1_0__Z.ENA
250 
rst_i_i => rst_i_i_i.IN0
251 
un11_w_alu_res_add7 => out1_7__Z.DATAB
252 
un11_w_alu_res_add7 => out0_7__Z.DATAB
253 
un11_w_alu_res_add7 => fsr_7__Z.DATAB
254 
un11_w_alu_res_add3 => din_r_3__Z.DATAB
255 
un11_w_alu_res_add3 => out1_3__Z.DATAB
256 
un11_w_alu_res_add3 => out0_3__Z.DATAB
257 
un11_w_alu_res_add3 => fsr_3__Z.DATAB
258 
un11_w_alu_res_add4 => din_r_4__Z.DATAB
259 
un11_w_alu_res_add4 => out1_4__Z.DATAB
260 
un11_w_alu_res_add4 => out0_4__Z.DATAB
261 
un11_w_alu_res_add4 => fsr_4__Z.DATAB
262 
un11_w_alu_res_add5 => din_r_5__Z.DATAB
263 
un11_w_alu_res_add5 => out1_5__Z.DATAB
264 
un11_w_alu_res_add5 => out0_5__Z.DATAB
265 
un11_w_alu_res_add5 => fsr_5__Z.DATAB
266 
un11_w_alu_res_add6 => din_r_6__Z.DATAB
267 
un11_w_alu_res_add6 => out1_6__Z.DATAB
268 
un11_w_alu_res_add6 => out0_6__Z.DATAB
269 
un11_w_alu_res_add6 => fsr_6__Z.DATAB
270 
w_c_2mem_i_a3 => din_r_6__Z.DATAA
271 
w_c_2mem_i_a3 => din_r_5__Z.DATAA
272 
w_c_2mem_i_a3 => din_r_4__Z.DATAA
273 
w_c_2mem_i_a3 => din_r_3__Z.DATAA
274 
w_c_2mem_i_a3 => out1_7__Z.DATAA
275 
w_c_2mem_i_a3 => out1_6__Z.DATAA
276 
w_c_2mem_i_a3 => out1_5__Z.DATAA
277 
w_c_2mem_i_a3 => out1_4__Z.DATAA
278 
w_c_2mem_i_a3 => out1_3__Z.DATAA
279 
w_c_2mem_i_a3 => out0_7__Z.DATAA
280 
w_c_2mem_i_a3 => out0_6__Z.DATAA
281 
w_c_2mem_i_a3 => out0_5__Z.DATAA
282 
w_c_2mem_i_a3 => out0_4__Z.DATAA
283 
w_c_2mem_i_a3 => out0_3__Z.DATAA
284 
w_c_2mem_i_a3 => fsr_7__Z.DATAA
285 
w_c_2mem_i_a3 => fsr_6__Z.DATAA
286 
w_c_2mem_i_a3 => fsr_5__Z.DATAA
287 
w_c_2mem_i_a3 => fsr_4__Z.DATAA
288 
w_c_2mem_i_a3 => fsr_3__Z.DATAA
289 
w_c_2mem_i_a3 => status_6_a_0_.DATAC
290 
w_mem_wr_r => wr_en_r_Z.DATAC
291 
w_mem_wr_r => write_out0_0_a3_0_o2_cZ.DATAA
292 
w_mem_wr_r => ram128x8:i_reg_file.w_mem_wr_r
293 
clk_c => wr_en_r_Z.CLK
294 
clk_c => reg_in1_0__Z.CLK
295 
clk_c => reg_in1_1__Z.CLK
296 
clk_c => reg_in1_2__Z.CLK
297 
clk_c => reg_in1_3__Z.CLK
298 
clk_c => reg_in1_4__Z.CLK
299 
clk_c => reg_in1_5__Z.CLK
300 
clk_c => reg_in1_6__Z.CLK
301 
clk_c => reg_in1_7__Z.CLK
302 
clk_c => wr_addr_r_1__Z.CLK
303 
clk_c => wr_addr_r_2__Z.CLK
304 
clk_c => wr_addr_r_3__Z.CLK
305 
clk_c => din_r_6__Z.CLK
306 
clk_c => din_r_5__Z.CLK
307 
clk_c => din_r_4__Z.CLK
308 
clk_c => din_r_3__Z.CLK
309 
clk_c => din_r_2__Z.CLK
310 
clk_c => din_r_1__Z.CLK
311 
clk_c => din_r_0__Z.CLK
312 
clk_c => wr_addr_r_4__Z.CLK
313 
clk_c => wr_addr_r_0__Z.CLK
314 
clk_c => reg_in0_7__Z.CLK
315 
clk_c => reg_in0_6__Z.CLK
316 
clk_c => reg_in0_5__Z.CLK
317 
clk_c => reg_in0_4__Z.CLK
318 
clk_c => reg_in0_3__Z.CLK
319 
clk_c => reg_in0_2__Z.CLK
320 
clk_c => reg_in0_1__Z.CLK
321 
clk_c => reg_in0_0__Z.CLK
322 
clk_c => status_7__Z.CLK
323 
clk_c => status_6__Z.CLK
324 
clk_c => status_5__Z.CLK
325 
clk_c => status_4__Z.CLK
326 
clk_c => status_3__Z.CLK
327 
clk_c => status_2__Z.CLK
328 
clk_c => status_1__Z.CLK
329 
clk_c => status_0__Z.CLK
330 
clk_c => out1_7__Z.CLK
331 
clk_c => out1_6__Z.CLK
332 
clk_c => out1_5__Z.CLK
333 
clk_c => out1_4__Z.CLK
334 
clk_c => out1_3__Z.CLK
335 
clk_c => out1_2__Z.CLK
336 
clk_c => out1_1__Z.CLK
337 
clk_c => out1_0__Z.CLK
338 
clk_c => out0_7__Z.CLK
339 
clk_c => out0_6__Z.CLK
340 
clk_c => out0_5__Z.CLK
341 
clk_c => out0_4__Z.CLK
342 
clk_c => out0_3__Z.CLK
343 
clk_c => out0_2__Z.CLK
344 
clk_c => out0_1__Z.CLK
345 
clk_c => out0_0__Z.CLK
346 
clk_c => fsr_7__Z.CLK
347 
clk_c => fsr_6__Z.CLK
348 
clk_c => fsr_5__Z.CLK
349 
clk_c => fsr_4__Z.CLK
350 
clk_c => fsr_3__Z.CLK
351 
clk_c => fsr_2__Z.CLK
352 
clk_c => fsr_1__Z.CLK
353 
clk_c => fsr_0__Z.CLK
354 
clk_c => ram128x8:i_reg_file.clk_c
355 
 
356 
 
357 
|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file
358 
alt_ram_q_7 <= altsyncram_Z1:altsyncram_component_Z.q_b[7]
359 
alt_ram_q_6 <= altsyncram_Z1:altsyncram_component_Z.q_b[6]
360 
alt_ram_q_5 <= altsyncram_Z1:altsyncram_component_Z.q_b[5]
361 
alt_ram_q_4 <= altsyncram_Z1:altsyncram_component_Z.q_b[4]
362 
alt_ram_q_3 <= altsyncram_Z1:altsyncram_component_Z.q_b[3]
363 
alt_ram_q_2 <= altsyncram_Z1:altsyncram_component_Z.q_b[2]
364 
alt_ram_q_1 <= altsyncram_Z1:altsyncram_component_Z.q_b[1]
365 
alt_ram_q_0 <= altsyncram_Z1:altsyncram_component_Z.q_b[0]
366 
w_ins_4 => altsyncram_Z1:altsyncram_component_Z.address_b[4]
367 
w_ins_3 => altsyncram_Z1:altsyncram_component_Z.address_b[3]
368 
w_ins_2 => altsyncram_Z1:altsyncram_component_Z.address_b[2]
369 
w_ins_1 => altsyncram_Z1:altsyncram_component_Z.address_b[1]
370 
w_ins_0 => altsyncram_Z1:altsyncram_component_Z.address_b[0]
371 
fsr_1 => altsyncram_Z1:altsyncram_component_Z.address_b[6]
372 
fsr_1 => altsyncram_Z1:altsyncram_component_Z.address_a[6]
373 
fsr_0 => altsyncram_Z1:altsyncram_component_Z.address_b[5]
374 
fsr_0 => altsyncram_Z1:altsyncram_component_Z.address_a[5]
375 
w_ek_r_4 => altsyncram_Z1:altsyncram_component_Z.address_a[4]
376 
w_ek_r_3 => altsyncram_Z1:altsyncram_component_Z.address_a[3]
377 
w_ek_r_2 => altsyncram_Z1:altsyncram_component_Z.address_a[2]
378 
w_ek_r_1 => altsyncram_Z1:altsyncram_component_Z.address_a[1]
379 
w_ek_r_0 => altsyncram_Z1:altsyncram_component_Z.address_a[0]
380 
w_alu_res_1_6_2 => altsyncram_Z1:altsyncram_component_Z.data_a[7]
381 
w_alu_res_1_6_1 => altsyncram_Z1:altsyncram_component_Z.data_a[6]
382 
w_alu_res_1_6_0 => altsyncram_Z1:altsyncram_component_Z.data_a[5]
383 
w_alu_res_1_3_0 => altsyncram_Z1:altsyncram_component_Z.data_a[4]
384 
w_alu_res_1_1_0 => altsyncram_Z1:altsyncram_component_Z.data_a[3]
385 
w_alu_res_1_0_2 => altsyncram_Z1:altsyncram_component_Z.data_a[2]
386 
w_alu_res_1_0_1 => altsyncram_Z1:altsyncram_component_Z.data_a[1]
387 
w_alu_res_1_0_0 => altsyncram_Z1:altsyncram_component_Z.data_a[0]
388 
clk_c => altsyncram_Z1:altsyncram_component_Z.clock0
389 
w_mem_wr_r => altsyncram_Z1:altsyncram_component_Z.wren_a
390 
 
391 
 
392 
|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z
393 
wren_a => altsyncram:U1.wren_a
394 
data_a[0] => altsyncram:U1.data_a
395 
data_a[1] => altsyncram:U1.data_a
396 
data_a[2] => altsyncram:U1.data_a
397 
data_a[3] => altsyncram:U1.data_a
398 
data_a[4] => altsyncram:U1.data_a
399 
data_a[5] => altsyncram:U1.data_a
400 
data_a[6] => altsyncram:U1.data_a
401 
data_a[7] => altsyncram:U1.data_a
402 
address_a[0] => altsyncram:U1.address_a
403 
address_a[1] => altsyncram:U1.address_a
404 
address_a[2] => altsyncram:U1.address_a
405 
address_a[3] => altsyncram:U1.address_a
406 
address_a[4] => altsyncram:U1.address_a
407 
address_a[5] => altsyncram:U1.address_a
408 
address_a[6] => altsyncram:U1.address_a
409 
address_b[0] => altsyncram:U1.address_b
410 
address_b[1] => altsyncram:U1.address_b
411 
address_b[2] => altsyncram:U1.address_b
412 
address_b[3] => altsyncram:U1.address_b
413 
address_b[4] => altsyncram:U1.address_b
414 
address_b[5] => altsyncram:U1.address_b
415 
address_b[6] => altsyncram:U1.address_b
416 
clock0 => altsyncram:U1.clock0
417 
q_a[0] <= altsyncram:U1.q_a
418 
q_a[1] <= altsyncram:U1.q_a
419 
q_a[2] <= altsyncram:U1.q_a
420 
q_a[3] <= altsyncram:U1.q_a
421 
q_a[4] <= altsyncram:U1.q_a
422 
q_a[5] <= altsyncram:U1.q_a
423 
q_a[6] <= altsyncram:U1.q_a
424 
q_a[7] <= altsyncram:U1.q_a
425 
q_b[0] <= altsyncram:U1.q_b
426 
q_b[1] <= altsyncram:U1.q_b
427 
q_b[2] <= altsyncram:U1.q_b
428 
q_b[3] <= altsyncram:U1.q_b
429 
q_b[4] <= altsyncram:U1.q_b
430 
q_b[5] <= altsyncram:U1.q_b
431 
q_b[6] <= altsyncram:U1.q_b
432 
q_b[7] <= altsyncram:U1.q_b
433 
 
434 
 
435 
|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z|altsyncram:U1
436 
wren_a => altsyncram_hg91:auto_generated.wren_a
437 
wren_b => ~NO_FANOUT~
438 
rden_b => ~NO_FANOUT~
439 
data_a[0] => altsyncram_hg91:auto_generated.data_a[0]
440 
data_a[1] => altsyncram_hg91:auto_generated.data_a[1]
441 
data_a[2] => altsyncram_hg91:auto_generated.data_a[2]
442 
data_a[3] => altsyncram_hg91:auto_generated.data_a[3]
443 
data_a[4] => altsyncram_hg91:auto_generated.data_a[4]
444 
data_a[5] => altsyncram_hg91:auto_generated.data_a[5]
445 
data_a[6] => altsyncram_hg91:auto_generated.data_a[6]
446 
data_a[7] => altsyncram_hg91:auto_generated.data_a[7]
447 
data_b[0] => ~NO_FANOUT~
448 
data_b[1] => ~NO_FANOUT~
449 
data_b[2] => ~NO_FANOUT~
450 
data_b[3] => ~NO_FANOUT~
451 
data_b[4] => ~NO_FANOUT~
452 
data_b[5] => ~NO_FANOUT~
453 
data_b[6] => ~NO_FANOUT~
454 
data_b[7] => ~NO_FANOUT~
455 
address_a[0] => altsyncram_hg91:auto_generated.address_a[0]
456 
address_a[1] => altsyncram_hg91:auto_generated.address_a[1]
457 
address_a[2] => altsyncram_hg91:auto_generated.address_a[2]
458 
address_a[3] => altsyncram_hg91:auto_generated.address_a[3]
459 
address_a[4] => altsyncram_hg91:auto_generated.address_a[4]
460 
address_a[5] => altsyncram_hg91:auto_generated.address_a[5]
461 
address_a[6] => altsyncram_hg91:auto_generated.address_a[6]
462 
address_b[0] => altsyncram_hg91:auto_generated.address_b[0]
463 
address_b[1] => altsyncram_hg91:auto_generated.address_b[1]
464 
address_b[2] => altsyncram_hg91:auto_generated.address_b[2]
465 
address_b[3] => altsyncram_hg91:auto_generated.address_b[3]
466 
address_b[4] => altsyncram_hg91:auto_generated.address_b[4]
467 
address_b[5] => altsyncram_hg91:auto_generated.address_b[5]
468 
address_b[6] => altsyncram_hg91:auto_generated.address_b[6]
469 
addressstall_a => ~NO_FANOUT~
470 
addressstall_b => ~NO_FANOUT~
471 
clock0 => altsyncram_hg91:auto_generated.clock0
472 
clock1 => ~NO_FANOUT~
473 
clocken0 => ~NO_FANOUT~
474 
clocken1 => ~NO_FANOUT~
475 
aclr0 => ~NO_FANOUT~
476 
aclr1 => ~NO_FANOUT~
477 
byteena_a[0] => ~NO_FANOUT~
478 
byteena_b[0] => ~NO_FANOUT~
479 
q_a[0] <= altsyncram_hg91:auto_generated.q_a[0]
480 
q_a[1] <= altsyncram_hg91:auto_generated.q_a[1]
481 
q_a[2] <= altsyncram_hg91:auto_generated.q_a[2]
482 
q_a[3] <= altsyncram_hg91:auto_generated.q_a[3]
483 
q_a[4] <= altsyncram_hg91:auto_generated.q_a[4]
484 
q_a[5] <= altsyncram_hg91:auto_generated.q_a[5]
485 
q_a[6] <= altsyncram_hg91:auto_generated.q_a[6]
486 
q_a[7] <= altsyncram_hg91:auto_generated.q_a[7]
487 
q_b[0] <= altsyncram_hg91:auto_generated.q_b[0]
488 
q_b[1] <= altsyncram_hg91:auto_generated.q_b[1]
489 
q_b[2] <= altsyncram_hg91:auto_generated.q_b[2]
490 
q_b[3] <= altsyncram_hg91:auto_generated.q_b[3]
491 
q_b[4] <= altsyncram_hg91:auto_generated.q_b[4]
492 
q_b[5] <= altsyncram_hg91:auto_generated.q_b[5]
493 
q_b[6] <= altsyncram_hg91:auto_generated.q_b[6]
494 
q_b[7] <= altsyncram_hg91:auto_generated.q_b[7]
495 
 
496 
 
497 
|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z|altsyncram:U1|altsyncram_hg91:auto_generated
498 
address_a[0] => ram_block1a0.PORTAADDR
499 
address_a[0] => ram_block1a1.PORTAADDR
500 
address_a[0] => ram_block1a2.PORTAADDR
501 
address_a[0] => ram_block1a3.PORTAADDR
502 
address_a[0] => ram_block1a4.PORTAADDR
503 
address_a[0] => ram_block1a5.PORTAADDR
504 
address_a[0] => ram_block1a6.PORTAADDR
505 
address_a[0] => ram_block1a7.PORTAADDR
506 
address_a[1] => ram_block1a0.PORTAADDR1
507 
address_a[1] => ram_block1a1.PORTAADDR1
508 
address_a[1] => ram_block1a2.PORTAADDR1
509 
address_a[1] => ram_block1a3.PORTAADDR1
510 
address_a[1] => ram_block1a4.PORTAADDR1
511 
address_a[1] => ram_block1a5.PORTAADDR1
512 
address_a[1] => ram_block1a6.PORTAADDR1
513 
address_a[1] => ram_block1a7.PORTAADDR1
514 
address_a[2] => ram_block1a0.PORTAADDR2
515 
address_a[2] => ram_block1a1.PORTAADDR2
516 
address_a[2] => ram_block1a2.PORTAADDR2
517 
address_a[2] => ram_block1a3.PORTAADDR2
518 
address_a[2] => ram_block1a4.PORTAADDR2
519 
address_a[2] => ram_block1a5.PORTAADDR2
520 
address_a[2] => ram_block1a6.PORTAADDR2
521 
address_a[2] => ram_block1a7.PORTAADDR2
522 
address_a[3] => ram_block1a0.PORTAADDR3
523 
address_a[3] => ram_block1a1.PORTAADDR3
524 
address_a[3] => ram_block1a2.PORTAADDR3
525 
address_a[3] => ram_block1a3.PORTAADDR3
526 
address_a[3] => ram_block1a4.PORTAADDR3
527 
address_a[3] => ram_block1a5.PORTAADDR3
528 
address_a[3] => ram_block1a6.PORTAADDR3
529 
address_a[3] => ram_block1a7.PORTAADDR3
530 
address_a[4] => ram_block1a0.PORTAADDR4
531 
address_a[4] => ram_block1a1.PORTAADDR4
532 
address_a[4] => ram_block1a2.PORTAADDR4
533 
address_a[4] => ram_block1a3.PORTAADDR4
534 
address_a[4] => ram_block1a4.PORTAADDR4
535 
address_a[4] => ram_block1a5.PORTAADDR4
536 
address_a[4] => ram_block1a6.PORTAADDR4
537 
address_a[4] => ram_block1a7.PORTAADDR4
538 
address_a[5] => ram_block1a0.PORTAADDR5
539 
address_a[5] => ram_block1a1.PORTAADDR5
540 
address_a[5] => ram_block1a2.PORTAADDR5
541 
address_a[5] => ram_block1a3.PORTAADDR5
542 
address_a[5] => ram_block1a4.PORTAADDR5
543 
address_a[5] => ram_block1a5.PORTAADDR5
544 
address_a[5] => ram_block1a6.PORTAADDR5
545 
address_a[5] => ram_block1a7.PORTAADDR5
546 
address_a[6] => ram_block1a0.PORTAADDR6
547 
address_a[6] => ram_block1a1.PORTAADDR6
548 
address_a[6] => ram_block1a2.PORTAADDR6
549 
address_a[6] => ram_block1a3.PORTAADDR6
550 
address_a[6] => ram_block1a4.PORTAADDR6
551 
address_a[6] => ram_block1a5.PORTAADDR6
552 
address_a[6] => ram_block1a6.PORTAADDR6
553 
address_a[6] => ram_block1a7.PORTAADDR6
554 
address_b[0] => ram_block1a0.PORTBADDR
555 
address_b[0] => ram_block1a1.PORTBADDR
556 
address_b[0] => ram_block1a2.PORTBADDR
557 
address_b[0] => ram_block1a3.PORTBADDR
558 
address_b[0] => ram_block1a4.PORTBADDR
559 
address_b[0] => ram_block1a5.PORTBADDR
560 
address_b[0] => ram_block1a6.PORTBADDR
561 
address_b[0] => ram_block1a7.PORTBADDR
562 
address_b[1] => ram_block1a0.PORTBADDR1
563 
address_b[1] => ram_block1a1.PORTBADDR1
564 
address_b[1] => ram_block1a2.PORTBADDR1
565 
address_b[1] => ram_block1a3.PORTBADDR1
566 
address_b[1] => ram_block1a4.PORTBADDR1
567 
address_b[1] => ram_block1a5.PORTBADDR1
568 
address_b[1] => ram_block1a6.PORTBADDR1
569 
address_b[1] => ram_block1a7.PORTBADDR1
570 
address_b[2] => ram_block1a0.PORTBADDR2
571 
address_b[2] => ram_block1a1.PORTBADDR2
572 
address_b[2] => ram_block1a2.PORTBADDR2
573 
address_b[2] => ram_block1a3.PORTBADDR2
574 
address_b[2] => ram_block1a4.PORTBADDR2
575 
address_b[2] => ram_block1a5.PORTBADDR2
576 
address_b[2] => ram_block1a6.PORTBADDR2
577 
address_b[2] => ram_block1a7.PORTBADDR2
578 
address_b[3] => ram_block1a0.PORTBADDR3
579 
address_b[3] => ram_block1a1.PORTBADDR3
580 
address_b[3] => ram_block1a2.PORTBADDR3
581 
address_b[3] => ram_block1a3.PORTBADDR3
582 
address_b[3] => ram_block1a4.PORTBADDR3
583 
address_b[3] => ram_block1a5.PORTBADDR3
584 
address_b[3] => ram_block1a6.PORTBADDR3
585 
address_b[3] => ram_block1a7.PORTBADDR3
586 
address_b[4] => ram_block1a0.PORTBADDR4
587 
address_b[4] => ram_block1a1.PORTBADDR4
588 
address_b[4] => ram_block1a2.PORTBADDR4
589 
address_b[4] => ram_block1a3.PORTBADDR4
590 
address_b[4] => ram_block1a4.PORTBADDR4
591 
address_b[4] => ram_block1a5.PORTBADDR4
592 
address_b[4] => ram_block1a6.PORTBADDR4
593 
address_b[4] => ram_block1a7.PORTBADDR4
594 
address_b[5] => ram_block1a0.PORTBADDR5
595 
address_b[5] => ram_block1a1.PORTBADDR5
596 
address_b[5] => ram_block1a2.PORTBADDR5
597 
address_b[5] => ram_block1a3.PORTBADDR5
598 
address_b[5] => ram_block1a4.PORTBADDR5
599 
address_b[5] => ram_block1a5.PORTBADDR5
600 
address_b[5] => ram_block1a6.PORTBADDR5
601 
address_b[5] => ram_block1a7.PORTBADDR5
602 
address_b[6] => ram_block1a0.PORTBADDR6
603 
address_b[6] => ram_block1a1.PORTBADDR6
604 
address_b[6] => ram_block1a2.PORTBADDR6
605 
address_b[6] => ram_block1a3.PORTBADDR6
606 
address_b[6] => ram_block1a4.PORTBADDR6
607 
address_b[6] => ram_block1a5.PORTBADDR6
608 
address_b[6] => ram_block1a6.PORTBADDR6
609 
address_b[6] => ram_block1a7.PORTBADDR6
610 
clock0 => ram_block1a0.CLK0
611 
clock0 => ram_block1a1.CLK0
612 
clock0 => ram_block1a2.CLK0
613 
clock0 => ram_block1a3.CLK0
614 
clock0 => ram_block1a4.CLK0
615 
clock0 => ram_block1a5.CLK0
616 
clock0 => ram_block1a6.CLK0
617 
clock0 => ram_block1a7.CLK0
618 
data_a[0] => ram_block1a0.PORTADATAIN
619 
data_a[1] => ram_block1a1.PORTADATAIN
620 
data_a[2] => ram_block1a2.PORTADATAIN
621 
data_a[3] => ram_block1a3.PORTADATAIN
622 
data_a[4] => ram_block1a4.PORTADATAIN
623 
data_a[5] => ram_block1a5.PORTADATAIN
624 
data_a[6] => ram_block1a6.PORTADATAIN
625 
data_a[7] => ram_block1a7.PORTADATAIN
626 
q_a[0] <=
627 
q_a[1] <=
628 
q_a[2] <=
629 
q_a[3] <=
630 
q_a[4] <=
631 
q_a[5] <=
632 
q_a[6] <=
633 
q_a[7] <=
634 
q_b[0] <= ram_block1a0.PORTBDATAOUT
635 
q_b[1] <= ram_block1a1.PORTBDATAOUT
636 
q_b[2] <= ram_block1a2.PORTBDATAOUT
637 
q_b[3] <= ram_block1a3.PORTBDATAOUT
638 
q_b[4] <= ram_block1a4.PORTBDATAOUT
639 
q_b[5] <= ram_block1a5.PORTBDATAOUT
640 
q_b[6] <= ram_block1a6.PORTBDATAOUT
641 
q_b[7] <= ram_block1a7.PORTBDATAOUT
642 
wren_a => ram_block1a0.PORTAWE
643 
wren_a => ram_block1a1.PORTAWE
644 
wren_a => ram_block1a2.PORTAWE
645 
wren_a => ram_block1a3.PORTAWE
646 
wren_a => ram_block1a4.PORTAWE
647 
wren_a => ram_block1a5.PORTAWE
648 
wren_a => ram_block1a6.PORTAWE
649 
wren_a => ram_block1a7.PORTAWE
650 
 
651 
 
652 
|ClaiRISC_core|pram:program_rom
653 
sclrsclrw_pc_nxt_0_0_a2_x_0 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_0
654 
sclrsclrw_pc_nxt_0_0_a2_x_1 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_1
655 
sclrsclrw_pc_nxt_0_0_a2_x_2 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_2
656 
sclrsclrw_pc_nxt_0_0_a2_x_3 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_3
657 
sclrsclrw_pc_nxt_0_0_a2_x_4 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_4
658 
sclrsclrw_pc_nxt_0_0_a2_x_5 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_5
659 
sclrsclrw_pc_nxt_0_0_a2_x_6 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_6
660 
w_ins_0 <= rom128x12:i_alt_ram.w_ins_0
661 
w_ins_1 <= rom128x12:i_alt_ram.w_ins_1
662 
w_ins_2 <= rom128x12:i_alt_ram.w_ins_2
663 
w_ins_3 <= rom128x12:i_alt_ram.w_ins_3
664 
w_ins_4 <= rom128x12:i_alt_ram.w_ins_4
665 
w_ins_6 <= rom128x12:i_alt_ram.w_ins_6
666 
w_ins_7 <= rom128x12:i_alt_ram.w_ins_7
667 
clk_c => rom128x12:i_alt_ram.clk_c
668 
w_mem_wr <= rom128x12:i_alt_ram.w_mem_wr
669 
 
670 
 
671 
|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram
672 
w_ins_7 <= altsyncram_Z2:altsyncram_component_Z.q_a[7]
673 
w_ins_6 <= altsyncram_Z2:altsyncram_component_Z.q_a[6]
674 
w_ins_4 <= altsyncram_Z2:altsyncram_component_Z.q_a[4]
675 
w_ins_3 <= altsyncram_Z2:altsyncram_component_Z.q_a[3]
676 
w_ins_2 <= altsyncram_Z2:altsyncram_component_Z.q_a[2]
677 
w_ins_1 <= altsyncram_Z2:altsyncram_component_Z.q_a[1]
678 
w_ins_0 <= altsyncram_Z2:altsyncram_component_Z.q_a[0]
679 
sclrsclrw_pc_nxt_0_0_a2_x_6 => altsyncram_Z2:altsyncram_component_Z.address_a[6]
680 
sclrsclrw_pc_nxt_0_0_a2_x_5 => altsyncram_Z2:altsyncram_component_Z.address_a[5]
681 
sclrsclrw_pc_nxt_0_0_a2_x_4 => altsyncram_Z2:altsyncram_component_Z.address_a[4]
682 
sclrsclrw_pc_nxt_0_0_a2_x_3 => altsyncram_Z2:altsyncram_component_Z.address_a[3]
683 
sclrsclrw_pc_nxt_0_0_a2_x_2 => altsyncram_Z2:altsyncram_component_Z.address_a[2]
684 
sclrsclrw_pc_nxt_0_0_a2_x_1 => altsyncram_Z2:altsyncram_component_Z.address_a[1]
685 
sclrsclrw_pc_nxt_0_0_a2_x_0 => altsyncram_Z2:altsyncram_component_Z.address_a[0]
686 
w_mem_wr <= altsyncram_Z2:altsyncram_component_Z.q_a[5]
687 
clk_c => altsyncram_Z2:altsyncram_component_Z.clock0
688 
 
689 
 
690 
|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z
691 
address_a[0] => altsyncram:U1.address_a
692 
address_a[1] => altsyncram:U1.address_a
693 
address_a[2] => altsyncram:U1.address_a
694 
address_a[3] => altsyncram:U1.address_a
695 
address_a[4] => altsyncram:U1.address_a
696 
address_a[5] => altsyncram:U1.address_a
697 
address_a[6] => altsyncram:U1.address_a
698 
clock0 => altsyncram:U1.clock0
699 
q_a[0] <= altsyncram:U1.q_a
700 
q_a[1] <= altsyncram:U1.q_a
701 
q_a[2] <= altsyncram:U1.q_a
702 
q_a[3] <= altsyncram:U1.q_a
703 
q_a[4] <= altsyncram:U1.q_a
704 
q_a[5] <= altsyncram:U1.q_a
705 
q_a[6] <= altsyncram:U1.q_a
706 
q_a[7] <= altsyncram:U1.q_a
707 
q_b[0] <= altsyncram:U1.q_b
708 
 
709 
 
710 
|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z|altsyncram:U1
711 
wren_a => ~NO_FANOUT~
712 
wren_b => ~NO_FANOUT~
713 
rden_b => ~NO_FANOUT~
714 
data_a[0] => ~NO_FANOUT~
715 
data_a[1] => ~NO_FANOUT~
716 
data_a[2] => ~NO_FANOUT~
717 
data_a[3] => ~NO_FANOUT~
718 
data_a[4] => ~NO_FANOUT~
719 
data_a[5] => ~NO_FANOUT~
720 
data_a[6] => ~NO_FANOUT~
721 
data_a[7] => ~NO_FANOUT~
722 
data_b[0] => ~NO_FANOUT~
723 
address_a[0] => altsyncram_u8r:auto_generated.address_a[0]
724 
address_a[1] => altsyncram_u8r:auto_generated.address_a[1]
725 
address_a[2] => altsyncram_u8r:auto_generated.address_a[2]
726 
address_a[3] => altsyncram_u8r:auto_generated.address_a[3]
727 
address_a[4] => altsyncram_u8r:auto_generated.address_a[4]
728 
address_a[5] => altsyncram_u8r:auto_generated.address_a[5]
729 
address_a[6] => altsyncram_u8r:auto_generated.address_a[6]
730 
address_b[0] => ~NO_FANOUT~
731 
addressstall_a => ~NO_FANOUT~
732 
addressstall_b => ~NO_FANOUT~
733 
clock0 => altsyncram_u8r:auto_generated.clock0
734 
clock1 => ~NO_FANOUT~
735 
clocken0 => ~NO_FANOUT~
736 
clocken1 => ~NO_FANOUT~
737 
aclr0 => ~NO_FANOUT~
738 
aclr1 => ~NO_FANOUT~
739 
byteena_a[0] => ~NO_FANOUT~
740 
byteena_b[0] => ~NO_FANOUT~
741 
q_a[0] <= altsyncram_u8r:auto_generated.q_a[0]
742 
q_a[1] <= altsyncram_u8r:auto_generated.q_a[1]
743 
q_a[2] <= altsyncram_u8r:auto_generated.q_a[2]
744 
q_a[3] <= altsyncram_u8r:auto_generated.q_a[3]
745 
q_a[4] <= altsyncram_u8r:auto_generated.q_a[4]
746 
q_a[5] <= altsyncram_u8r:auto_generated.q_a[5]
747 
q_a[6] <= altsyncram_u8r:auto_generated.q_a[6]
748 
q_a[7] <= altsyncram_u8r:auto_generated.q_a[7]
749 
q_b[0] <= altsyncram_u8r:auto_generated.q_b[0]
750 
 
751 
 
752 
|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z|altsyncram:U1|altsyncram_u8r:auto_generated
753 
address_a[0] => ram_block1a0.PORTAADDR
754 
address_a[0] => ram_block1a1.PORTAADDR
755 
address_a[0] => ram_block1a2.PORTAADDR
756 
address_a[0] => ram_block1a3.PORTAADDR
757 
address_a[0] => ram_block1a4.PORTAADDR
758 
address_a[0] => ram_block1a5.PORTAADDR
759 
address_a[0] => ram_block1a6.PORTAADDR
760 
address_a[0] => ram_block1a7.PORTAADDR
761 
address_a[1] => ram_block1a0.PORTAADDR1
762 
address_a[1] => ram_block1a1.PORTAADDR1
763 
address_a[1] => ram_block1a2.PORTAADDR1
764 
address_a[1] => ram_block1a3.PORTAADDR1
765 
address_a[1] => ram_block1a4.PORTAADDR1
766 
address_a[1] => ram_block1a5.PORTAADDR1
767 
address_a[1] => ram_block1a6.PORTAADDR1
768 
address_a[1] => ram_block1a7.PORTAADDR1
769 
address_a[2] => ram_block1a0.PORTAADDR2
770 
address_a[2] => ram_block1a1.PORTAADDR2
771 
address_a[2] => ram_block1a2.PORTAADDR2
772 
address_a[2] => ram_block1a3.PORTAADDR2
773 
address_a[2] => ram_block1a4.PORTAADDR2
774 
address_a[2] => ram_block1a5.PORTAADDR2
775 
address_a[2] => ram_block1a6.PORTAADDR2
776 
address_a[2] => ram_block1a7.PORTAADDR2
777 
address_a[3] => ram_block1a0.PORTAADDR3
778 
address_a[3] => ram_block1a1.PORTAADDR3
779 
address_a[3] => ram_block1a2.PORTAADDR3
780 
address_a[3] => ram_block1a3.PORTAADDR3
781 
address_a[3] => ram_block1a4.PORTAADDR3
782 
address_a[3] => ram_block1a5.PORTAADDR3
783 
address_a[3] => ram_block1a6.PORTAADDR3
784 
address_a[3] => ram_block1a7.PORTAADDR3
785 
address_a[4] => ram_block1a0.PORTAADDR4
786 
address_a[4] => ram_block1a1.PORTAADDR4
787 
address_a[4] => ram_block1a2.PORTAADDR4
788 
address_a[4] => ram_block1a3.PORTAADDR4
789 
address_a[4] => ram_block1a4.PORTAADDR4
790 
address_a[4] => ram_block1a5.PORTAADDR4
791 
address_a[4] => ram_block1a6.PORTAADDR4
792 
address_a[4] => ram_block1a7.PORTAADDR4
793 
address_a[5] => ram_block1a0.PORTAADDR5
794 
address_a[5] => ram_block1a1.PORTAADDR5
795 
address_a[5] => ram_block1a2.PORTAADDR5
796 
address_a[5] => ram_block1a3.PORTAADDR5
797 
address_a[5] => ram_block1a4.PORTAADDR5
798 
address_a[5] => ram_block1a5.PORTAADDR5
799 
address_a[5] => ram_block1a6.PORTAADDR5
800 
address_a[5] => ram_block1a7.PORTAADDR5
801 
address_a[6] => ram_block1a0.PORTAADDR6
802 
address_a[6] => ram_block1a1.PORTAADDR6
803 
address_a[6] => ram_block1a2.PORTAADDR6
804 
address_a[6] => ram_block1a3.PORTAADDR6
805 
address_a[6] => ram_block1a4.PORTAADDR6
806 
address_a[6] => ram_block1a5.PORTAADDR6
807 
address_a[6] => ram_block1a6.PORTAADDR6
808 
address_a[6] => ram_block1a7.PORTAADDR6
809 
clock0 => ram_block1a0.CLK0
810 
clock0 => ram_block1a1.CLK0
811 
clock0 => ram_block1a2.CLK0
812 
clock0 => ram_block1a3.CLK0
813 
clock0 => ram_block1a4.CLK0
814 
clock0 => ram_block1a5.CLK0
815 
clock0 => ram_block1a6.CLK0
816 
clock0 => ram_block1a7.CLK0
817 
q_a[0] <= ram_block1a0.PORTADATAOUT
818 
q_a[1] <= ram_block1a1.PORTADATAOUT
819 
q_a[2] <= ram_block1a2.PORTADATAOUT
820 
q_a[3] <= ram_block1a3.PORTADATAOUT
821 
q_a[4] <= ram_block1a4.PORTADATAOUT
822 
q_a[5] <= ram_block1a5.PORTADATAOUT
823 
q_a[6] <= ram_block1a6.PORTADATAOUT
824 
q_a[7] <= ram_block1a7.PORTADATAOUT
825 
q_b[0] <=
826 
 
827 
 

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