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[/] [lwrisc/] [trunk/] [QU2/] [db/] [ClaiRISC_core.hif] - Blame information for rev 19

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Version 4.2 Build 157 12/07/2004 SJ Full Version
32
1575
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
RETIME_OFF
REMAP_OFF
 
-- Start Partition --
|
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
Off
ADV_NETLIST_OPT_SYNTH_GATE_RETIME
Off
STATE_MACHINE_PROCESSING
Auto
STRATIXII_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONE_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONEII_OPTIMIZATION_TECHNIQUE
Balanced
STRATIX_OPTIMIZATION_TECHNIQUE
Balanced
MAXII_OPTIMIZATION_TECHNIQUE
Balanced
----
-- End Partition --
# entity
ClaiRISC_core
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(0).cnf
db|ClaiRISC_core.(0).cnf
# end
# entity
wb_mem_man
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(1).cnf
db|ClaiRISC_core.(1).cnf
# end
# entity
ram128x8
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(2).cnf
db|ClaiRISC_core.(2).cnf
# end
# entity
altsyncram_Z1
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(3).cnf
db|ClaiRISC_core.(3).cnf
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus42|libraries|megafunctions|altsyncram.tdf
1101745298
6
# storage
db|ClaiRISC_core.(4).cnf
db|ClaiRISC_core.(4).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
7
PARAMETER_UNKNOWN
USR
NUMWORDS_A
128
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_UNKNOWN
USR
WIDTHAD_B
7
PARAMETER_UNKNOWN
USR
NUMWORDS_B
128
PARAMETER_UNKNOWN
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
 
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_hg91
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
c:|altera|quartus42|libraries|megafunctions|stratix_ram_block.inc
1094871114
c:|altera|quartus42|libraries|megafunctions|lpm_mux.inc
1094870318
c:|altera|quartus42|libraries|megafunctions|lpm_decode.inc
1094870100
c:|altera|quartus42|libraries|megafunctions|aglobal42.inc
1101745276
c:|altera|quartus42|libraries|megafunctions|altsyncram.inc
1094868954
c:|altera|quartus42|libraries|megafunctions|a_rdenreg.inc
1094867530
c:|altera|quartus42|libraries|megafunctions|altrom.inc
1094868876
c:|altera|quartus42|libraries|megafunctions|altram.inc
1094868838
c:|altera|quartus42|libraries|megafunctions|altdpram.inc
1094868494
c:|altera|quartus42|libraries|megafunctions|altqpram.inc
1094868820
}
# end
# entity
altsyncram_hg91
# case_insensitive
# source_file
db|altsyncram_hg91.tdf
1205137604
6
# storage
db|ClaiRISC_core.(5).cnf
db|ClaiRISC_core.(5).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
none
 
}
# end
# entity
pram
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(6).cnf
db|ClaiRISC_core.(6).cnf
# end
# entity
rom128x12
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(7).cnf
db|ClaiRISC_core.(7).cnf
# end
# entity
altsyncram_Z2
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(8).cnf
db|ClaiRISC_core.(8).cnf
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus42|libraries|megafunctions|altsyncram.tdf
1101745298
6
# storage
db|ClaiRISC_core.(9).cnf
db|ClaiRISC_core.(9).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
7
PARAMETER_UNKNOWN
USR
NUMWORDS_A
128
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
init_file.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
 
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_u8r
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
clock0
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_b
}
# include_file {
c:|altera|quartus42|libraries|megafunctions|stratix_ram_block.inc
1094871114
c:|altera|quartus42|libraries|megafunctions|lpm_mux.inc
1094870318
c:|altera|quartus42|libraries|megafunctions|lpm_decode.inc
1094870100
c:|altera|quartus42|libraries|megafunctions|aglobal42.inc
1101745276
c:|altera|quartus42|libraries|megafunctions|altsyncram.inc
1094868954
c:|altera|quartus42|libraries|megafunctions|a_rdenreg.inc
1094867530
c:|altera|quartus42|libraries|megafunctions|altrom.inc
1094868876
c:|altera|quartus42|libraries|megafunctions|altram.inc
1094868838
c:|altera|quartus42|libraries|megafunctions|altdpram.inc
1094868494
c:|altera|quartus42|libraries|megafunctions|altqpram.inc
1094868820
}
# end
# entity
altsyncram_u8r
# case_insensitive
# source_file
db|altsyncram_u8r.tdf
1205137606
6
# storage
db|ClaiRISC_core.(10).cnf
db|ClaiRISC_core.(10).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
}
# memory_file {
init_file.mif
 
}
# end
# complete
 

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Subversion Repositories lwrisc

[/] [lwrisc/] [trunk/] [QU2/] [db/] [ClaiRISC_core.hif] - Blame information for rev 19

Line No.	Rev	Author	Line
1	10	mcupro	`Version 4.2 Build 157 12/07/2004 SJ Full Version`
2			`32`
3			`1575`
4			`OFF`
5			`OFF`
6			`OFF`
7			`OFF`
8			`OFF`
9			`FV_OFF`
10			`VRSM_ON`
11			`VHSM_ON`
12			`RETIME_OFF`
13			`REMAP_OFF`
14
15			`-- Start Partition --`
16			`\|`
17			`ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP`
18			`Off`
19			`ADV_NETLIST_OPT_SYNTH_GATE_RETIME`
20			`Off`
21			`STATE_MACHINE_PROCESSING`
22			`Auto`
23			`STRATIXII_OPTIMIZATION_TECHNIQUE`
24			`Balanced`
25			`CYCLONE_OPTIMIZATION_TECHNIQUE`
26			`Balanced`
27			`CYCLONEII_OPTIMIZATION_TECHNIQUE`
28			`Balanced`
29			`STRATIX_OPTIMIZATION_TECHNIQUE`
30			`Balanced`
31			`MAXII_OPTIMIZATION_TECHNIQUE`
32			`Balanced`
33			`----`
34			`-- End Partition --`
35			`# entity`
36			`ClaiRISC_core`
37			`# case_sensitive`
38			`# source_file`
39			`..\|SYN\|rev_1\|ClaiRISC_core.vqm`
40			`1205137544`
41			`25`
42			`# storage`
43			`db\|ClaiRISC_core.(0).cnf`
44			`db\|ClaiRISC_core.(0).cnf`
45			`# end`
46			`# entity`
47			`wb_mem_man`
48			`# case_sensitive`
49			`# source_file`
50			`..\|SYN\|rev_1\|ClaiRISC_core.vqm`
51			`1205137544`
52			`25`
53			`# storage`
54			`db\|ClaiRISC_core.(1).cnf`
55			`db\|ClaiRISC_core.(1).cnf`
56			`# end`
57			`# entity`
58			`ram128x8`
59			`# case_sensitive`
60			`# source_file`
61			`..\|SYN\|rev_1\|ClaiRISC_core.vqm`
62			`1205137544`
63			`25`
64			`# storage`
65			`db\|ClaiRISC_core.(2).cnf`
66			`db\|ClaiRISC_core.(2).cnf`
67			`# end`
68			`# entity`
69			`altsyncram_Z1`
70			`# case_sensitive`
71			`# source_file`
72			`..\|SYN\|rev_1\|ClaiRISC_core.vqm`
73			`1205137544`
74			`25`
75			`# storage`
76			`db\|ClaiRISC_core.(3).cnf`
77			`db\|ClaiRISC_core.(3).cnf`
78			`# end`
79			`# entity`
80			`altsyncram`
81			`# case_insensitive`
82			`# source_file`
83			`c:\|altera\|quartus42\|libraries\|megafunctions\|altsyncram.tdf`
84			`1101745298`
85			`6`
86			`# storage`
87			`db\|ClaiRISC_core.(4).cnf`
88			`db\|ClaiRISC_core.(4).cnf`
89			`# user_parameter {`
90			`BYTE_SIZE_BLOCK`
91			`8`
92			`PARAMETER_UNKNOWN`
93			`DEF`
94			`AUTO_CARRY_CHAINS`
95			`ON`
96			`AUTO_CARRY`
97			`USR`
98			`IGNORE_CARRY_BUFFERS`
99			`OFF`
100			`IGNORE_CARRY`
101			`USR`
102			`AUTO_CASCADE_CHAINS`
103			`ON`
104			`AUTO_CASCADE`
105			`USR`
106			`IGNORE_CASCADE_BUFFERS`
107			`OFF`
108			`IGNORE_CASCADE`
109			`USR`
110			`OPERATION_MODE`
111			`DUAL_PORT`
112			`PARAMETER_UNKNOWN`
113			`USR`
114			`WIDTH_A`
115			`8`
116			`PARAMETER_UNKNOWN`
117			`USR`
118			`WIDTHAD_A`
119			`7`
120			`PARAMETER_UNKNOWN`
121			`USR`
122			`NUMWORDS_A`
123			`128`
124			`PARAMETER_UNKNOWN`
125			`USR`
126			`OUTDATA_REG_A`
127			`UNREGISTERED`
128			`PARAMETER_UNKNOWN`
129			`DEF`
130			`ADDRESS_ACLR_A`
131			`NONE`
132			`PARAMETER_UNKNOWN`
133			`USR`
134			`OUTDATA_ACLR_A`
135			`NONE`
136			`PARAMETER_UNKNOWN`
137			`DEF`
138			`WRCONTROL_ACLR_A`
139			`NONE`
140			`PARAMETER_UNKNOWN`
141			`USR`
142			`INDATA_ACLR_A`
143			`NONE`
144			`PARAMETER_UNKNOWN`
145			`USR`
146			`BYTEENA_ACLR_A`
147			`NONE`
148			`PARAMETER_UNKNOWN`
149			`DEF`
150			`WIDTH_B`
151			`8`
152			`PARAMETER_UNKNOWN`
153			`USR`
154			`WIDTHAD_B`
155			`7`
156			`PARAMETER_UNKNOWN`
157			`USR`
158			`NUMWORDS_B`
159			`128`
160			`PARAMETER_UNKNOWN`
161			`USR`
162			`INDATA_REG_B`
163			`CLOCK1`
164			`PARAMETER_UNKNOWN`
165			`DEF`
166			`WRCONTROL_WRADDRESS_REG_B`
167			`CLOCK1`
168			`PARAMETER_UNKNOWN`
169			`DEF`
170			`RDCONTROL_REG_B`
171			`CLOCK1`
172			`PARAMETER_UNKNOWN`
173			`DEF`
174			`ADDRESS_REG_B`
175			`CLOCK0`
176			`PARAMETER_UNKNOWN`
177			`USR`
178			`OUTDATA_REG_B`
179			`UNREGISTERED`
180			`PARAMETER_UNKNOWN`
181			`USR`
182			`BYTEENA_REG_B`
183			`CLOCK1`
184			`PARAMETER_UNKNOWN`
185			`DEF`
186			`INDATA_ACLR_B`
187			`NONE`
188			`PARAMETER_UNKNOWN`
189			`DEF`
190			`WRCONTROL_ACLR_B`
191			`NONE`
192			`PARAMETER_UNKNOWN`
193			`DEF`
194			`ADDRESS_ACLR_B`
195			`NONE`
196			`PARAMETER_UNKNOWN`
197			`USR`
198			`OUTDATA_ACLR_B`
199			`NONE`
200			`PARAMETER_UNKNOWN`
201			`USR`
202			`RDCONTROL_ACLR_B`
203			`NONE`
204			`PARAMETER_UNKNOWN`
205			`DEF`
206			`BYTEENA_ACLR_B`
207			`NONE`
208			`PARAMETER_UNKNOWN`
209			`DEF`
210			`WIDTH_BYTEENA_A`
211			`1`
212			`PARAMETER_UNKNOWN`
213			`USR`
214			`WIDTH_BYTEENA_B`
215			`1`
216			`PARAMETER_UNKNOWN`
217			`DEF`
218			`RAM_BLOCK_TYPE`
219			`AUTO`
220			`PARAMETER_UNKNOWN`
221			`DEF`
222			`BYTE_SIZE`
223			`8`
224			`PARAMETER_UNKNOWN`
225			`DEF`
226			`READ_DURING_WRITE_MODE_MIXED_PORTS`
227			`DONT_CARE`
228			`PARAMETER_UNKNOWN`
229			`USR`
230			`INIT_FILE`
231			`UNUSED`
232			`PARAMETER_UNKNOWN`
233			`DEF`
234			`INIT_FILE_LAYOUT`
235			`PORT_A`
236			`PARAMETER_UNKNOWN`
237			`DEF`
238			`MAXIMUM_DEPTH`
239
240			`PARAMETER_UNKNOWN`
241			`DEF`
242			`CLOCK_ENABLE_INPUT_A`
243			`NORMAL`
244			`PARAMETER_UNKNOWN`
245			`DEF`
246			`CLOCK_ENABLE_INPUT_B`
247			`NORMAL`
248			`PARAMETER_UNKNOWN`
249			`DEF`
250			`CLOCK_ENABLE_OUTPUT_A`
251			`NORMAL`
252			`PARAMETER_UNKNOWN`
253			`DEF`
254			`CLOCK_ENABLE_OUTPUT_B`
255			`NORMAL`
256			`PARAMETER_UNKNOWN`
257			`DEF`
258			`DEVICE_FAMILY`
259			`Cyclone`
260			`PARAMETER_UNKNOWN`
261			`USR`
262			`CBXI_PARAMETER`
263			`altsyncram_hg91`
264			`PARAMETER_UNKNOWN`
265			`USR`
266			`}`
267			`# used_port {`
268			`address_a`
269			`address_a`
270			`address_a`
271			`address_a`
272			`address_a`
273			`address_a`
274			`address_a`
275			`address_b`
276			`address_b`
277			`address_b`
278			`address_b`
279			`address_b`
280			`address_b`
281			`address_b`
282			`clock0`
283			`data_a`
284			`data_a`
285			`data_a`
286			`data_a`
287			`data_a`
288			`data_a`
289			`data_a`
290			`data_a`
291			`q_a`
292			`q_a`
293			`q_a`
294			`q_a`
295			`q_a`
296			`q_a`
297			`q_a`
298			`q_a`
299			`q_b`
300			`q_b`
301			`q_b`
302			`q_b`
303			`q_b`
304			`q_b`
305			`q_b`
306			`q_b`
307			`wren_a`
308			`}`
309			`# include_file {`
310			`c:\|altera\|quartus42\|libraries\|megafunctions\|stratix_ram_block.inc`
311			`1094871114`
312			`c:\|altera\|quartus42\|libraries\|megafunctions\|lpm_mux.inc`
313			`1094870318`
314			`c:\|altera\|quartus42\|libraries\|megafunctions\|lpm_decode.inc`
315			`1094870100`
316			`c:\|altera\|quartus42\|libraries\|megafunctions\|aglobal42.inc`
317			`1101745276`
318			`c:\|altera\|quartus42\|libraries\|megafunctions\|altsyncram.inc`
319			`1094868954`
320			`c:\|altera\|quartus42\|libraries\|megafunctions\|a_rdenreg.inc`
321			`1094867530`
322			`c:\|altera\|quartus42\|libraries\|megafunctions\|altrom.inc`
323			`1094868876`
324			`c:\|altera\|quartus42\|libraries\|megafunctions\|altram.inc`
325			`1094868838`
326			`c:\|altera\|quartus42\|libraries\|megafunctions\|altdpram.inc`
327			`1094868494`
328			`c:\|altera\|quartus42\|libraries\|megafunctions\|altqpram.inc`
329			`1094868820`
330			`}`
331			`# end`
332			`# entity`
333			`altsyncram_hg91`
334			`# case_insensitive`
335			`# source_file`
336			`db\|altsyncram_hg91.tdf`
337			`1205137604`
338			`6`
339			`# storage`
340			`db\|ClaiRISC_core.(5).cnf`
341			`db\|ClaiRISC_core.(5).cnf`
342			`# user_parameter {`
343			`PORT_A_ADDRESS_WIDTH`
344			`1`
345			`PARAMETER_UNKNOWN`
346			`DEF`
347			`PORT_A_BYTE_ENABLE_MASK_WIDTH`
348			`1`
349			`PARAMETER_UNKNOWN`
350			`DEF`
351			`PORT_A_DATA_WIDTH`
352			`1`
353			`PARAMETER_UNKNOWN`
354			`DEF`
355			`PORT_B_ADDRESS_WIDTH`
356			`1`
357			`PARAMETER_UNKNOWN`
358			`DEF`
359			`PORT_B_BYTE_ENABLE_MASK_WIDTH`
360			`1`
361			`PARAMETER_UNKNOWN`
362			`DEF`
363			`PORT_B_DATA_WIDTH`
364			`1`
365			`PARAMETER_UNKNOWN`
366			`DEF`
367			`}`
368			`# used_port {`
369			`wren_a`
370			`data_a0`
371			`data_a1`
372			`data_a2`
373			`data_a3`
374			`data_a4`
375			`data_a5`
376			`data_a6`
377			`data_a7`
378			`address_a0`
379			`address_a1`
380			`address_a2`
381			`address_a3`
382			`address_a4`
383			`address_a5`
384			`address_a6`
385			`address_b0`
386			`address_b1`
387			`address_b2`
388			`address_b3`
389			`address_b4`
390			`address_b5`
391			`address_b6`
392			`clock0`
393			`q_a0`
394			`q_a1`
395			`q_a2`
396			`q_a3`
397			`q_a4`
398			`q_a5`
399			`q_a6`
400			`q_a7`
401			`q_b0`
402			`q_b1`
403			`q_b2`
404			`q_b3`
405			`q_b4`
406			`q_b5`
407			`q_b6`
408			`q_b7`
409			`}`
410			`# memory_file {`
411			`none`
412
413			`}`
414			`# end`
415			`# entity`
416			`pram`
417			`# case_sensitive`
418			`# source_file`
419			`..\|SYN\|rev_1\|ClaiRISC_core.vqm`
420			`1205137544`
421			`25`
422			`# storage`
423			`db\|ClaiRISC_core.(6).cnf`
424			`db\|ClaiRISC_core.(6).cnf`
425			`# end`
426			`# entity`
427			`rom128x12`
428			`# case_sensitive`
429			`# source_file`
430			`..\|SYN\|rev_1\|ClaiRISC_core.vqm`
431			`1205137544`
432			`25`
433			`# storage`
434			`db\|ClaiRISC_core.(7).cnf`
435			`db\|ClaiRISC_core.(7).cnf`
436			`# end`
437			`# entity`
438			`altsyncram_Z2`
439			`# case_sensitive`
440			`# source_file`
441			`..\|SYN\|rev_1\|ClaiRISC_core.vqm`
442			`1205137544`
443			`25`
444			`# storage`
445			`db\|ClaiRISC_core.(8).cnf`
446			`db\|ClaiRISC_core.(8).cnf`
447			`# end`
448			`# entity`
449			`altsyncram`
450			`# case_insensitive`
451			`# source_file`
452			`c:\|altera\|quartus42\|libraries\|megafunctions\|altsyncram.tdf`
453			`1101745298`
454			`6`
455			`# storage`
456			`db\|ClaiRISC_core.(9).cnf`
457			`db\|ClaiRISC_core.(9).cnf`
458			`# user_parameter {`
459			`BYTE_SIZE_BLOCK`
460			`8`
461			`PARAMETER_UNKNOWN`
462			`DEF`
463			`AUTO_CARRY_CHAINS`
464			`ON`
465			`AUTO_CARRY`
466			`USR`
467			`IGNORE_CARRY_BUFFERS`
468			`OFF`
469			`IGNORE_CARRY`
470			`USR`
471			`AUTO_CASCADE_CHAINS`
472			`ON`
473			`AUTO_CASCADE`
474			`USR`
475			`IGNORE_CASCADE_BUFFERS`
476			`OFF`
477			`IGNORE_CASCADE`
478			`USR`
479			`OPERATION_MODE`
480			`ROM`
481			`PARAMETER_UNKNOWN`
482			`USR`
483			`WIDTH_A`
484			`8`
485			`PARAMETER_UNKNOWN`
486			`USR`
487			`WIDTHAD_A`
488			`7`
489			`PARAMETER_UNKNOWN`
490			`USR`
491			`NUMWORDS_A`
492			`128`
493			`PARAMETER_UNKNOWN`
494			`USR`
495			`OUTDATA_REG_A`
496			`UNREGISTERED`
497			`PARAMETER_UNKNOWN`
498			`USR`
499			`ADDRESS_ACLR_A`
500			`NONE`
501			`PARAMETER_UNKNOWN`
502			`USR`
503			`OUTDATA_ACLR_A`
504			`NONE`
505			`PARAMETER_UNKNOWN`
506			`USR`
507			`WRCONTROL_ACLR_A`
508			`NONE`
509			`PARAMETER_UNKNOWN`
510			`DEF`
511			`INDATA_ACLR_A`
512			`NONE`
513			`PARAMETER_UNKNOWN`
514			`DEF`
515			`BYTEENA_ACLR_A`
516			`NONE`
517			`PARAMETER_UNKNOWN`
518			`DEF`
519			`WIDTH_B`
520			`1`
521			`PARAMETER_UNKNOWN`
522			`DEF`
523			`WIDTHAD_B`
524			`1`
525			`PARAMETER_UNKNOWN`
526			`DEF`
527			`NUMWORDS_B`
528			`1`
529			`PARAMETER_UNKNOWN`
530			`DEF`
531			`INDATA_REG_B`
532			`CLOCK1`
533			`PARAMETER_UNKNOWN`
534			`DEF`
535			`WRCONTROL_WRADDRESS_REG_B`
536			`CLOCK1`
537			`PARAMETER_UNKNOWN`
538			`DEF`
539			`RDCONTROL_REG_B`
540			`CLOCK1`
541			`PARAMETER_UNKNOWN`
542			`DEF`
543			`ADDRESS_REG_B`
544			`CLOCK1`
545			`PARAMETER_UNKNOWN`
546			`DEF`
547			`OUTDATA_REG_B`
548			`UNREGISTERED`
549			`PARAMETER_UNKNOWN`
550			`DEF`
551			`BYTEENA_REG_B`
552			`CLOCK1`
553			`PARAMETER_UNKNOWN`
554			`DEF`
555			`INDATA_ACLR_B`
556			`NONE`
557			`PARAMETER_UNKNOWN`
558			`DEF`
559			`WRCONTROL_ACLR_B`
560			`NONE`
561			`PARAMETER_UNKNOWN`
562			`DEF`
563			`ADDRESS_ACLR_B`
564			`NONE`
565			`PARAMETER_UNKNOWN`
566			`DEF`
567			`OUTDATA_ACLR_B`
568			`NONE`
569			`PARAMETER_UNKNOWN`
570			`DEF`
571			`RDCONTROL_ACLR_B`
572			`NONE`
573			`PARAMETER_UNKNOWN`
574			`DEF`
575			`BYTEENA_ACLR_B`
576			`NONE`
577			`PARAMETER_UNKNOWN`
578			`DEF`
579			`WIDTH_BYTEENA_A`
580			`1`
581			`PARAMETER_UNKNOWN`
582			`USR`
583			`WIDTH_BYTEENA_B`
584			`1`
585			`PARAMETER_UNKNOWN`
586			`DEF`
587			`RAM_BLOCK_TYPE`
588			`AUTO`
589			`PARAMETER_UNKNOWN`
590			`DEF`
591			`BYTE_SIZE`
592			`8`
593			`PARAMETER_UNKNOWN`
594			`DEF`
595			`READ_DURING_WRITE_MODE_MIXED_PORTS`
596			`DONT_CARE`
597			`PARAMETER_UNKNOWN`
598			`DEF`
599			`INIT_FILE`
600			`init_file.mif`
601			`PARAMETER_UNKNOWN`
602			`USR`
603			`INIT_FILE_LAYOUT`
604			`PORT_A`
605			`PARAMETER_UNKNOWN`
606			`DEF`
607			`MAXIMUM_DEPTH`
608
609			`PARAMETER_UNKNOWN`
610			`DEF`
611			`CLOCK_ENABLE_INPUT_A`
612			`NORMAL`
613			`PARAMETER_UNKNOWN`
614			`DEF`
615			`CLOCK_ENABLE_INPUT_B`
616			`NORMAL`
617			`PARAMETER_UNKNOWN`
618			`DEF`
619			`CLOCK_ENABLE_OUTPUT_A`
620			`NORMAL`
621			`PARAMETER_UNKNOWN`
622			`DEF`
623			`CLOCK_ENABLE_OUTPUT_B`
624			`NORMAL`
625			`PARAMETER_UNKNOWN`
626			`DEF`
627			`DEVICE_FAMILY`
628			`Cyclone`
629			`PARAMETER_UNKNOWN`
630			`USR`
631			`CBXI_PARAMETER`
632			`altsyncram_u8r`
633			`PARAMETER_UNKNOWN`
634			`USR`
635			`}`
636			`# used_port {`
637			`address_a`
638			`address_a`
639			`address_a`
640			`address_a`
641			`address_a`
642			`address_a`
643			`address_a`
644			`clock0`
645			`q_a`
646			`q_a`
647			`q_a`
648			`q_a`
649			`q_a`
650			`q_a`
651			`q_a`
652			`q_a`
653			`q_b`
654			`}`
655			`# include_file {`
656			`c:\|altera\|quartus42\|libraries\|megafunctions\|stratix_ram_block.inc`
657			`1094871114`
658			`c:\|altera\|quartus42\|libraries\|megafunctions\|lpm_mux.inc`
659			`1094870318`
660			`c:\|altera\|quartus42\|libraries\|megafunctions\|lpm_decode.inc`
661			`1094870100`
662			`c:\|altera\|quartus42\|libraries\|megafunctions\|aglobal42.inc`
663			`1101745276`
664			`c:\|altera\|quartus42\|libraries\|megafunctions\|altsyncram.inc`
665			`1094868954`
666			`c:\|altera\|quartus42\|libraries\|megafunctions\|a_rdenreg.inc`
667			`1094867530`
668			`c:\|altera\|quartus42\|libraries\|megafunctions\|altrom.inc`
669			`1094868876`
670			`c:\|altera\|quartus42\|libraries\|megafunctions\|altram.inc`
671			`1094868838`
672			`c:\|altera\|quartus42\|libraries\|megafunctions\|altdpram.inc`
673			`1094868494`
674			`c:\|altera\|quartus42\|libraries\|megafunctions\|altqpram.inc`
675			`1094868820`
676			`}`
677			`# end`
678			`# entity`
679			`altsyncram_u8r`
680			`# case_insensitive`
681			`# source_file`
682			`db\|altsyncram_u8r.tdf`
683			`1205137606`
684			`6`
685			`# storage`
686			`db\|ClaiRISC_core.(10).cnf`
687			`db\|ClaiRISC_core.(10).cnf`
688			`# user_parameter {`
689			`PORT_A_ADDRESS_WIDTH`
690			`1`
691			`PARAMETER_UNKNOWN`
692			`DEF`
693			`PORT_A_BYTE_ENABLE_MASK_WIDTH`
694			`1`
695			`PARAMETER_UNKNOWN`
696			`DEF`
697			`PORT_A_DATA_WIDTH`
698			`1`
699			`PARAMETER_UNKNOWN`
700			`DEF`
701			`PORT_B_ADDRESS_WIDTH`
702			`1`
703			`PARAMETER_UNKNOWN`
704			`DEF`
705			`PORT_B_BYTE_ENABLE_MASK_WIDTH`
706			`1`
707			`PARAMETER_UNKNOWN`
708			`DEF`
709			`PORT_B_DATA_WIDTH`
710			`1`
711			`PARAMETER_UNKNOWN`
712			`DEF`
713			`}`
714			`# used_port {`
715			`address_a0`
716			`address_a1`
717			`address_a2`
718			`address_a3`
719			`address_a4`
720			`address_a5`
721			`address_a6`
722			`clock0`
723			`q_a0`
724			`q_a1`
725			`q_a2`
726			`q_a3`
727			`q_a4`
728			`q_a5`
729			`q_a6`
730			`q_a7`
731			`q_b0`
732			`}`
733			`# memory_file {`
734			`init_file.mif`
735
736			`}`
737			`# end`
738			`# complete`
739