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[/] [lwrisc/] [trunk/] [QU2/] [db/] [altsyncram_hg91.tdf] - Blame information for rev 19

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1 10 mcupro 
--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="NONE" NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_a q_b wren_a
2 
--VERSION_BEGIN 4.2 cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END
3 
 
4 
 
5 
--  Copyright (C) 1988-2002 Altera Corporation
6 
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
7 
--  support information,  device programming or simulation file,  and any other
8 
--  associated  documentation or information  provided by  Altera  or a partner
9 
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
10 
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
11 
--  other  use  of such  megafunction  design,  netlist,  support  information,
12 
--  device programming or simulation file,  or any other  related documentation
13 
--  or information  is prohibited  for  any  other purpose,  including, but not
14 
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
15 
--  any other  silicon devices,  unless such use is  explicitly  licensed under
16 
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
17 
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
18 
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
19 
--  support  information,  device programming or simulation file,  or any other
20 
--  related documentation or information provided by  Altera  or a megafunction
21 
--  partner, remains with Altera, the megafunction partner, or their respective
22 
--  licensors. No other licenses, including any licenses needed under any third
23 
--  party's intellectual property, are provided herein.
24 
 
25 
 
26 
PARAMETERS
27 
(
28 
        PORT_A_ADDRESS_WIDTH = 1,
29 
        PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
30 
        PORT_A_DATA_WIDTH = 1,
31 
        PORT_B_ADDRESS_WIDTH = 1,
32 
        PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
33 
        PORT_B_DATA_WIDTH = 1
34 
);
35 
FUNCTION cyclone_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
36 
WITH (  CONNECTIVITY_CHECKING,  DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS,  INIT_FILE,      INIT_FILE_LAYOUT,       LOGICAL_RAM_NAME,       mem_init0,      mem_init1,      MIXED_PORT_FEED_THROUGH_MODE,   OPERATION_MODE, PORT_A_ADDRESS_CLEAR,   PORT_A_ADDRESS_WIDTH,   PORT_A_BYTE_ENABLE_CLEAR,       PORT_A_BYTE_ENABLE_MASK_WIDTH,  PORT_A_DATA_IN_CLEAR,   PORT_A_DATA_OUT_CLEAR,  PORT_A_DATA_OUT_CLOCK,  PORT_A_DATA_WIDTH,      PORT_A_FIRST_ADDRESS,   PORT_A_FIRST_BIT_NUMBER,        PORT_A_LAST_ADDRESS,    PORT_A_LOGICAL_RAM_DEPTH,       PORT_A_LOGICAL_RAM_WIDTH,       PORT_A_WRITE_ENABLE_CLEAR,      PORT_B_ADDRESS_CLEAR,   PORT_B_ADDRESS_CLOCK,   PORT_B_ADDRESS_WIDTH,   PORT_B_BYTE_ENABLE_CLEAR,       PORT_B_BYTE_ENABLE_CLOCK,       PORT_B_BYTE_ENABLE_MASK_WIDTH,  PORT_B_DATA_IN_CLEAR,   PORT_B_DATA_IN_CLOCK,   PORT_B_DATA_OUT_CLEAR,  PORT_B_DATA_OUT_CLOCK,  PORT_B_DATA_WIDTH,      PORT_B_FIRST_ADDRESS,   PORT_B_FIRST_BIT_NUMBER,        PORT_B_LAST_ADDRESS,    PORT_B_LOGICAL_RAM_DEPTH,       PORT_B_LOGICAL_RAM_WIDTH,       PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR,  PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK,  POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
37 
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
38 
 
39 
--synthesis_resources = M4K 1
40 
SUBDESIGN altsyncram_hg91
41 
(
42 
        address_a[6..0] :       input;
43 
        address_b[6..0] :       input;
44 
        clock0  :       input;
45 
        data_a[7..0]    :       input;
46 
        q_a[7..0]       :       output;
47 
        q_b[7..0]       :       output;
48 
        wren_a  :       input;
49 
)
50 
VARIABLE
51 
        ram_block1a0 : cyclone_ram_block
52 
                WITH (
53 
                        CONNECTIVITY_CHECKING = "OFF",
54 
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
55 
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
56 
                        OPERATION_MODE = "dual_port",
57 
                        PORT_A_ADDRESS_CLEAR = "none",
58 
                        PORT_A_ADDRESS_WIDTH = 7,
59 
                        PORT_A_DATA_IN_CLEAR = "none",
60 
                        PORT_A_DATA_WIDTH = 1,
61 
                        PORT_A_FIRST_ADDRESS = 0,
62 
                        PORT_A_FIRST_BIT_NUMBER = 0,
63 
                        PORT_A_LAST_ADDRESS = 127,
64 
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
65 
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
66 
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
67 
                        PORT_B_ADDRESS_CLEAR = "none",
68 
                        PORT_B_ADDRESS_CLOCK = "clock0",
69 
                        PORT_B_ADDRESS_WIDTH = 7,
70 
                        PORT_B_DATA_WIDTH = 1,
71 
                        PORT_B_FIRST_ADDRESS = 0,
72 
                        PORT_B_FIRST_BIT_NUMBER = 0,
73 
                        PORT_B_LAST_ADDRESS = 127,
74 
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
75 
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
76 
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
77 
                        RAM_BLOCK_TYPE = "auto"
78 
                );
79 
        ram_block1a1 : cyclone_ram_block
80 
                WITH (
81 
                        CONNECTIVITY_CHECKING = "OFF",
82 
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
83 
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
84 
                        OPERATION_MODE = "dual_port",
85 
                        PORT_A_ADDRESS_CLEAR = "none",
86 
                        PORT_A_ADDRESS_WIDTH = 7,
87 
                        PORT_A_DATA_IN_CLEAR = "none",
88 
                        PORT_A_DATA_WIDTH = 1,
89 
                        PORT_A_FIRST_ADDRESS = 0,
90 
                        PORT_A_FIRST_BIT_NUMBER = 1,
91 
                        PORT_A_LAST_ADDRESS = 127,
92 
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
93 
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
94 
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
95 
                        PORT_B_ADDRESS_CLEAR = "none",
96 
                        PORT_B_ADDRESS_CLOCK = "clock0",
97 
                        PORT_B_ADDRESS_WIDTH = 7,
98 
                        PORT_B_DATA_WIDTH = 1,
99 
                        PORT_B_FIRST_ADDRESS = 0,
100 
                        PORT_B_FIRST_BIT_NUMBER = 1,
101 
                        PORT_B_LAST_ADDRESS = 127,
102 
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
103 
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
104 
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
105 
                        RAM_BLOCK_TYPE = "auto"
106 
                );
107 
        ram_block1a2 : cyclone_ram_block
108 
                WITH (
109 
                        CONNECTIVITY_CHECKING = "OFF",
110 
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
111 
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
112 
                        OPERATION_MODE = "dual_port",
113 
                        PORT_A_ADDRESS_CLEAR = "none",
114 
                        PORT_A_ADDRESS_WIDTH = 7,
115 
                        PORT_A_DATA_IN_CLEAR = "none",
116 
                        PORT_A_DATA_WIDTH = 1,
117 
                        PORT_A_FIRST_ADDRESS = 0,
118 
                        PORT_A_FIRST_BIT_NUMBER = 2,
119 
                        PORT_A_LAST_ADDRESS = 127,
120 
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
121 
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
122 
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
123 
                        PORT_B_ADDRESS_CLEAR = "none",
124 
                        PORT_B_ADDRESS_CLOCK = "clock0",
125 
                        PORT_B_ADDRESS_WIDTH = 7,
126 
                        PORT_B_DATA_WIDTH = 1,
127 
                        PORT_B_FIRST_ADDRESS = 0,
128 
                        PORT_B_FIRST_BIT_NUMBER = 2,
129 
                        PORT_B_LAST_ADDRESS = 127,
130 
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
131 
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
132 
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
133 
                        RAM_BLOCK_TYPE = "auto"
134 
                );
135 
        ram_block1a3 : cyclone_ram_block
136 
                WITH (
137 
                        CONNECTIVITY_CHECKING = "OFF",
138 
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
139 
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
140 
                        OPERATION_MODE = "dual_port",
141 
                        PORT_A_ADDRESS_CLEAR = "none",
142 
                        PORT_A_ADDRESS_WIDTH = 7,
143 
                        PORT_A_DATA_IN_CLEAR = "none",
144 
                        PORT_A_DATA_WIDTH = 1,
145 
                        PORT_A_FIRST_ADDRESS = 0,
146 
                        PORT_A_FIRST_BIT_NUMBER = 3,
147 
                        PORT_A_LAST_ADDRESS = 127,
148 
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
149 
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
150 
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
151 
                        PORT_B_ADDRESS_CLEAR = "none",
152 
                        PORT_B_ADDRESS_CLOCK = "clock0",
153 
                        PORT_B_ADDRESS_WIDTH = 7,
154 
                        PORT_B_DATA_WIDTH = 1,
155 
                        PORT_B_FIRST_ADDRESS = 0,
156 
                        PORT_B_FIRST_BIT_NUMBER = 3,
157 
                        PORT_B_LAST_ADDRESS = 127,
158 
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
159 
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
160 
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
161 
                        RAM_BLOCK_TYPE = "auto"
162 
                );
163 
        ram_block1a4 : cyclone_ram_block
164 
                WITH (
165 
                        CONNECTIVITY_CHECKING = "OFF",
166 
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
167 
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
168 
                        OPERATION_MODE = "dual_port",
169 
                        PORT_A_ADDRESS_CLEAR = "none",
170 
                        PORT_A_ADDRESS_WIDTH = 7,
171 
                        PORT_A_DATA_IN_CLEAR = "none",
172 
                        PORT_A_DATA_WIDTH = 1,
173 
                        PORT_A_FIRST_ADDRESS = 0,
174 
                        PORT_A_FIRST_BIT_NUMBER = 4,
175 
                        PORT_A_LAST_ADDRESS = 127,
176 
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
177 
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
178 
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
179 
                        PORT_B_ADDRESS_CLEAR = "none",
180 
                        PORT_B_ADDRESS_CLOCK = "clock0",
181 
                        PORT_B_ADDRESS_WIDTH = 7,
182 
                        PORT_B_DATA_WIDTH = 1,
183 
                        PORT_B_FIRST_ADDRESS = 0,
184 
                        PORT_B_FIRST_BIT_NUMBER = 4,
185 
                        PORT_B_LAST_ADDRESS = 127,
186 
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
187 
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
188 
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
189 
                        RAM_BLOCK_TYPE = "auto"
190 
                );
191 
        ram_block1a5 : cyclone_ram_block
192 
                WITH (
193 
                        CONNECTIVITY_CHECKING = "OFF",
194 
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
195 
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
196 
                        OPERATION_MODE = "dual_port",
197 
                        PORT_A_ADDRESS_CLEAR = "none",
198 
                        PORT_A_ADDRESS_WIDTH = 7,
199 
                        PORT_A_DATA_IN_CLEAR = "none",
200 
                        PORT_A_DATA_WIDTH = 1,
201 
                        PORT_A_FIRST_ADDRESS = 0,
202 
                        PORT_A_FIRST_BIT_NUMBER = 5,
203 
                        PORT_A_LAST_ADDRESS = 127,
204 
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
205 
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
206 
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
207 
                        PORT_B_ADDRESS_CLEAR = "none",
208 
                        PORT_B_ADDRESS_CLOCK = "clock0",
209 
                        PORT_B_ADDRESS_WIDTH = 7,
210 
                        PORT_B_DATA_WIDTH = 1,
211 
                        PORT_B_FIRST_ADDRESS = 0,
212 
                        PORT_B_FIRST_BIT_NUMBER = 5,
213 
                        PORT_B_LAST_ADDRESS = 127,
214 
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
215 
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
216 
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
217 
                        RAM_BLOCK_TYPE = "auto"
218 
                );
219 
        ram_block1a6 : cyclone_ram_block
220 
                WITH (
221 
                        CONNECTIVITY_CHECKING = "OFF",
222 
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
223 
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
224 
                        OPERATION_MODE = "dual_port",
225 
                        PORT_A_ADDRESS_CLEAR = "none",
226 
                        PORT_A_ADDRESS_WIDTH = 7,
227 
                        PORT_A_DATA_IN_CLEAR = "none",
228 
                        PORT_A_DATA_WIDTH = 1,
229 
                        PORT_A_FIRST_ADDRESS = 0,
230 
                        PORT_A_FIRST_BIT_NUMBER = 6,
231 
                        PORT_A_LAST_ADDRESS = 127,
232 
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
233 
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
234 
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
235 
                        PORT_B_ADDRESS_CLEAR = "none",
236 
                        PORT_B_ADDRESS_CLOCK = "clock0",
237 
                        PORT_B_ADDRESS_WIDTH = 7,
238 
                        PORT_B_DATA_WIDTH = 1,
239 
                        PORT_B_FIRST_ADDRESS = 0,
240 
                        PORT_B_FIRST_BIT_NUMBER = 6,
241 
                        PORT_B_LAST_ADDRESS = 127,
242 
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
243 
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
244 
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
245 
                        RAM_BLOCK_TYPE = "auto"
246 
                );
247 
        ram_block1a7 : cyclone_ram_block
248 
                WITH (
249 
                        CONNECTIVITY_CHECKING = "OFF",
250 
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
251 
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
252 
                        OPERATION_MODE = "dual_port",
253 
                        PORT_A_ADDRESS_CLEAR = "none",
254 
                        PORT_A_ADDRESS_WIDTH = 7,
255 
                        PORT_A_DATA_IN_CLEAR = "none",
256 
                        PORT_A_DATA_WIDTH = 1,
257 
                        PORT_A_FIRST_ADDRESS = 0,
258 
                        PORT_A_FIRST_BIT_NUMBER = 7,
259 
                        PORT_A_LAST_ADDRESS = 127,
260 
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
261 
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
262 
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
263 
                        PORT_B_ADDRESS_CLEAR = "none",
264 
                        PORT_B_ADDRESS_CLOCK = "clock0",
265 
                        PORT_B_ADDRESS_WIDTH = 7,
266 
                        PORT_B_DATA_WIDTH = 1,
267 
                        PORT_B_FIRST_ADDRESS = 0,
268 
                        PORT_B_FIRST_BIT_NUMBER = 7,
269 
                        PORT_B_LAST_ADDRESS = 127,
270 
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
271 
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
272 
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
273 
                        RAM_BLOCK_TYPE = "auto"
274 
                );
275 
        address_a_wire[6..0]    : WIRE;
276 
        address_b_wire[6..0]    : WIRE;
277 
 
278 
BEGIN
279 
        ram_block1a[7..0].clk0 = clock0;
280 
        ram_block1a[0].portaaddr[] = ( address_a_wire[6..0]);
281 
        ram_block1a[1].portaaddr[] = ( address_a_wire[6..0]);
282 
        ram_block1a[2].portaaddr[] = ( address_a_wire[6..0]);
283 
        ram_block1a[3].portaaddr[] = ( address_a_wire[6..0]);
284 
        ram_block1a[4].portaaddr[] = ( address_a_wire[6..0]);
285 
        ram_block1a[5].portaaddr[] = ( address_a_wire[6..0]);
286 
        ram_block1a[6].portaaddr[] = ( address_a_wire[6..0]);
287 
        ram_block1a[7].portaaddr[] = ( address_a_wire[6..0]);
288 
        ram_block1a[0].portadatain[] = ( data_a[0..0]);
289 
        ram_block1a[1].portadatain[] = ( data_a[1..1]);
290 
        ram_block1a[2].portadatain[] = ( data_a[2..2]);
291 
        ram_block1a[3].portadatain[] = ( data_a[3..3]);
292 
        ram_block1a[4].portadatain[] = ( data_a[4..4]);
293 
        ram_block1a[5].portadatain[] = ( data_a[5..5]);
294 
        ram_block1a[6].portadatain[] = ( data_a[6..6]);
295 
        ram_block1a[7].portadatain[] = ( data_a[7..7]);
296 
        ram_block1a[7..0].portawe = wren_a;
297 
        ram_block1a[0].portbaddr[] = ( address_b_wire[6..0]);
298 
        ram_block1a[1].portbaddr[] = ( address_b_wire[6..0]);
299 
        ram_block1a[2].portbaddr[] = ( address_b_wire[6..0]);
300 
        ram_block1a[3].portbaddr[] = ( address_b_wire[6..0]);
301 
        ram_block1a[4].portbaddr[] = ( address_b_wire[6..0]);
302 
        ram_block1a[5].portbaddr[] = ( address_b_wire[6..0]);
303 
        ram_block1a[6].portbaddr[] = ( address_b_wire[6..0]);
304 
        ram_block1a[7].portbaddr[] = ( address_b_wire[6..0]);
305 
        ram_block1a[0].portbrewe = B"1";
306 
        ram_block1a[1].portbrewe = B"1";
307 
        ram_block1a[2].portbrewe = B"1";
308 
        ram_block1a[3].portbrewe = B"1";
309 
        ram_block1a[4].portbrewe = B"1";
310 
        ram_block1a[5].portbrewe = B"1";
311 
        ram_block1a[6].portbrewe = B"1";
312 
        ram_block1a[7].portbrewe = B"1";
313 
        address_a_wire[] = address_a[];
314 
        address_b_wire[] = address_b[];
315 
        q_b[] = ( ram_block1a[7].portbdataout[0..0], ram_block1a[6].portbdataout[0..0], ram_block1a[5].portbdataout[0..0], ram_block1a[4].portbdataout[0..0], ram_block1a[3].portbdataout[0..0], ram_block1a[2].portbdataout[0..0], ram_block1a[1].portbdataout[0..0], ram_block1a[0].portbdataout[0..0]);
316 
END;
317 
--VALID FILE

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