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[/] [lwrisc/] [trunk/] [QU2/] [db/] [altsyncram_u8r.tdf] - Blame information for rev 10

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1 10 mcupro 
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="NO" INIT_FILE="init_file.mif" NUMWORDS_A=128 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 address_a clock0 q_a q_b
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--VERSION_BEGIN 4.2 cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END
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--  Copyright (C) 1988-2002 Altera Corporation
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--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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--  support information,  device programming or simulation file,  and any other
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--  associated  documentation or information  provided by  Altera  or a partner
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--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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--  other  use  of such  megafunction  design,  netlist,  support  information,
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--  device programming or simulation file,  or any other  related documentation
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--  or information  is prohibited  for  any  other purpose,  including, but not
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--  limited to  modification,  reverse engineering,  de-compiling, or use  with
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--  any other  silicon devices,  unless such use is  explicitly  licensed under
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--  a separate agreement with  Altera  or a megafunction partner.  Title to the
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--  intellectual property,  including patents,  copyrights,  trademarks,  trade
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--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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--  support  information,  device programming or simulation file,  or any other
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--  related documentation or information provided by  Altera  or a megafunction
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--  partner, remains with Altera, the megafunction partner, or their respective
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--  licensors. No other licenses, including any licenses needed under any third
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--  party's intellectual property, are provided herein.
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PARAMETERS
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(
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        PORT_A_ADDRESS_WIDTH = 1,
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        PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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        PORT_A_DATA_WIDTH = 1,
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        PORT_B_ADDRESS_WIDTH = 1,
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        PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
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        PORT_B_DATA_WIDTH = 1
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);
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FUNCTION cyclone_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
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WITH (  CONNECTIVITY_CHECKING,  DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS,  INIT_FILE,      INIT_FILE_LAYOUT,       LOGICAL_RAM_NAME,       mem_init0,      mem_init1,      MIXED_PORT_FEED_THROUGH_MODE,   OPERATION_MODE, PORT_A_ADDRESS_CLEAR,   PORT_A_ADDRESS_WIDTH,   PORT_A_BYTE_ENABLE_CLEAR,       PORT_A_BYTE_ENABLE_MASK_WIDTH,  PORT_A_DATA_IN_CLEAR,   PORT_A_DATA_OUT_CLEAR,  PORT_A_DATA_OUT_CLOCK,  PORT_A_DATA_WIDTH,      PORT_A_FIRST_ADDRESS,   PORT_A_FIRST_BIT_NUMBER,        PORT_A_LAST_ADDRESS,    PORT_A_LOGICAL_RAM_DEPTH,       PORT_A_LOGICAL_RAM_WIDTH,       PORT_A_WRITE_ENABLE_CLEAR,      PORT_B_ADDRESS_CLEAR,   PORT_B_ADDRESS_CLOCK,   PORT_B_ADDRESS_WIDTH,   PORT_B_BYTE_ENABLE_CLEAR,       PORT_B_BYTE_ENABLE_CLOCK,       PORT_B_BYTE_ENABLE_MASK_WIDTH,  PORT_B_DATA_IN_CLEAR,   PORT_B_DATA_IN_CLOCK,   PORT_B_DATA_OUT_CLEAR,  PORT_B_DATA_OUT_CLOCK,  PORT_B_DATA_WIDTH,      PORT_B_FIRST_ADDRESS,   PORT_B_FIRST_BIT_NUMBER,        PORT_B_LAST_ADDRESS,    PORT_B_LOGICAL_RAM_DEPTH,       PORT_B_LOGICAL_RAM_WIDTH,       PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR,  PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK,  POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = M4K 1
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SUBDESIGN altsyncram_u8r
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(
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        address_a[6..0] :       input;
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        clock0  :       input;
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        q_a[7..0]       :       output;
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        q_b[0..0]       :       output;
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)
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VARIABLE
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        ram_block1a0 : cyclone_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "init_file.mif",
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                        INIT_FILE_LAYOUT = "port_a",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        OPERATION_MODE = "rom",
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                        PORT_A_ADDRESS_CLEAR = "none",
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                        PORT_A_ADDRESS_WIDTH = 7,
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                        PORT_A_DATA_OUT_CLEAR = "none",
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                        PORT_A_DATA_OUT_CLOCK = "none",
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 0,
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                        PORT_A_LAST_ADDRESS = 127,
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                        PORT_A_LOGICAL_RAM_DEPTH = 128,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        RAM_BLOCK_TYPE = "auto"
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                );
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        ram_block1a1 : cyclone_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "init_file.mif",
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                        INIT_FILE_LAYOUT = "port_a",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        OPERATION_MODE = "rom",
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                        PORT_A_ADDRESS_CLEAR = "none",
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                        PORT_A_ADDRESS_WIDTH = 7,
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                        PORT_A_DATA_OUT_CLEAR = "none",
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                        PORT_A_DATA_OUT_CLOCK = "none",
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 1,
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                        PORT_A_LAST_ADDRESS = 127,
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                        PORT_A_LOGICAL_RAM_DEPTH = 128,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        RAM_BLOCK_TYPE = "auto"
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                );
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        ram_block1a2 : cyclone_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "init_file.mif",
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                        INIT_FILE_LAYOUT = "port_a",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        OPERATION_MODE = "rom",
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                        PORT_A_ADDRESS_CLEAR = "none",
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                        PORT_A_ADDRESS_WIDTH = 7,
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                        PORT_A_DATA_OUT_CLEAR = "none",
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                        PORT_A_DATA_OUT_CLOCK = "none",
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 2,
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                        PORT_A_LAST_ADDRESS = 127,
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                        PORT_A_LOGICAL_RAM_DEPTH = 128,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        RAM_BLOCK_TYPE = "auto"
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                );
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        ram_block1a3 : cyclone_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "init_file.mif",
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                        INIT_FILE_LAYOUT = "port_a",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        OPERATION_MODE = "rom",
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                        PORT_A_ADDRESS_CLEAR = "none",
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                        PORT_A_ADDRESS_WIDTH = 7,
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                        PORT_A_DATA_OUT_CLEAR = "none",
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                        PORT_A_DATA_OUT_CLOCK = "none",
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 3,
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                        PORT_A_LAST_ADDRESS = 127,
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                        PORT_A_LOGICAL_RAM_DEPTH = 128,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        RAM_BLOCK_TYPE = "auto"
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                );
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        ram_block1a4 : cyclone_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "init_file.mif",
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                        INIT_FILE_LAYOUT = "port_a",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        OPERATION_MODE = "rom",
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                        PORT_A_ADDRESS_CLEAR = "none",
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                        PORT_A_ADDRESS_WIDTH = 7,
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                        PORT_A_DATA_OUT_CLEAR = "none",
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                        PORT_A_DATA_OUT_CLOCK = "none",
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 4,
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                        PORT_A_LAST_ADDRESS = 127,
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                        PORT_A_LOGICAL_RAM_DEPTH = 128,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        RAM_BLOCK_TYPE = "auto"
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                );
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        ram_block1a5 : cyclone_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "init_file.mif",
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                        INIT_FILE_LAYOUT = "port_a",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        OPERATION_MODE = "rom",
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                        PORT_A_ADDRESS_CLEAR = "none",
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                        PORT_A_ADDRESS_WIDTH = 7,
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                        PORT_A_DATA_OUT_CLEAR = "none",
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                        PORT_A_DATA_OUT_CLOCK = "none",
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 5,
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                        PORT_A_LAST_ADDRESS = 127,
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                        PORT_A_LOGICAL_RAM_DEPTH = 128,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        RAM_BLOCK_TYPE = "auto"
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                );
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        ram_block1a6 : cyclone_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "init_file.mif",
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                        INIT_FILE_LAYOUT = "port_a",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        OPERATION_MODE = "rom",
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                        PORT_A_ADDRESS_CLEAR = "none",
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                        PORT_A_ADDRESS_WIDTH = 7,
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                        PORT_A_DATA_OUT_CLEAR = "none",
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                        PORT_A_DATA_OUT_CLOCK = "none",
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 6,
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                        PORT_A_LAST_ADDRESS = 127,
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                        PORT_A_LOGICAL_RAM_DEPTH = 128,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        RAM_BLOCK_TYPE = "auto"
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                );
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        ram_block1a7 : cyclone_ram_block
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                WITH (
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "init_file.mif",
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                        INIT_FILE_LAYOUT = "port_a",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        OPERATION_MODE = "rom",
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                        PORT_A_ADDRESS_CLEAR = "none",
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                        PORT_A_ADDRESS_WIDTH = 7,
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                        PORT_A_DATA_OUT_CLEAR = "none",
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                        PORT_A_DATA_OUT_CLOCK = "none",
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 7,
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                        PORT_A_LAST_ADDRESS = 127,
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                        PORT_A_LOGICAL_RAM_DEPTH = 128,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        RAM_BLOCK_TYPE = "auto"
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                );
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BEGIN
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        ram_block1a[7..0].clk0 = clock0;
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        ram_block1a[0].portaaddr[] = ( address_a[6..0]);
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        ram_block1a[1].portaaddr[] = ( address_a[6..0]);
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        ram_block1a[2].portaaddr[] = ( address_a[6..0]);
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        ram_block1a[3].portaaddr[] = ( address_a[6..0]);
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        ram_block1a[4].portaaddr[] = ( address_a[6..0]);
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        ram_block1a[5].portaaddr[] = ( address_a[6..0]);
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        ram_block1a[6].portaaddr[] = ( address_a[6..0]);
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        ram_block1a[7].portaaddr[] = ( address_a[6..0]);
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        q_a[] = ( ram_block1a[7].portadataout[0..0], ram_block1a[6].portadataout[0..0], ram_block1a[5].portadataout[0..0], ram_block1a[4].portadataout[0..0], ram_block1a[3].portadataout[0..0], ram_block1a[2].portadataout[0..0], ram_block1a[1].portadataout[0..0], ram_block1a[0].portadataout[0..0]);
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END;
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--VALID FILE

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