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[/] [lwrisc/] [trunk/] [RTL/] [altera/] [rom1024x12.v] - Blame information for rev 7

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1 7 mcupro
// megafunction wizard: %ROM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram 
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// ============================================================
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// File Name: rom1024x12.v
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// Megafunction Name(s):
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//                      altsyncram
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 4.2 Build 157 12/07/2004 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2004 Altera Corporation
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//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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//support information,  device programming or simulation file,  and any other
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//associated  documentation or information  provided by  Altera  or a partner
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//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
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//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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//other  use  of such  megafunction  design,  netlist,  support  information,
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//device programming or simulation file,  or any other  related documentation
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//or information  is prohibited  for  any  other purpose,  including, but not
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//limited to  modification,  reverse engineering,  de-compiling, or use  with
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//any other  silicon devices,  unless such use is  explicitly  licensed under
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//a separate agreement with  Altera  or a megafunction partner.  Title to the
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//intellectual property,  including patents,  copyrights,  trademarks,  trade
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//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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//support  information,  device programming or simulation file,  or any other
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//related documentation or information provided by  Altera  or a megafunction
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//partner, remains with Altera, the megafunction partner, or their respective
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//licensors. No other licenses, including any licenses needed under any third
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//party's intellectual property, are provided herein.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module rom1024x12 (
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        address,
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        clock,
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        q);
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        input   [9:0]  address;
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        input     clock;
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        output  [11:0]  q;
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        wire [11:0] sub_wire0;
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        wire [11:0] q = sub_wire0[11:0];
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        altsyncram      altsyncram_component (
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                                .clock0 (clock),
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                                .address_a (address),
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                                .q_a (sub_wire0)
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                                // synopsys translate_off
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                                ,
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                                .aclr0 (),
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                                .aclr1 (),
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                                .address_b (),
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                                .addressstall_a (),
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                                .addressstall_b (),
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                                .byteena_a (),
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                                .byteena_b (),
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                                .clock1 (),
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                                .clocken0 (),
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                                .clocken1 (),
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                                .data_a (),
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                                .data_b (),
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                                .q_b (),
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                                .rden_b (),
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                                .wren_a (),
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                                .wren_b ()
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                                // synopsys translate_on
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                                );
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        defparam
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                altsyncram_component.intended_device_family = "Cyclone",
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                altsyncram_component.width_a = 12,
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                altsyncram_component.widthad_a = 10,
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                altsyncram_component.numwords_a = 1024,
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                altsyncram_component.operation_mode = "ROM",
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                altsyncram_component.outdata_reg_a = "UNREGISTERED",
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                altsyncram_component.address_aclr_a = "NONE",
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                altsyncram_component.outdata_aclr_a = "NONE",
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                altsyncram_component.width_byteena_a = 1,
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                altsyncram_component.init_file = "init_file.mif",
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                altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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                altsyncram_component.lpm_type = "altsyncram";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: WidthData NUMERIC "12"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "init_file.mif"
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// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: CONSTANT: INIT_FILE STRING "init_file.mif"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
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// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
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// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
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// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom1024.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom1024.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom1024.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom1024.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom1024_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom1024_bb.v FALSE

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